JPS6399428U - - Google Patents
Info
- Publication number
- JPS6399428U JPS6399428U JP19618386U JP19618386U JPS6399428U JP S6399428 U JPS6399428 U JP S6399428U JP 19618386 U JP19618386 U JP 19618386U JP 19618386 U JP19618386 U JP 19618386U JP S6399428 U JPS6399428 U JP S6399428U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- gate
- gates
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
第１図は本考案の原理ブロツク図であり、第２
図は本考案の１実施例であり、第３図は従来のＣ
ＭＯＳ回路であり、第４図は従来のＣＭＯＳ回路
の動作波形例図である。
図において、１……入力ゲート、２……内部回
路、３……出力ゲート、４……信号設定手段、３
３……クランプダイオード、３４……伝送ライン
。
Figure 1 is a block diagram of the principle of the present invention;
The figure shows one embodiment of the present invention, and Figure 3 shows the conventional C
This is a MOS circuit, and FIG. 4 is a diagram showing an example of operating waveforms of a conventional CMOS circuit. In the figure, 1...input gate, 2...internal circuit, 3...output gate, 4...signal setting means, 3
3...clamp diode, 34...transmission line.
Claims (1)
む複数の出力ゲート３―１を備えたコンプリメン
タルＭＯＳ回路において、 前記入力ゲート１の入力端に出力端を接続した
前記出力ゲート３―１と、 該出力ゲート３―１をハイインピーダンス状態
にする信号設定手段３―２を備えたことを特徴と
するコンプリメンタルＭＯＳ入力回路。[Claims for Utility Model Registration] In a complementary MOS circuit comprising a plurality of input gates 1 and a plurality of output gates 3-1 including diodes 3-3, an output terminal is connected to the input terminal of the input gate 1. A complementary MOS input circuit comprising: the output gate 3-1; and signal setting means 3-2 for setting the output gate 3-1 to a high impedance state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19618386U JPS6399428U (en) | 1986-12-19 | 1986-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19618386U JPS6399428U (en) | 1986-12-19 | 1986-12-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6399428U true JPS6399428U (en) | 1988-06-28 |
Family
ID=31154770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19618386U Pending JPS6399428U (en) | 1986-12-19 | 1986-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399428U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054519A (en) * | 1983-09-05 | 1985-03-29 | Matsushita Electric Ind Co Ltd | Input and output circuit |
| JPS6121139B2 (en) * | 1982-04-30 | 1986-05-26 | Kasai Kogyo Kk |
-
1986
- 1986-12-19 JP JP19618386U patent/JPS6399428U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6121139B2 (en) * | 1982-04-30 | 1986-05-26 | Kasai Kogyo Kk | |
| JPS6054519A (en) * | 1983-09-05 | 1985-03-29 | Matsushita Electric Ind Co Ltd | Input and output circuit |