JPS63100851U - - Google Patents
Info
- Publication number
- JPS63100851U JPS63100851U JP19563386U JP19563386U JPS63100851U JP S63100851 U JPS63100851 U JP S63100851U JP 19563386 U JP19563386 U JP 19563386U JP 19563386 U JP19563386 U JP 19563386U JP S63100851 U JPS63100851 U JP S63100851U
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- polarity
- positive
- semiconductor integrated
- arranged symmetrically
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Structure Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク回路図、
第２図は第１図の中の切換回路の回路図、第３図
は本考案の他の実施例のブロツク回路図である。
１……集積回路基板、２ａ，２ｂ，３……同一
回路、４……切換回路、５，６，９，１０……電
源ライン、７，８，１１，１８……配線、Ｔ１〜
Ｔ８，７，８……外部端子、ＴＴ……外部端子列
。
FIG. 1 is a block circuit diagram of an embodiment of the present invention.
FIG. 2 is a circuit diagram of the switching circuit shown in FIG. 1, and FIG. 3 is a block circuit diagram of another embodiment of the present invention. 1... Integrated circuit board, 2a, 2b, 3... Same circuit, 4... Switching circuit, 5, 6, 9, 10... Power line, 7, 8, 11, 18... Wiring, T1~
T8, 7, 8...External terminal, TT...External terminal row.
Claims (1)
回路において、前記同一回路に必要な入出力等の
端子を対称配列とし、加えて対称配列された２つ
の端子を有し、さらに、この２端子および前記同
一回路の正および負の電源ライン間に、極性判別
機能並びに判別後の極性に応じて同一回路の正お
よび負の電源ラインにこれらの極性と一致した電
源を加えるための切換回路を有していることを特
徴とする半導体集積回路。 In a semiconductor integrated circuit composed of an even number of identical circuits, terminals such as input/output necessary for the identical circuits are arranged symmetrically, and in addition have two terminals arranged symmetrically, and furthermore, these two terminals and Between the positive and negative power lines of the same circuit, there is provided a polarity discrimination function and a switching circuit for applying power matching the polarity to the positive and negative power lines of the same circuit according to the determined polarity. A semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19563386U JPS63100851U (en) | 1986-12-18 | 1986-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19563386U JPS63100851U (en) | 1986-12-18 | 1986-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63100851U true JPS63100851U (en) | 1988-06-30 |
Family
ID=31153696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19563386U Pending JPS63100851U (en) | 1986-12-18 | 1986-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63100851U (en) |
-
1986
- 1986-12-18 JP JP19563386U patent/JPS63100851U/ja active Pending
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