JPH01133823U - - Google Patents
Info
- Publication number
- JPH01133823U JPH01133823U JP3058288U JP3058288U JPH01133823U JP H01133823 U JPH01133823 U JP H01133823U JP 3058288 U JP3058288 U JP 3058288U JP 3058288 U JP3058288 U JP 3058288U JP H01133823 U JPH01133823 U JP H01133823U
- Authority
- JP
- Japan
- Prior art keywords
- buffer circuits
- output
- unit buffer
- inverters
- buffer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案による出力バツフア回路の一実
施例の構成を示す結線図、第２図は本考案の一実
施例の出力電流を示す波形図、第３図は従来の出
力バツフア回路の構成を示す結線図、第４図は従
来例の出力電流の波形図、第５図は既提案による
出力バツフア回路の構成例を示す結線図である。
１０，２０は単位バツフア回路、１１，１２は
ＰチヤンネルＭＯＳトランジスタ、１２，２２は
ＮチヤンネルＭＯＳトランジスタ、３１，３２は
インバータである。
Figure 1 is a wiring diagram showing the configuration of an embodiment of the output buffer circuit according to the present invention, Figure 2 is a waveform diagram showing the output current of the embodiment of the invention, and Figure 3 is the configuration of a conventional output buffer circuit. 4 is a waveform diagram of an output current in a conventional example, and FIG. 5 is a wiring diagram showing an example of the configuration of an output buffer circuit according to an existing proposal. 10 and 20 are unit buffer circuits, 11 and 12 are P-channel MOS transistors, 12 and 22 are N-channel MOS transistors, and 31 and 32 are inverters.
Claims (1)
複数の単位バツフア回路の各出力端子を共通に接
続すると共に、 上記複数の単位バツフア回路の各入力端子を偶
数個のインバータを介して接続してなる出力バツ
フア回路。[Claims for Utility Model Registration] Each output terminal of a plurality of unit buffer circuits each consisting of a pair of complementary transistors is connected in common, and each input terminal of the plurality of unit buffer circuits is connected to an even number of inverters. Connect through the output buffer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3058288U JPH01133823U (en) | 1988-03-08 | 1988-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3058288U JPH01133823U (en) | 1988-03-08 | 1988-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133823U true JPH01133823U (en) | 1989-09-12 |
Family
ID=31255765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3058288U Pending JPH01133823U (en) | 1988-03-08 | 1988-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133823U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8310296B2 (en) | 2008-07-18 | 2012-11-13 | Denso Corporation | Driving transistor control circuit |
-
1988
- 1988-03-08 JP JP3058288U patent/JPH01133823U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8310296B2 (en) | 2008-07-18 | 2012-11-13 | Denso Corporation | Driving transistor control circuit |