JPS63162549U - - Google Patents
Info
- Publication number
- JPS63162549U JPS63162549U JP5434287U JP5434287U JPS63162549U JP S63162549 U JPS63162549 U JP S63162549U JP 5434287 U JP5434287 U JP 5434287U JP 5434287 U JP5434287 U JP 5434287U JP S63162549 U JPS63162549 U JP S63162549U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- semiconductor integrated
- circuit device
- integrated circuit
- voltage supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案の半導体集積回路装置の一実施
例の構成を示す図、第２図は第１図のＣＭＯＳイ
ンバータ１０，２０の入出力特性図、第３図は他
の実施例の構成を示す図、第４図は従来例の構成
を示す図である。
１，８……半導体集積回路装置、２，３……ワ
イヤ接続パツド、４……電源電圧供給線、５……
基準電圧供給線、６，７……ワイヤ、１０〜６０
……ＣＭＯＳインバータ、Ｍ１，Ｍ３，Ｍ５，Ｍ
７，Ｍ９，Ｍ１１……ＰＭＯＳトランジスタ、Ｍ
２，Ｍ４，Ｍ６，Ｍ８，Ｍ１０，Ｍ１２……ＮＭ
ＯＳトランジスタ、Ｒ１〜Ｒ１８……等価インピ
ーダンス、ＶＤＤ……電源電圧、ＶＩＮ……入力
電圧、ＶＯＵＴ……出力電圧。
FIG. 1 is a diagram showing the configuration of one embodiment of the semiconductor integrated circuit device of the present invention, FIG. 2 is an input/output characteristic diagram of the CMOS inverters 10 and 20 of FIG. 1, and FIG. 3 is the configuration of another embodiment. FIG. 4 is a diagram showing the configuration of a conventional example. 1, 8... Semiconductor integrated circuit device, 2, 3... Wire connection pad, 4... Power supply voltage supply line, 5...
Reference voltage supply line, 6, 7...Wire, 10-60
...CMOS inverter, M 1 , M 3 , M 5 , M
7 , M9 , M11 ...PMOS transistor, M
2 , M4 , M6 , M8 , M10 , M12 ...NM
OS transistor, R1 to R18 ...Equivalent impedance, VDD...Power supply voltage, VIN...Input voltage, VOUT...Output voltage.
Claims (1)
路が集積された半導体集積回路装置において、 ワイヤ接続パツドから各ゲートに至る間のイン
ピーダンスがそれぞれ等しい動作電圧供給線を有
することを特徴とする半導体集積回路装置。 ２ 前記ゲートはＣＭＯＳインバータゲートであ
る実用新案登録請求の範囲第１項に記載の半導体
集積回路装置。[Claims for Utility Model Registration] 1. A semiconductor integrated circuit device in which a gate circuit configured by connecting gates in multiple stages is integrated, which has operating voltage supply lines with equal impedance from a wire connection pad to each gate. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein the gate is a CMOS inverter gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5434287U JPS63162549U (en) | 1987-04-09 | 1987-04-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5434287U JPS63162549U (en) | 1987-04-09 | 1987-04-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63162549U true JPS63162549U (en) | 1988-10-24 |
Family
ID=30881247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5434287U Pending JPS63162549U (en) | 1987-04-09 | 1987-04-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63162549U (en) |
-
1987
- 1987-04-09 JP JP5434287U patent/JPS63162549U/ja active Pending
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