JPH01123362U - - Google Patents
Info
- Publication number
- JPH01123362U JPH01123362U JP1912388U JP1912388U JPH01123362U JP H01123362 U JPH01123362 U JP H01123362U JP 1912388 U JP1912388 U JP 1912388U JP 1912388 U JP1912388 U JP 1912388U JP H01123362 U JPH01123362 U JP H01123362U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistors
- mos transistor
- power supply
- mos
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図は、本考案の一実施例を示す基板電位発
生回路図、第２図は、第１図の回路に於ける出力
（ＶＢＢ）の電源電圧依存性を示す図、第３図は
、従来の基板電位発生回路図、第４図は、従来の
基板電位の電源電圧依存性を示す図である。
Ｔｒ１〜Ｔｒ４：ＭＯＳトランジスタ、Ｔｒ５
：デプリージヨンＭＯＳトランジスタ、Ｃ：キヤ
パシタ。
FIG. 1 is a substrate potential generation circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the power supply voltage dependence of the output (VBB) in the circuit of FIG. 1, and FIG. FIG. 4, a conventional substrate potential generation circuit diagram, is a diagram showing the dependence of the conventional substrate potential on the power supply voltage. T r1 to T r4 : MOS transistor, T r5
: depletion MOS transistor, C: capacitor.
Claims (1)
タと、 上記ＭＯＳトランジスタと電源との間に挿入さ
れたデプリージヨンＭＯＳトランジスタと、 出力端と他方の電源間に直列に接続された第３
及び第４ＭＯＳトランジスタと、 上記第１及び第２ＭＯＳトランジスタの接続点
と第３及び第４ＭＯＳトランジスタの接続点間に
挿入されたキヤパシタとを備えてなることを特徴
とする半導体装置の基板電位発生回路。[Claims for Utility Model Registration] First and second MOS transistors connected in series; a depletion MOS transistor inserted between the MOS transistors and the power supply; and a depletion MOS transistor connected in series between the output terminal and the other power supply. Third
and a fourth MOS transistor; and a capacitor inserted between a connection point between the first and second MOS transistors and a connection point between the third and fourth MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1912388U JPH01123362U (en) | 1988-02-16 | 1988-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1912388U JPH01123362U (en) | 1988-02-16 | 1988-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123362U true JPH01123362U (en) | 1989-08-22 |
Family
ID=31234355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1912388U Pending JPH01123362U (en) | 1988-02-16 | 1988-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123362U (en) |
-
1988
- 1988-02-16 JP JP1912388U patent/JPH01123362U/ja active Pending
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