JPS5810114U - integrated circuit - Google Patents

integrated circuit

Info

Publication number
JPS5810114U
JPS5810114U JP10047281U JP10047281U JPS5810114U JP S5810114 U JPS5810114 U JP S5810114U JP 10047281 U JP10047281 U JP 10047281U JP 10047281 U JP10047281 U JP 10047281U JP S5810114 U JPS5810114 U JP S5810114U
Authority
JP
Japan
Prior art keywords
integrated circuit
differential
monitoring
pair
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10047281U
Other languages
Japanese (ja)
Inventor
秀雄 高橋
義一 加藤
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP10047281U priority Critical patent/JPS5810114U/en
Publication of JPS5810114U publication Critical patent/JPS5810114U/en
Pending legal-status Critical Current

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  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は被トリミング回路を含む基準電圧発生回路を示
す回路図である。なお、図において１．２・・・ＭＯＳ
）ランジスタ、３・・・バイアス電流源、４．５・・・
負荷、６・・・増幅器、７，１２・・・端子ミ８，９・
・・電源端子、１０・・・被トリミング回路、１１１．
１１゜、・・・、１１ｎ・・・トリミング端子。FIG. 1 is a circuit diagram showing a reference voltage generation circuit including a circuit to be trimmed. In addition, in the figure, 1.2...MOS
) transistor, 3... bias current source, 4.5...
Load, 6... Amplifier, 7, 12... Terminal Mi 8, 9.
. . . Power supply terminal, 10 . . . Circuit to be trimmed, 111.
11°,..., 11n...Trimming terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 少なくとも一対の差動トランジスタを有する集積回路に
おいて、該差動トラシジスタのゲート電位を監視しうる
端子をもうけた集積回路。An integrated circuit having at least one pair of differential transistors, the integrated circuit having a terminal capable of monitoring a gate potential of the differential transistor.
JP10047281U 1981-07-06 1981-07-06 integrated circuit Pending JPS5810114U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10047281U JPS5810114U (en) 1981-07-06 1981-07-06 integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10047281U JPS5810114U (en) 1981-07-06 1981-07-06 integrated circuit

Publications (1)

Publication Number Publication Date
JPS5810114U true JPS5810114U (en) 1983-01-22

Family

ID=29895159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10047281U Pending JPS5810114U (en) 1981-07-06 1981-07-06 integrated circuit

Country Status (1)

Country Link
JP (1) JPS5810114U (en)

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