JPS615032U - Initial setting circuit - Google Patents
Initial setting circuitInfo
- Publication number
- JPS615032U JPS615032U JP8971684U JP8971684U JPS615032U JP S615032 U JPS615032 U JP S615032U JP 8971684 U JP8971684 U JP 8971684U JP 8971684 U JP8971684 U JP 8971684U JP S615032 U JPS615032 U JP S615032U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- initial setting
- setting circuit
- drain
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第1図は従来例を示す回路図、第2図a, bは第1図
に示された回路図の動作を示す波形図、第3図は本考案
の実施例を示す回路図、第4図a,bは第3図に示され
た実施例の動作を示す波形図、第5図は本考案の他の実
施例を示す回路図である。
6.11−・・第1のMOsトランジスタ、7,12・
・・第1のコンデンサ、8,13・・・第2のMOSト
ランジスタ、9.14・・・第2のコンデンサ、10,
15・・・インバータ。[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 a and b are waveform diagrams showing the operation of the circuit diagram shown in Fig. 1, and Fig. 3 is an embodiment of the present invention. 4a and 4b are waveform diagrams showing the operation of the embodiment shown in FIG. 3, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. 6.11--first MOs transistor, 7,12-
...First capacitor, 8,13...Second MOS transistor, 9.14...Second capacitor, 10,
15...Inverter.
Claims (1)
タと該第1のMOSトランジスタのドレインに一端が接
続された第1のコンデンサが電源及び接地間に直列接続
され、且つ、前記第1のMOS}ランジスタのゲート及
びドレインの接続点にゲートが接続された第2のMOS
トランジスタと該第2のMOSトランジスタのトレイン
に一端が接続された第2のコンデンサとが電源及び接地
間に接続されて成る初期設定回路。A first MOS transistor whose gate is connected to the drain and a first capacitor whose one end is connected to the drain of the first MOS transistor are connected in series between a power supply and ground, and the first MOS transistor a second MOS whose gate is connected to the connection point of the gate and drain of
An initialization circuit comprising a transistor and a second capacitor, one end of which is connected to the second MOS transistor train, connected between a power supply and ground.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8971684U JPS615032U (en) | 1984-06-15 | 1984-06-15 | Initial setting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8971684U JPS615032U (en) | 1984-06-15 | 1984-06-15 | Initial setting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS615032U true JPS615032U (en) | 1986-01-13 |
Family
ID=30644054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8971684U Pending JPS615032U (en) | 1984-06-15 | 1984-06-15 | Initial setting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS615032U (en) |
-
1984
- 1984-06-15 JP JP8971684U patent/JPS615032U/en active Pending
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