JPS619929U - Power-on detection/memory circuit - Google Patents
Power-on detection/memory circuitInfo
- Publication number
- JPS619929U JPS619929U JP9360484U JP9360484U JPS619929U JP S619929 U JPS619929 U JP S619929U JP 9360484 U JP9360484 U JP 9360484U JP 9360484 U JP9360484 U JP 9360484U JP S619929 U JPS619929 U JP S619929U
- Authority
- JP
- Japan
- Prior art keywords
- power
- detection
- memory circuit
- resistor
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図および第３図はそれぞれ本考案の実施例
を示す回路図である。
１０・・・・・・双安定回路、２０・・・・・・コンデ
ンサ、３０・・・・・・抵抗素子、１１・・・・・・Ｎ
ＯＲゲート、１２・・・・・・ＮＯＲゲート、１３・・
・・・・バツファインバータ、３０’，３０″・・・・
・・ＭＯＳトランジスタ、２０′・・・・・・コンデン
サ。FIG. 1, FIG. 2, and FIG. 3 are circuit diagrams each showing an embodiment of the present invention. 10... Bistable circuit, 20... Capacitor, 30... Resistance element, 11... N
OR gate, 12...NOR gate, 13...
...X fine inverter, 30', 30''...
...MOS transistor, 20'...capacitor.
Claims (2)
の直列回路と前記コンデンサと前記抵抗との接続点にセ
ット端子が接続されたセット及びリセット状態を設定で
きる双安定回路とを有することを特徴とする電源投入検
出・記憶回路。(1) It has a series circuit of a capacitor and a resistor connected in series between power supply terminals, and a bistable circuit capable of setting a set and reset state in which a set terminal is connected to a connection point between the capacitor and the resistor. Features a power-on detection/memory circuit.
ドレイン間インピーダンスを用いたことを特徴トする実
用新案登録請求の範囲第１項記載の電源投入検出・記憶
回路。(2) The resistor is the source Φ of the MOS transistor
A power-on detection/storage circuit according to claim 1, characterized in that a drain-to-drain impedance is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9360484U JPS619929U (en) | 1984-06-22 | 1984-06-22 | Power-on detection/memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9360484U JPS619929U (en) | 1984-06-22 | 1984-06-22 | Power-on detection/memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS619929U true JPS619929U (en) | 1986-01-21 |
Family
ID=30651433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9360484U Pending JPS619929U (en) | 1984-06-22 | 1984-06-22 | Power-on detection/memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS619929U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01157820U (en) * | 1988-04-20 | 1989-10-31 |
-
1984
- 1984-06-22 JP JP9360484U patent/JPS619929U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01157820U (en) * | 1988-04-20 | 1989-10-31 |
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