JPS6340029U - - Google Patents
Info
- Publication number
- JPS6340029U JPS6340029U JP1986133923U JP13392386U JPS6340029U JP S6340029 U JPS6340029 U JP S6340029U JP 1986133923 U JP1986133923 U JP 1986133923U JP 13392386 U JP13392386 U JP 13392386U JP S6340029 U JPS6340029 U JP S6340029U
- Authority
- JP
- Japan
- Prior art keywords
- series
- circuit
- delay circuit
- inverter
- inverter circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Pulse Circuits (AREA)
Description
第１図及び第３図は夫々本考案になる遅延回路
の第１実施例を示すブロツク系統図及びその動作
説明用信号波形図、第２図は本考案回路の要部の
一実施例を示す回路系統図、第４図は本考案回路
の第２実施例を示すブロツク系統図、第５図及び
第６図は夫々インバータ回路を偶数段直列接続し
た多段回路を用いた場合の一例のブロツク系統図
及びその動作説明用信号波形図である。
１ａ，１ｂ，２１ａ，２１ｂ，１―１〜１―ｍ
…多段回路、ＴＡ１〜ＴＡＫ…ｐチヤンネルＭＯ
Ｓトランジスタ、ＴＢ１〜ＴＢＫ…ｎチヤンネル
ＭＯＳトランジスタ。
1 and 3 are block diagrams showing a first embodiment of the delay circuit of the present invention and signal waveform diagrams for explaining its operation, and FIG. 2 shows an embodiment of the essential parts of the circuit of the present invention. Circuit system diagram: Figure 4 is a block system diagram showing a second embodiment of the circuit of the present invention, and Figures 5 and 6 are example block systems using a multi-stage circuit in which an even number of stages of inverter circuits are connected in series. FIG. 2 is a diagram and a signal waveform diagram for explaining its operation. 1a, 1b, 21a, 21b, 1- 1 ~ 1- m
...Multi-stage circuit, TA 1 ~ TAK...p channel MO
S transistor, TB1 to TBK...n channel MOS transistor.
Claims (1)
る一の多段回路を一の入力端子及び一の出力端子
間に複数個直列に接続してなる構成の遅延回路。 (2) 該インバータ回路は、ＣＭＯＳインバータ
回路である実用新案登録請求の範囲第１項記載の
遅延回路。[Claims for Utility Model Registration] (1) A delay circuit configured by connecting a plurality of multi-stage circuits in series between one input terminal and one output terminal, each of which is made up of an odd number of inverter circuits connected in series. . (2) The delay circuit according to claim 1, wherein the inverter circuit is a CMOS inverter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986133923U JPS6340029U (en) | 1986-09-01 | 1986-09-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986133923U JPS6340029U (en) | 1986-09-01 | 1986-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340029U true JPS6340029U (en) | 1988-03-15 |
Family
ID=31034682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986133923U Pending JPS6340029U (en) | 1986-09-01 | 1986-09-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340029U (en) |
-
1986
- 1986-09-01 JP JP1986133923U patent/JPS6340029U/ja active Pending
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