JPS63171029U

JPS63171029U -

Info

Publication number: JPS63171029U
Application number: JP6470287U
Authority: JP
Priority date: 1987-04-28
Filing date: 1987-04-28
Publication date: 1988-11-08

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による半導体装置
を示す構成図、第２図は第１図の各部における動
作を示す波形図、第３図は従来の半導体装置を示
す構成図、第４図は第３図の各部における動作を
示す波形図である。１ａ，１ｂ，１ｃはバツフア回路（回路素子）
、２ａ，２ｂ，２ｃは入力端子、３ａ，３ｂ，３
ｃは出力端子、４は電源端子、５は接地端子、６
はパツケージ、７ｂ，７ｃは遅延回路。なお、図
中、同一符号は同一又は相当部分を示す。 FIG. 1 is a configuration diagram showing a semiconductor device according to an embodiment of this invention, FIG. 2 is a waveform diagram showing the operation of each part of FIG. 1, FIG. 3 is a configuration diagram showing a conventional semiconductor device, and FIG. 4 3 is a waveform chart showing the operation of each part in FIG. 3. FIG. 1a, 1b, 1c are buffer circuits (circuit elements)
, 2a, 2b, 2c are input terminals, 3a, 3b, 3
c is the output terminal, 4 is the power terminal, 5 is the ground terminal, 6
is a package, and 7b and 7c are delay circuits. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

補正昭６３．５．７実用新案登録請求の範囲を次のように補正する
。Amendment May 7, 1983 The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】 (1) 入力が同時に遷移すると出力も同時に遷移
する複数の回路素子を出力段に備え、上記各回路
素子が共通の電源により駆動される半導体装置に
おいて、上記各回路素子の出力を独立に制御する
信号線上にそれぞれ信号遅延時間の異なる遅延回
路を備えたことを特徴とする半導体装置。 (2) 遅延回路は、複数の回路素子のうち１部又
は全回路素子の入力信号線上に備えられているこ
とを特徴とする実用新案登録請求の範囲第１項記
載の半導体装置。[Claims for Utility Model Registration] (1) In a semiconductor device in which the output stage includes a plurality of circuit elements whose outputs change simultaneously when the inputs change simultaneously, and each of the circuit elements is driven by a common power source, each of the circuits described above 1. A semiconductor device comprising delay circuits having different signal delay times on signal lines that independently control outputs of elements. (2) The semiconductor device according to claim 1, wherein the delay circuit is provided on the input signal line of one or all of the plurality of circuit elements.

Claims

[Claims for Utility Model Registration] (1) In a semiconductor device in which the output stage includes a plurality of circuit elements whose outputs change simultaneously when the inputs change simultaneously, and each of the circuit elements is driven by a common power source, each of the circuits described above 1. A semiconductor device comprising delay circuits having different signal delay times on signal lines that independently control outputs of elements. (2) The semiconductor device according to claim 1, wherein the delay circuit is provided on the input signal line of each circuit element except one of the plurality of circuit elements.