JPH02154501A - Microwave integrated circuit - Google Patents

Microwave integrated circuit

Info

Publication number
JPH02154501A
JPH02154501A JP63309249A JP30924988A JPH02154501A JP H02154501 A JPH02154501 A JP H02154501A JP 63309249 A JP63309249 A JP 63309249A JP 30924988 A JP30924988 A JP 30924988A JP H02154501 A JPH02154501 A JP H02154501A
Authority
JP
Japan
Prior art keywords
matching circuit
output
input
circuit
fets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63309249A
Other languages
Japanese (ja)
Inventor
Koji Nishida
西田 幸治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63309249A priority Critical patent/JPH02154501A/en
Publication of JPH02154501A publication Critical patent/JPH02154501A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain miniaturization by arranging active elements in parallel and connecting each to a common input matching circuit and a common output matching circuit. CONSTITUTION:FETs (chip FETs) 5,6 are arranged side by side, they are connected to an input matching circuit by using input wires 5i,6i and connected to an output matching circuit 4 by using output wires 5o,6o. Moreover, the input matching circuit 3 takes matching of the combined impedance of impedances S11a,S11b connected in parallel of the FETs 5,6. This is applied similarly to the output matching circuit 4. Since the circuit has a structure that plural chip FETs are arranged side by side between the input matching circuit 3 and the output matching circuit 4 in this way, the overall size is made small.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はマイクロ波集積回路に関する。[Detailed description of the invention] [Industrial application field] This invention relates to microwave integrated circuits.

〔従来の技術〕[Conventional technology]

第3図は例えば従来のマイクロ波集積回路を示したもの
で、図において、11.12はトランジスタ、例えば、
電界効果形トランジスタFETであって、それぞれの入
力端子11i、12iは人力整合回路13a、13bに
接続され、入力整合回路1.3 a、13bには分配器
14を通してマイクロ波人力(RF倍信号が与えられる
。I5は抵抗である。トランジスタ11および12の出
力端子110.120には出力整合回路16a、16b
が接続されている。17iは回路入力端子である。
FIG. 3 shows, for example, a conventional microwave integrated circuit. In the figure, reference numerals 11 and 12 indicate transistors, for example
It is a field effect transistor FET, and its input terminals 11i and 12i are connected to manual matching circuits 13a and 13b, and the input matching circuits 1.3a and 13b receive a microwave manual power (RF multiplied signal) through a distributor 14. I5 is a resistor.Output matching circuits 16a and 16b are connected to the output terminals 110 and 120 of transistors 11 and 12.
is connected. 17i is a circuit input terminal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来のマイクロ波集積回路では、飽和出力が各FE
TIIと12の飽和出力を合成したものとなり、飽和出
力を高めることができるが(利得は変わらない)、各F
ETII、12に対してそれぞれ入力整合回路13a、
13b、出力整合回路4a、4bを設けているので、大
形化するという問題があった。
In this conventional microwave integrated circuit, the saturated output is
It is a combination of the saturated output of TII and 12, and the saturated output can be increased (the gain remains the same), but each F
Input matching circuits 13a for ETII and 12, respectively.
13b, and output matching circuits 4a and 4b, there was a problem of increasing the size.

この発明は上記問題を解消するためになされたもので、
従来に比し、小型化することができるマイクロ波集積回
路を提供することを目的とする。
This invention was made to solve the above problem.
It is an object of the present invention to provide a microwave integrated circuit that can be made smaller than conventional ones.

〔課題を解決するための手段〕[Means to solve the problem]

この発明は上記目的を達成するため、並列配jljl’
In order to achieve the above object, the present invention utilizes a parallel arrangement jljl'
.

した能動素子を入力ワイヤを介して共通の入力整合回路
に接続し、出力ワイヤを介して共通の出力整合回路に接
続したものである。
The active elements are connected to a common input matching circuit via an input wire, and are connected to a common output matching circuit via an output wire.

〔作用〕[Effect]

この発明では、複数個の能動素子に対して、入力整合回
路、出力整合回路が1つであるので、小型化が可能とな
る。
In this invention, since there is only one input matching circuit and one output matching circuit for a plurality of active elements, miniaturization is possible.

〔実施例〕〔Example〕

以下、この発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は平面図であって、回路接続を第2図に示しであ
る。両図において、1は誘電体基板、2はキャリアであ
る。3は誘電体基板1」二の入力整合回路、4は誘電体
基板1上の出力整合回路、5.6はFETである。FE
T (チップFET)5.6は横並列配置され、それぞ
れは入力ワイヤ51.61を用いて入力整合回路に接続
され、また、それぞれ出力ワイヤ50.60を用いて出
力整合回路4に接続されている。なお、入力整合回路3
はF E T 5.6のインピーダンス5lla、S、
1.を並列にしたものに整合を取るようにする。出力整
合回路4にっても同様である。160は出力端子である
FIG. 1 is a plan view, and FIG. 2 shows the circuit connections. In both figures, 1 is a dielectric substrate and 2 is a carrier. 3 is an input matching circuit on the dielectric substrate 1'', 4 is an output matching circuit on the dielectric substrate 1, and 5.6 is an FET. FE
T (chip FETs) 5.6 are arranged horizontally in parallel, each connected to the input matching circuit using an input wire 51.61, and each connected to the output matching circuit 4 using an output wire 50.60. There is. In addition, input matching circuit 3
is the impedance of F E T 5.6 5lla, S,
1. Make sure to match the parallel versions. The same applies to the output matching circuit 4. 160 is an output terminal.

この実施例では、1つの入力整合回路3と1つの出力整
合回路4の間に複数個のチップF E ’Fを並列配置
した構造であるので、全体が小型となる。
This embodiment has a structure in which a plurality of chips FE'F are arranged in parallel between one input matching circuit 3 and one output matching circuit 4, so that the overall size is reduced.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明した通り、能動素子を並列配置して
各々を共通の入力整合回路と共通の出力整合回路に接続
する構成としたから、能動素子の各々に対して入力整合
回路と出力整合回路を設けていた従来のものに比して、
小型化することができる。
As explained above, this invention has a configuration in which active elements are arranged in parallel and each is connected to a common input matching circuit and a common output matching circuit. Compared to the conventional one, which had
Can be made smaller.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例の平面図、第2図は上記実施
例の回路接続図、第3図は従来のマイクロ波集積回路の
平面図である。 図において、1−誘電体基板、2−キャリア、3−人力
整合回路、4−出力整合回路、5.6FET。 なお、図中、同一符号は同一または相当部分を示す。
FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a circuit connection diagram of the above embodiment, and FIG. 3 is a plan view of a conventional microwave integrated circuit. In the figure, 1-dielectric substrate, 2-carrier, 3-human matching circuit, 4-output matching circuit, 5.6FET. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  並列配置した能動素子を入力ワイヤを介して共通の入
力整合回路に接続し、出力ワイヤを介して共通の出力整
合回路に接続したことを特徴とするマイクロ波集積回路
A microwave integrated circuit characterized in that active elements arranged in parallel are connected to a common input matching circuit via an input wire and connected to a common output matching circuit via an output wire.
JP63309249A 1988-12-06 1988-12-06 Microwave integrated circuit Pending JPH02154501A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63309249A JPH02154501A (en) 1988-12-06 1988-12-06 Microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63309249A JPH02154501A (en) 1988-12-06 1988-12-06 Microwave integrated circuit

Publications (1)

Publication Number Publication Date
JPH02154501A true JPH02154501A (en) 1990-06-13

Family

ID=17990727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63309249A Pending JPH02154501A (en) 1988-12-06 1988-12-06 Microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPH02154501A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6521192B1 (en) * 2018-05-28 2019-05-29 三菱電機株式会社 amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142101B2 (en) * 1979-10-31 1986-09-19 Yamaha Motor Co Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142101B2 (en) * 1979-10-31 1986-09-19 Yamaha Motor Co Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6521192B1 (en) * 2018-05-28 2019-05-29 三菱電機株式会社 amplifier

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