JPH04109701A - Microwave semiconductor device - Google Patents
Microwave semiconductor deviceInfo
- Publication number
- JPH04109701A JPH04109701A JP2229213A JP22921390A JPH04109701A JP H04109701 A JPH04109701 A JP H04109701A JP 2229213 A JP2229213 A JP 2229213A JP 22921390 A JP22921390 A JP 22921390A JP H04109701 A JPH04109701 A JP H04109701A
- Authority
- JP
- Japan
- Prior art keywords
- impedance matching
- input
- microwave semiconductor
- fet
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 20
- 230000001939 inductive effect Effects 0.000 abstract description 12
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6644—Packaging aspects of high-frequency amplifiers
- H01L2223/6655—Matching arrangements, e.g. arrangement of inductive and capacitive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Microwave Amplifiers (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、例えば電界効果トランジスタ（以下、ＦＥ
Ｔと記す）等の内部整合方式の電力用電界効果型マイク
ロ波半導体装置に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a field effect transistor (hereinafter referred to as FE
The present invention relates to an internal matching type power field-effect microwave semiconductor device such as a power field-effect microwave semiconductor device (denoted as T).
（従来の技術）
一般に、内部整合方式の電力用電界効果型トランジスタ
においては、第５図に示すように外囲器１内にＦＥＴ２
が金錫ハンダ等により固着され、二〇ＦＥＴ２の両側の
外囲器ｌには、その入力端子及び出力端子に対応して入
力及び出力インピーダンス整合用の第１及び第２の回路
基板３ａ。(Prior Art) Generally, in an internal matching type power field effect transistor, as shown in FIG.
are fixed with gold-tin solder or the like, and first and second circuit boards 3a for input and output impedance matching are attached to the envelope l on both sides of the FET 2, corresponding to the input and output terminals thereof.
３ｂが同様に金錫ハンダ等により固着される。この第１
及び第２の回路基板３ａ、３ｂには入力及び出力インピ
ーダンス整合回路４ｇ、４ｂが形成サレル。この入力及
び出力インピーダンス整合回路４ａ、４ｂは、例えばチ
・ツブコンデンサ等の集中定数回路素子、オーブンスタ
ブ等の分布定数回路素子で構成される。そして、これら
ＦＥＴ２と第１及び第２の回路基板３ａ、３ｂの入力及
び出力インピーダンス整合回路４ａ、４ｂは金属線５を
介して電気的に一接続される。3b is similarly fixed with gold-tin solder or the like. This first
Input and output impedance matching circuits 4g and 4b are formed on the second circuit boards 3a and 3b. The input and output impedance matching circuits 4a and 4b are composed of lumped constant circuit elements such as chip capacitors and distributed constant circuit elements such as oven stubs. These FETs 2 and the input and output impedance matching circuits 4a and 4b of the first and second circuit boards 3a and 3b are electrically connected via a metal wire 5.
ところで、このようなトランジスタにあっては、その金
属線５の誘導リアクタンス成分により、容量性テするＦ
ＥＴ２のインピーダンスを誘導性に変換し、この変換し
たインピーダンスをインピーダンス整合回路４ａ、４ｂ
の容量性リアクタンス成分により電源及び負荷のインピ
ーダンス（通常５０オ一ム程度）に整合を採っている。By the way, in such a transistor, due to the inductive reactance component of the metal line 5, the F which is capacitive is
The impedance of ET2 is converted into inductive one, and the converted impedance is passed through impedance matching circuits 4a and 4b.
The capacitive reactance component matches the impedance of the power supply and load (usually about 50 ohms).
そこで、ＦＥＴ２の動作周波数が低い場合には、そのイ
ンピーダンスが大きくなることにより、大きな誘導性成
分が必要となるために、その金属線５の長さ寸法を比較
的長く設定して、大きな所望の誘導性成分を得る必要が
ある。Therefore, when the operating frequency of the FET 2 is low, its impedance becomes large and a large inductive component is required. It is necessary to obtain an inducible component.
しかしながら、上記のように金属線５を長く採ったトラ
ンジスタでは、金属線５をボンディングする装置の性能
上、ボンディングした金属線５のループを均一にするこ
とが困難なことにより（第５図（ｂ）参照）、そのリア
クタンス成分が不均一となるために、インピーダンス整
合回路４ａ。However, in a transistor in which the metal wire 5 is long as described above, it is difficult to make the loop of the bonded metal wire 5 uniform due to the performance of the device for bonding the metal wire 5 (see Fig. 5 (b). ), the reactance component of the impedance matching circuit 4a is non-uniform.
４ｂの特性にばらつきが起り、その特性歩留が悪いとい
う問題を有していた。There was a problem that variations occurred in the characteristics of 4b and the yield of the characteristics was poor.
（発明が解決しようとする課題）
以上述べたように、従来のマイクロ波半導体装置では、
誘導性成分を大きく採ると、インピーダンス整合回路の
特性歩留が悪化するという問題を有していた。(Problem to be solved by the invention) As mentioned above, in the conventional microwave semiconductor device,
If the inductive component is large, there is a problem in that the characteristic yield of the impedance matching circuit deteriorates.
この発明は上記の事情に鑑みてなされたもので、ボンデ
ィング精度の均一化を図り得るようにして、誘導リアク
タンス成分の均一化を図り、インピーダンス整合回路の
特性歩留の向上を実現したマイクロ波半導体装置を提供
することを目的とする。This invention has been made in view of the above circumstances, and is a microwave semiconductor that achieves uniform bonding accuracy, equalizes inductive reactance components, and improves the characteristic yield of impedance matching circuits. The purpose is to provide equipment.
［発明の構成コ
（課題を解決するための手段）
この発明はマイクロ波半導体素子の入力端子及び出力端
子に対して入力及び出力インピーダンス整合回路を金属
線を介して電気的に接続してなるマイクロ波半導体装置
において、前記マイクロ波半導体素子と前記入力及び出
力インピーダンス整合回路の少なくともいづれか一方の
間に両面に金属膜が形成された誘電体基板を介在し、こ
の誘電体基板を介して前記マイクロ波半導体素子の入出
力端と入力及び出力インピーダンス整合回路との電気的
接続を行うように構成したものである。[Structure of the Invention (Means for Solving the Problems) The present invention provides a micro-wave semiconductor device in which input and output impedance matching circuits are electrically connected to the input and output terminals of a microwave semiconductor element via metal wires. In the microwave semiconductor device, a dielectric substrate having metal films formed on both surfaces is interposed between the microwave semiconductor element and at least one of the input and output impedance matching circuits, and the microwave is transmitted through the dielectric substrate. It is configured to electrically connect the input/output terminals of the semiconductor element and the input and output impedance matching circuits.
（作用）
上記構成によれば、マイクロ波半導体素子の入力端子及
び出力端子と入力及び出力インピーダンス整合回路部品
を電気的に接続する金属線は誘電体基板を介してボンデ
ィングされることにより、その長さ寸法の短縮化が図れ
る。従って、ボンディング精度の均一化が図れて、誘導
リアクタンス成分の均一化が図れ、インピーダンス整合
回路の特性歩留が向上される。(Function) According to the above configuration, the metal wires that electrically connect the input terminals and output terminals of the microwave semiconductor element and the input and output impedance matching circuit components are bonded via the dielectric substrate, so that the length of the metal wires is increased by bonding through the dielectric substrate. The length can be shortened. Therefore, bonding accuracy can be made uniform, inductive reactance components can be made uniform, and the characteristic yield of the impedance matching circuit can be improved.
（実施例）
以下、この発明の実施例について、図面を参照して詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図はこの発明の一実施例に係るマイクロ波半導体装
置を示すもので、外囲器１０にはマイクロ波半導体素子
であるＦＥＴＩＩが金錫ノ１ンダ等を用いて固着される
。このＦＥＴＩＩの両側の外囲器内には第１及び第２の
回路基板１２ａ。FIG. 1 shows a microwave semiconductor device according to an embodiment of the present invention, in which a microwave semiconductor element FET II is fixed to an envelope 10 using a gold-tin solder or the like. First and second circuit boards 12a are provided in the envelopes on both sides of this FET II.
１２ｂが金錫ハンダ等により固着される。この第１及び
第２の回路基板１２ａ、１．２ｂには入力及び出力イン
ピーダンス整合回路１３ａ、１．３ｂが形成され、この
入力及び出力インピーダンス整合回路１３ａ、１３ｂ・
は図示しない外部機器に接続される入力端子及び出力端
子に金属線１４を介してボンディング接続される。12b is fixed with gold-tin solder or the like. Input and output impedance matching circuits 13a and 1.3b are formed on the first and second circuit boards 12a and 1.2b, and these input and output impedance matching circuits 13a and 13b.
are bonded via metal wires 14 to input terminals and output terminals connected to external equipment (not shown).
また、第１の回路基板１３ａとＦＥＴＩ １との間の外
囲器１０には誘電体基板１５が、例えば金錫ハンダ等に
より固着される。誘電体基板１５はＦＥＴＩＩを第１の
回路基板１２ａの入力インピーダンス回路１３ａより遮
断するように配置され、例えば第２図に示すように、両
面に金属膜１５ａ。Further, a dielectric substrate 15 is fixed to the envelope 10 between the first circuit board 13a and the FETI 1 using, for example, gold-tin solder. The dielectric substrate 15 is arranged to isolate the FET II from the input impedance circuit 13a of the first circuit board 12a, and has metal films 15a on both sides, for example, as shown in FIG.
１５ｂが形成される。そして、この誘電体基板１５は、
その一方面の金属膜１５ａが第１の回路基板１２ ａの
入力インピーダンス整合回路１３ａ及びＦＥＴＩＩの入
力端子に金属線１６を介してボンディング接続される。15b is formed. This dielectric substrate 15 is
The metal film 15a on one side is bonded to the input impedance matching circuit 13a of the first circuit board 12a and the input terminal of the FET II via a metal wire 16.
さらに、ＦＥＴＩＩは、その出力端子が第２の回路基板
１２ｂの出力インピーダンス整合回路１３ｂに金属線１
６を介してボンディング接続される。Further, the FET II has its output terminal connected to the output impedance matching circuit 13b of the second circuit board 12b through the metal wire 1.
Bonding connection is made through 6.
上記構成において、インピーダンス整合は、その金属線
１６の長さ寸法が要求される誘導リアクタンス成分に対
応して設定される。そして、この金属線１６は、ＦＥＴ
１１、誘電体基板１５、第１及び第２の回路基板１２ａ
、１２ｂの間にそれぞれボンデインク接続される本数に
応じて均一な長さ寸法に設定されて、それぞれにボンデ
ィング接続される。この結果、比較的、短い均一な長さ
寸法の金属線１６を用いて、比較的大きな誘導リアクタ
ンス成分を得ることが可能となる。In the above configuration, impedance matching is set so that the length of the metal wire 16 corresponds to the required inductive reactance component. This metal wire 16 is connected to the FET
11, dielectric substrate 15, first and second circuit boards 12a
, 12b are set to have uniform lengths according to the number of wires to be bonded and ink-connected, respectively, and are bonded to each other. As a result, it is possible to obtain a relatively large inductive reactance component using the metal wire 16 having a relatively short and uniform length dimension.
このように、上記マイクロ波半導体装置はＦＥＴＩＩと
入力インピーダンス整合回路１３ａとの間に両面に金属
膜１５ａ、１５ｂが形成された誘電体基板１５を介在し
、この誘電体基板１５を介してＦＥＴＩＩの入力端子と
入力インピーダンス整合回路１３ａとの電気的接続を行
うように構成した。これによれば、ＦＥＴ１１の入力端
子と入力インピーダンス整合回路１３ａを電気的に接続
する金属線１６は誘電体基板１５を介してボンディング
接続されることにより、その長さ寸法の短縮化が図れて
、ボンディング精度の均一化が図れ、誘導リアクタンス
成分の均一化が図れるため、インピーダンス整合回路の
特性歩留が向上される。In this manner, the microwave semiconductor device has a dielectric substrate 15 with metal films 15a and 15b formed on both surfaces interposed between the FET II and the input impedance matching circuit 13a. It was configured to electrically connect the input terminal and the input impedance matching circuit 13a. According to this, the metal wire 16 that electrically connects the input terminal of the FET 11 and the input impedance matching circuit 13a is bonded via the dielectric substrate 15, so that its length can be shortened. Since bonding accuracy can be made uniform and inductive reactance components can be made uniform, the characteristic yield of the impedance matching circuit is improved.
なお、上記誘電体基板１５は、第３図及び第４図に示す
ように構成することも可能である。Note that the dielectric substrate 15 can also be configured as shown in FIGS. 3 and 4.
すなわち、第３図は誘電体基板の金属線接続面となる一
方面の金属膜の周囲部に凹凸状の目印パターン１５ｃを
形成したものである。これによれば、目印パターン１５
Ｃがボンディング接続の際のめやすとなり、ボンディン
グ作業の簡便化が図れる。That is, in FIG. 3, a concavo-convex mark pattern 15c is formed around the metal film on one side of the dielectric substrate serving as the metal line connection surface. According to this, landmark pattern 15
C serves as a guideline for bonding connection, and the bonding work can be simplified.
第４図は誘電体基板１５の載置面となる他方面に一方面
の金属膜に対応した凹部１５ｄを形成し、この凹部１５
ｄの周囲のみに一方面の金属膜１５ａと対向しない金属
膜１５ｅを形成したものである。これによれば、両面に
形成した金属膜１５ａ。In FIG. 4, a recess 15d corresponding to the metal film on one side is formed on the other surface of the dielectric substrate 15, which is the mounting surface.
A metal film 15e that does not face the metal film 15a on one side is formed only around d. According to this, the metal film 15a is formed on both sides.
１５ｅにより発生する静電容量を小さくすることにより
、インピーダンス整合回路１３ａ、１３ｂへの悪影響の
防止が図れ、さらに有効な効果が期待される。By reducing the capacitance generated by the impedance matching circuit 15e, it is possible to prevent an adverse effect on the impedance matching circuits 13a and 13b, and more effective effects are expected.
また、上記実施例では、誘電体基板１５を第１の回路基
板１２ａとＦＥＴＩＩの間に介在した場合を代表して説
明したが、これに限ることなく、要求される誘導性リア
クタンス成分に応じて、第１及び第２の回路基板１２ａ
、１２ｂとＦＥＴ１１の双方の間に介在したり、あるい
は第２の回路基板１２ｂとＦＥＴ１１との間に介在する
ことも可能である。Further, in the above embodiment, the case where the dielectric substrate 15 is interposed between the first circuit board 12a and the FET II has been described as a representative case, but the present invention is not limited to this, and the , first and second circuit boards 12a
, 12b and the FET 11, or between the second circuit board 12b and the FET 11.
さらに、上記実施例では、ＦＥＴＩＩを用いて構成した
場合で説明したが、これに限ることなく、各種のマイク
ロ波半導体素子において適用可能である。Further, in the above embodiment, a case has been described in which the structure is configured using FETII, but the present invention is not limited to this, and can be applied to various microwave semiconductor devices.
よって、この発明は上記実施例に限ることなく、その他
、この発明の要旨を逸脱しない範囲で種々の変形を実施
し得ることは勿論のことである。Therefore, it goes without saying that the present invention is not limited to the above embodiments, and that various modifications can be made without departing from the spirit of the invention.
［発明の効果］
以上詳述したように、この発明によれば、ボンディング
精度の均一化を図り得るようにして、誘導リアクタンス
成分の均一化を図り、インピーダンス整合回路の特性歩
留の向上を実現したマイクロ波半導体装置を提供するこ
とができる。[Effects of the Invention] As detailed above, according to the present invention, bonding accuracy can be made uniform, inductive reactance components can be made uniform, and the characteristic yield of impedance matching circuits can be improved. A microwave semiconductor device can be provided.
第１図はこの発明の一実施例に係るマイクロ波半導体装
置を示した図、第２図は第１図の誘電体基板を取出して
示した図、第３図及び第４図はこの発明の他の実施例を
示した図、′！ｓ５図は従来のマイクロ波半導体装置を
示した図である。
１０−・・外囲器、１ｌ−ＦＥＴ、１２ｇ、１２ｂ・・
・第１及び第２の回路基板、１３ａ、１３ｂ・・・入力
及び出力インピーダンス整合回路、１４．１６・・・金
属線、１５・・・誘電体基板、１５ａ、１５ｂ。
］
金属膜、
］
目印バタ
ノ、
・・・凹部。
■願人代理人FIG. 1 is a diagram showing a microwave semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing the dielectric substrate of FIG. 1 taken out, and FIGS. A diagram showing another embodiment, ′! Figure s5 is a diagram showing a conventional microwave semiconductor device. 10-...Envelope, 1l-FET, 12g, 12b...
- First and second circuit boards, 13a, 13b... Input and output impedance matching circuit, 14.16... Metal wire, 15... Dielectric substrate, 15a, 15b. ] Metal film, ] Mark Batano, ... recess. ■Applicant's agent
Claims (3)
対して入力及び出力インピーダンス整合回路を金属線を
介して電気的に接続してなるマイクロ波半導体装置にお
いて、 前記マイクロ波半導体素子と前記入力及び出力インピー
ダンス整合回路の少なくともいづれか一方の間に両面に
金属膜が形成された誘電体基板を介在し、この誘電体基
板を介して前記マイクロ波半導体素子の入出力端と入力
及び出力インピーダンス整合回路との電気的接続を行う
ように構成したことを特徴とするマイクロ波半導体装置
。(1) In a microwave semiconductor device in which input and output impedance matching circuits are electrically connected to input terminals and output terminals of a microwave semiconductor element via metal wires, the microwave semiconductor element and the input and output terminals are electrically connected to each other via metal wires. A dielectric substrate having a metal film formed on both surfaces is interposed between at least one of the output impedance matching circuits, and the input and output terminals of the microwave semiconductor element and the input and output impedance matching circuits are connected via the dielectric substrate. 1. A microwave semiconductor device characterized in that it is configured to make an electrical connection.
属膜の周囲部に凹凸状の目印パターンを形成したことを
特徴とする請求項１記載のマイクロ波半導体装置。(2) The microwave semiconductor device according to claim 1, wherein an uneven mark pattern is formed on the periphery of the metal film on one side of the dielectric substrate serving as the metal line connection surface.
属線接続面となる一方面の金属膜に対応して形成し、こ
の凹部の周囲部に前記金属膜を形成したことを特徴とす
る請求項１又は請求項２記載のマイクロは半導体装置。(3) The dielectric substrate has a concave portion formed on the other surface, which is the mounting surface, corresponding to the metal film on one surface, which is the metal wire connection surface, and the metal film is formed around the concave portion. A micro semiconductor device according to claim 1 or claim 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2229213A JPH04109701A (en) | 1990-08-29 | 1990-08-29 | Microwave semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2229213A JPH04109701A (en) | 1990-08-29 | 1990-08-29 | Microwave semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04109701A true JPH04109701A (en) | 1992-04-10 |
Family
ID=16888598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2229213A Pending JPH04109701A (en) | 1990-08-29 | 1990-08-29 | Microwave semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04109701A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7409668B2 (en) * | 2005-08-19 | 2008-08-05 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Method for improving via's impedance |
| EP2197030A3 (en) * | 2008-12-10 | 2010-08-04 | Kabushiki Kaisha Toshiba | A high frequency semiconductor device |
-
1990
- 1990-08-29 JP JP2229213A patent/JPH04109701A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7409668B2 (en) * | 2005-08-19 | 2008-08-05 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Method for improving via's impedance |
| EP2197030A3 (en) * | 2008-12-10 | 2010-08-04 | Kabushiki Kaisha Toshiba | A high frequency semiconductor device |
| US8431973B2 (en) | 2008-12-10 | 2013-04-30 | Kabushiki Kaisha Toshiba | High frequency semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0786460A (en) | Semiconductor device | |
| JPH01233795A (en) | Hybrid integrated circuit | |
| JPH04109701A (en) | Microwave semiconductor device | |
| JP2758321B2 (en) | Circuit board | |
| JPH01273404A (en) | High frequency semiconductor device | |
| JP2661570B2 (en) | High frequency device | |
| JP3259217B2 (en) | Noise reduction package | |
| JPS6397001A (en) | Microwave semiconductor device | |
| JPS62269349A (en) | Semiconductor device | |
| JPS62150903A (en) | High frequency hybrid integrated circuit device | |
| JPH02140969A (en) | Semiconductor integrated circuit device | |
| JP3237398B2 (en) | Microwave semiconductor integrated circuit module | |
| JPH0233963A (en) | High frequency transistor | |
| JPH05299570A (en) | Semiconductor device | |
| JPH03276745A (en) | Semiconductor device | |
| JPH04264800A (en) | Composite integrated circuit | |
| JPS5869947U (en) | microwave semiconductor circuit | |
| JPS63133701A (en) | Microwave semiconductor device | |
| JPS6380608A (en) | Microwave semiconductor amplifier | |
| JPH06244298A (en) | Microwave integrated circuit device | |
| JPH02134906A (en) | Device for high frequency power amplification | |
| JPH01239945A (en) | Hybrid integrated circuit device | |
| JPH11298264A (en) | High frequency power amplifier circuit device | |
| JPH10178125A (en) | Package | |
| JPH0254603A (en) | Power supply circuit |