JPH01239945A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH01239945A
JPH01239945A JP63068804A JP6880488A JPH01239945A JP H01239945 A JPH01239945 A JP H01239945A JP 63068804 A JP63068804 A JP 63068804A JP 6880488 A JP6880488 A JP 6880488A JP H01239945 A JPH01239945 A JP H01239945A
Authority
JP
Japan
Prior art keywords
semiconductor element
pad
plated
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63068804A
Other languages
Japanese (ja)
Inventor
Masahide Yamauchi
山内　眞英
Tetsuo Mori
哲郎 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63068804A priority Critical patent/JPH01239945A/en
Publication of JPH01239945A publication Critical patent/JPH01239945A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1905—Shape
    • H01L2924/19051—Impedance matching structure [e.g. balun]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Abstract

PURPOSE:To reduce an irregularity in a plated thin wire and to reduce an input inductance by a method wherein a semiconductor element is inserted into a hole made in a substrate and a circuit pattern and a pad part are fixed on an identical plane and connected by using the plated thin wire. CONSTITUTION:Pad parts 9 formed on a semiconductor element 3 and circuit patterns formed on a dielectric substrate 1 are fixed in such a way that they are situated on an almost identical plane; they are connected to be conductive by using plated thin wires 10. By this constitution, an irregularity in the plated thin wires 10 can be reduced; an inductance of an input can be reduced. In addition, the area of the plated pads 9 can be made small; a parasitic capacitance can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、例えば通信機器関連に使用される超高周波
用の混成集積回路装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a hybrid integrated circuit device for ultra-high frequencies used, for example, in communication equipment.

〔従来の技術〕[Conventional technology]

第２図は従来の混成集積回路装置を示すｌ！ｒ面斜視図
であり、図において、１はアルミナ等からなる誘電体基
板、２は上記誘電体基板ｌ土に形成された回路パターン
、３は上記誘電体基板ｌ上に妥着された半導体素子、４
は上記半導体素子３上に形成されたポンディングパッド
、５は上記ポンディングパッド４と上記回路パターン２
とを電気的に接続する金属細線、６は上記誘電体基板１
と上記半導体素子３とを接合Ｔる接着剤である０次に動
作について説明Ｔる。外部から送られてくる高周波信号
は、誘？ｉＥ体基板１に形成された一万の回路パターン
２より、金属細線５及びポンディングパッド４を経由し
て半導体素子３に印加される。ここで半導体素子３には
外部より直流電力が印加されており（図示せず）、入力
された高周波信号が増幅される。FIG. 2 shows a conventional hybrid integrated circuit device. It is an R-plane perspective view, and in the figure, 1 is a dielectric substrate made of alumina or the like, 2 is a circuit pattern formed on the dielectric substrate l, and 3 is a semiconductor element fixed on the dielectric substrate l. , 4
5 is a bonding pad formed on the semiconductor element 3, and 5 is the bonding pad 4 and the circuit pattern 2.
A thin metal wire 6 electrically connects the dielectric substrate 1
The zero-order operation of the adhesive used to bond the semiconductor element 3 and the semiconductor element 3 will now be explained. Is the high frequency signal sent from the outside an inducer? A voltage is applied from the 10,000 circuit patterns 2 formed on the iE body substrate 1 to the semiconductor element 3 via the thin metal wires 5 and the bonding pads 4. Here, DC power is applied to the semiconductor element 3 from the outside (not shown), and the input high frequency signal is amplified.

この増幅された高周波信号は他方（出力＋１ｉｌｌ　）
のポンディングパッド４、金属細線５及び回路パターン
２を経由して出力信号として取り出される。This amplified high frequency signal is the other (output + 1ill)
The output signal is taken out as an output signal via the bonding pad 4, the thin metal wire 5, and the circuit pattern 2.

（発明が解決しようとする課題〕 従来の混成集積回路装置は以上のように宥或ぎれている
ので、高周波信号は長くがっ寸法のバラツキの大きい忙
４細線５及びワイヤボンドするにめ面積が大に形成きれ
たポンディングパッド４ご経由しなければならす、人力
のインダクタンスか大さくなったり、ポンディングパッ
ドによる寄生６討の増大等が生じて、高周波特性か低Ｆ
Ｔる問題点があった。(Problems to be Solved by the Invention) Conventional hybrid integrated circuit devices have the above-mentioned problems, so high-frequency signals are produced by long wires with large dimensional variations and small wire bonding areas. The inductance of the human power must be passed through the overly formed bonding pad 4, which may increase, and the parasitic effects due to the bonding pad may increase, resulting in poor high frequency characteristics or low F.
There were a number of problems.

この発明は上記のような問題点を解消丁６ためなされた
もので、入力インダクタンスの軽減、寄生容量の軽減ご
可能に下る高周波用の混成集積回路装置を得ることを目
的とする〇 〔課題を解決下６ｚめの手段〕 この発明に係る混成集積回路装置は、穴部を収けた基板
を有し１口の穴部に半導体素子を挿入し、かつ上記基板
面に形成された回路パターンと上記半導体素子面に形成
されたパッド部とがほぼ同一平面上に位置するように固
着Ｔるとともに、上ｇ己回路パターンと上記パッド部と
をメッキ細線により電気的に接緬したものである。This invention was made to solve the above-mentioned problems, and aims to provide a high-frequency hybrid integrated circuit device that can reduce input inductance and parasitic capacitance. Sixth Means for Solving] A hybrid integrated circuit device according to the present invention has a substrate having a hole, a semiconductor element is inserted into one hole, and the circuit pattern formed on the surface of the substrate and the above-described The pad portion formed on the surface of the semiconductor element is fixed so as to be located on substantially the same plane, and the upper circuit pattern and the pad portion are electrically connected by a thin plated wire.

〔作用〕 この発明に３ける混成集積回路装置は、基板面に形成さ
れた回路パターンと半導体素子面Ｇこ形成されたパッド
部とがはは１司−面上となり、メッキ細線により導通妥
耽し二ので、細線のバラツキが少なく入力のインダクタ
ンスを低減できる。またパッドの白檀を極端に減少する
ことができ寄生容量な低減できる。[Function] In the hybrid integrated circuit device according to the third aspect of the present invention, the circuit pattern formed on the substrate surface and the pad portion formed on the semiconductor element surface are on one plane, and conduction is achieved by the plated thin wire. Therefore, there is less variation in thin wires and input inductance can be reduced. In addition, the sandalwood of the pad can be drastically reduced, and the parasitic capacitance can also be reduced.

〔実施例〕〔Example〕

第１図はこの発明の一実施例による混１５！２＋集槓回
路装置Ｐ示す断面斜視図であって、ｌはアルミナ等から
なる誘電体基板、２は土泥誘電体基板１上に形成された
回路パターン、３は上記誘電体基板１に設けられた穴部
７に接着剤８により固定された半導体素子、９は上記千
導雀素子３土に設けられたメッキパッド、１０　ＧＺメ
ッキで形成され７こメッキ細線であり、このメッキ細線
１０は上記回路パターンｚと上記メッキパッド９とを電
気的に導通させるものである。FIG. 1 is a cross-sectional perspective view showing a mixed 15!2+concentrator circuit device P according to an embodiment of the present invention, where l is a dielectric substrate made of alumina or the like, and 2 is formed on a mud dielectric substrate 1. 3 is a semiconductor element fixed in a hole 7 provided in the dielectric substrate 1 with an adhesive 8; 9 is a plating pad provided on the Sendojaku element 3; 10 is formed by GZ plating. This plated thin wire 10 electrically connects the circuit pattern z and the plated pad 9.

また誘電体基板ｌ上に形成されている回路パターン２と
、半導体素子３上に形成されているメッキパッド９とが
、はぼ同一面上に位置するように溝成されている。Further, the grooves are formed so that the circuit pattern 2 formed on the dielectric substrate 1 and the plating pad 9 formed on the semiconductor element 3 are located on almost the same plane.

なお上記メッキ細線１０は、細線形成用のレジスト層を
形成した後、メッキ法によりメッキ細線を形成し、レジ
スｌ−Ｊ＃を除去する方法で作成下る。The plated thin wire 10 is produced by forming a resist layer for forming the thin wire, forming the plated thin wire by a plating method, and removing the resist l-J#.

次に動作について説、明Ｔ＾０外部力）ら送られてくる
高周波信号は誘電体基板ｌに形成された一万の（ロ）路
パターン２からメッキ細線ｌＯ及びメッキパッド９を経
由して半導体素子３に印加される。半導体素子３には外
部よつ直流電力か印Ｕ［ｌされており（図示せず）、入
力さねに高周波信号が増幅される。Next, we will explain the operation.The high frequency signal sent from T^0 external force is transmitted from the 10,000 (b) path pattern 2 formed on the dielectric substrate l via the plated thin wire lO and the plated pad 9. A voltage is applied to the semiconductor element 3. The semiconductor element 3 is connected to an external DC power source (not shown), and a high frequency signal is amplified at the input.

この増ｌＩ４された高周波信号は、他方（出力側）のメ
ッキバッド９、メッキａ線］０及び（ロ）路パターン２
を経由して出力信号として取り出される。ここで従来の
長くかつ寸法のバラツキの大きい金拠細線から敬μ幅の
メッキ細線ｌＯに改良したためインダクタンスの低減が
図れ、バラツキも少なくて＠る。またメッキバッド９は
従来のポンディングパッド４に比べその面積を小さくす
ることかでき寄生容量の低減が５ＪＮごとなる。このた
め超高周波（８０ＧＨｚ〜）において良好な特性が得ら
れろ。This amplified high frequency signal is transmitted to the other (output side) plating pad 9, plating a line]0 and (b) path pattern 2.
is extracted as an output signal via . Here, since the conventional long metal wire with large variations in dimensions has been improved to a plated thin wire with a width of 10 μm, the inductance can be reduced and the variation is also small. Furthermore, the area of the plating pad 9 can be made smaller than that of the conventional bonding pad 4, and the parasitic capacitance can be reduced by 5 JN. Therefore, good characteristics can be obtained at ultra-high frequencies (80 GHz and above).

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、半導体素子上に形成さ
れたパッド部と基板上に形成された（口）路パターンと
をほぼ同一面上に位置するようにして、メッキ細線によ
りパッド部と（ロ）路パターンを妥続したので、インダ
クタンスの低減及びバラツキの低減が達成できるととも
に、パッド部の面積が極端に小さくでき、寄生容量の軽
減が可能となる。As described above, according to the present invention, the pad portion formed on the semiconductor element and the path pattern formed on the substrate are located on almost the same plane, and the pad portion is connected with the plated thin wire. (b) Since the circuit pattern is maintained, it is possible to reduce inductance and variation, and the area of the pad portion can be extremely reduced, making it possible to reduce parasitic capacitance.

このため特に超高周波（’：３０ＧＨｚ　−）での良好
な特性をもつ混成集積回路装置が得られる効果がある。Therefore, there is an effect that a hybrid integrated circuit device having good characteristics particularly at ultra-high frequencies (': 30 GHz -) can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例による混成集積回路装置を
示す断面斜視図、第２図は従来の混成集積回路装置を示
す断面斜視図である。 図中、１は誘電体基板、２は回路パターン、３は°半導
体素子、７は穴部、８は接着材、９はパッド部、１０は
メッキ細線である。 尚、図中同一符号は同一またに相当部分ご示す。 代理人　　　大　　岩　　増　　雄FIG. 1 is a cross-sectional perspective view showing a hybrid integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional perspective view showing a conventional hybrid integrated circuit device. In the figure, 1 is a dielectric substrate, 2 is a circuit pattern, 3 is a semiconductor element, 7 is a hole, 8 is an adhesive, 9 is a pad, and 10 is a thin plated wire. In addition, the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

【特許請求の範囲】[Claims] 　穴部が設けられた基板と、上記穴部に挿入される半導
体素子を有し、上記基板上に形成された回路パターンと
上記半導体素子上に形成されたパッド部とがほぼ同一面
上に位置するように上記半導体素子を上記基板の穴部に
固着するとともに、上記回路パターンと上記パッド部と
をメッキ細線により電気的に接続したことを特徴とする
混成集積回路装置。A substrate provided with a hole and a semiconductor element inserted into the hole, wherein a circuit pattern formed on the substrate and a pad formed on the semiconductor element are located on substantially the same plane. A hybrid integrated circuit device, wherein the semiconductor element is fixed in the hole of the substrate, and the circuit pattern and the pad are electrically connected by a thin plated wire.
JP63068804A 1988-03-22 1988-03-22 Hybrid integrated circuit device Pending JPH01239945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63068804A JPH01239945A (en) 1988-03-22 1988-03-22 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63068804A JPH01239945A (en) 1988-03-22 1988-03-22 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH01239945A true JPH01239945A (en) 1989-09-25

Family

ID=13384271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63068804A Pending JPH01239945A (en) 1988-03-22 1988-03-22 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH01239945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT14667U1 (en) * 2014-03-26 2016-03-15 Tridonic Gmbh & Co Kg Printed circuit board with coil unit and a mounting method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT14667U1 (en) * 2014-03-26 2016-03-15 Tridonic Gmbh & Co Kg Printed circuit board with coil unit and a mounting method therefor

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