JPH0243761A - Microwave monolithic integrated circuit device - Google Patents

Microwave monolithic integrated circuit device

Info

Publication number
JPH0243761A
JPH0243761A JP63193943A JP19394388A JPH0243761A JP H0243761 A JPH0243761 A JP H0243761A JP 63193943 A JP63193943 A JP 63193943A JP 19394388 A JP19394388 A JP 19394388A JP H0243761 A JPH0243761 A JP H0243761A
Authority
JP
Japan
Prior art keywords
bias
bonding pad
integrated circuit
wire
mim capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63193943A
Other languages
Japanese (ja)
Inventor
Yasuhiro Akiba
秋葉　康弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63193943A priority Critical patent/JPH0243761A/en
Publication of JPH0243761A publication Critical patent/JPH0243761A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To alleviate the effect caused by the variability of a bonding wire in length and inductance on a high frequency property by providing a means of small area at a low cost by a method wherein an MIM capacitor is provided near to a DC bias bonding pad and concurrently a grounding means is provided to ground the DC bias bonding pad. CONSTITUTION:A metal-insulator-metal(MIM) capacitor 6 is provided near to a DC bias bonding pad 3 of a microwave monolithic integrated circuit 1, and concurrently a grounding means is provided to ground the MIM capacitor 6 making the DC bias bonding pad 3 shortcircuited as to a high frequency component. For instance, the above MIM capacitor 6 is grounded by making a metal layer above it connected with a metal chip carrier 7 through a bonding wire 4, and a metal layer under the MIM capacitor 6 is connected to the DC bias bonding pad 3 and a wiring pattern 9 by means of through-hole 8a and 8b respectively, and a DC bias wire 5 is wire-bonded to the DC bias bonding pad 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高周波帯で使用されるマイクロ波モノリシッ
ク集積回路装置に係わり、特にその００７４７７回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a microwave monolithic integrated circuit device used in a high frequency band, and particularly to its 007477 circuit.

〔従来の技術〕[Conventional technology]

従来、この種のマイクロ波モノリシック集積回路装置に
用いられる００７４７７回路は、第３図に示すようにマ
イクロ波モノリシック集積回路１の外部に配設されたタ
ンパンコン２と、マイクロ波モノリシック集積回路（以
下ＭＭＩＣと称する）１に形成されたＤＣバイアスボン
ディングパッド３とがボンディングワイヤ４によ多接続
され、このタンパンコン２には外部からＤＣバイアス電
流ｌを入出力させるＤＣバイアスワイヤ５が接続されて
構成されている。Conventionally, the 007477 circuit used in this type of microwave monolithic integrated circuit device consists of a tampan condenser 2 disposed outside the microwave monolithic integrated circuit 1 and a microwave monolithic integrated circuit (hereinafter MMIC) as shown in FIG. DC bias bonding pads 3 formed on the DC bias bonding pads 1 (referred to as . . . There is.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の００７４７７回路は、ボンディングワイ
ヤ４によシボンデイングパッド３とタンパンコン２とを
接続しているため、ボンディングワイヤ４のインダクタ
ンスによシボンデイングバツド３の接地が不十分となる
とともにボンディングワイヤ４の長さのばらつきによシ
、特にバイアス線路を整合回路に使用している場合には
高周波特性が大きく変化することがあシ、また、タンパ
ンコン２を使用しているため、面積が広く必要となシ、
費用本かかるという問題があった。In the conventional 007477 circuit described above, since the bonding pad 3 and the contact pad 2 are connected by the bonding wire 4, the grounding of the bonding pad 3 is insufficient due to the inductance of the bonding wire 4, and the bonding wire Due to variations in the length of 4, the high frequency characteristics may change significantly, especially when a bias line is used as a matching circuit.Also, since tampan condenser 2 is used, a large area is required. Tonashi,
There was a problem with the cost involved.

したがって本発明は、前述した従来の問題に鑑みてなさ
れたものでおり、その目的は、小面積および低費用でボ
ンディングワイヤのインダクタンスおよびボンディング
ワイヤ長のばらつきによる高周波特性の影響を軽減させ
たマイクロ波モノリシック集積回路装置を提供すること
にある。Therefore, the present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a microwave which reduces the influence of high frequency characteristics due to variations in bonding wire inductance and bonding wire length, in a small area and at low cost. An object of the present invention is to provide a monolithic integrated circuit device.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のマイクロ波モノリシック集積回路装置は、ＭＭ
ＩＣのポンディングパッドの近傍にメタルインシュレー
タメタル（以下ＭＩＭと称する）キャパシタを設けると
ともにこのＭＩＭキャパシタを接地する接地手段を有し
て構成される。The microwave monolithic integrated circuit device of the present invention comprises MM
A metal insulator metal (hereinafter referred to as MIM) capacitor is provided near a bonding pad of an IC, and a grounding means is provided for grounding this MIM capacitor.

〔作用〕[Effect]

本発明においては、ＭＩＣのポンディングパッドが高周
波的に短絡されることになる。In the present invention, the bonding pads of the MIC are short-circuited at high frequencies.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例によるマイクロ波モノリシッ
ク集積回路装置の構成を示す平面図であシ、前述の図と
同一部分には同一符号を付しである。同図において、Ｍ
ＭＩＣｌのＤＣバイアスボンディングパッド３の近傍に
は、ＭＩＭキャパシタ６が設けられ、ＤＣバイアスボン
ディングパッド３はこのＭＩＭキャパシタ６によシ高周
波的に短絡される構成となっている。すなわち、このＭ
ＩＭキャパシタ６は、その上層のメタル層がボンディン
グワイヤ４によりメタルチップキャリア７に接続されて
接地されておシ、その下層のメタル層がそれぞれスルー
ホール８ａ　ｔ　ａｂによシＤＣバイアスボンディング
パッド３．配線パターン９に接続され、ＤＣバイアスボ
ンディングパッド３にはＤＣバイアスワイヤ５がワイヤ
ボンディングされている。FIG. 1 is a plan view showing the configuration of a microwave monolithic integrated circuit device according to an embodiment of the present invention, and the same parts as in the previous figures are given the same reference numerals. In the same figure, M
An MIM capacitor 6 is provided near the DC bias bonding pad 3 of MICl, and the DC bias bonding pad 3 is configured to be short-circuited to the MIM capacitor 6 at high frequency. That is, this M
The upper metal layer of the IM capacitor 6 is connected to the metal chip carrier 7 by the bonding wire 4 and grounded, and the lower metal layer is connected to the DC bias bonding pad 3 through the through holes 8a, tab, respectively. A DC bias wire 5 is connected to the wiring pattern 9 and wire-bonded to the DC bias bonding pad 3 .

このような構成において、ＤＣバイアス電流Ｉは、ＤＣ
バイアスワイヤ５を介してＤＣバイアスボンディングパ
ッド３に供給され、スルーホール８ａによってＭｒＭキ
ャパシタ６の下層へ供給されてＭＩＭキャパシタ６を通
シ、さらにスルーホール８ｂによって上層の配線パター
ン９に供給されて図示しないＦＥＴ等へ供給される。こ
のとき、ＭＩＭキャパシタ６の上層メタル層はボンディ
ングワイヤ４によシメタルチップキャリア７に接地され
、高周波的に短絡されることになる。In such a configuration, the DC bias current I is
It is supplied to the DC bias bonding pad 3 via the bias wire 5, supplied to the lower layer of the MrM capacitor 6 through the through hole 8a, passed through the MIM capacitor 6, and further supplied to the upper layer wiring pattern 9 through the through hole 8b. It is supplied to FETs etc. that do not operate. At this time, the upper metal layer of the MIM capacitor 6 is grounded to the metal chip carrier 7 by the bonding wire 4, and is short-circuited at high frequency.

第２図は本発明の他の実施例であり、ＭＩＭキャパシタ
をメタライズ面によ）接地した場合の構成を示す平面図
である。同図において、第１図と異なる点は、ＭＩＭキ
ャパシタ６をＭＭＩ　Ｃ１の側面メタライズ１０によシ
接地したことにある。これによって接地をより十分にと
ることができるとともに自動ボンダを使用してもボンデ
ィングワイヤ長のばらつきによるＭＭＩ　Ｃ１の高周波
特性のばらつきを考慮する必要がないので、自動化によ
る費用削減が期待できる。FIG. 2 is another embodiment of the present invention, and is a plan view showing a configuration in which an MIM capacitor is grounded (through a metallized surface). This figure differs from FIG. 1 in that the MIM capacitor 6 is grounded to the side metallization 10 of the MMI C1. This allows more sufficient grounding, and even if an automatic bonder is used, there is no need to consider variations in the high frequency characteristics of the MMI C1 due to variations in bonding wire length, so automation can be expected to reduce costs.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＤＣバイアスのポンディ
ングパッド近傍にＭＩＭキャパシタを設けるとともにこ
のＭＩＭキャパシタを接地する接地手段を設けたことに
よ、り、ＤＣバイアスボンディングパッドが高周波的に
短絡されるので、従来のタン７パンコンへのボンディン
グワイヤのインダクタンスによるＭＭＩＣの高周波特性
への影響およびそのボンディングワイヤ長のばらつきに
よるＭＭ　Ｉ　Ｃの高周波特性のばらつきが軽減され、
かつタンパンコンが不要となることにより、その所有面
私および費用を削減できる。また、ボンディングワイヤ
長のばらつきによるＭＭＩＣの高周波特性のばらつきを
考慮する必要がなくなるので、自動ボンダ使用の自動化
による費用削減が期待できるなどの極めて優れた効果が
得られる。As explained above, the present invention provides an MIM capacitor near the DC bias bonding pad and also provides a grounding means for grounding this MIM capacitor, so that the DC bias bonding pad is short-circuited at high frequencies. Therefore, the influence on the high frequency characteristics of the MMIC due to the inductance of the bonding wire to the conventional connector and the variation in the high frequency characteristics of the MMIC due to the variation in the length of the bonding wire are reduced.
In addition, by eliminating the need for a tampan condenser, ownership and costs can be reduced. Further, since it is no longer necessary to take into consideration variations in the high frequency characteristics of the MMIC due to variations in bonding wire length, extremely excellent effects such as cost reduction can be achieved by automating the use of an automatic bonder.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例によるマイクロ波モノリシッ
ク集積回路装置のＭＩＭキャパシタをボンディングワイ
ヤにて接地した場合の構成を示す平面図、第２図は本発
明の他の実施例によるＭＩＭキャパシタを側面メタライ
ズによシ接地した場合の構成を示す平面図、第３図は従
来のマイクロ波モノリシック集積回路装置の構成を示す
平面図である０ １・・・・マイクロ波モノリシック集積回路（ＭＭＩＣ
）、３１１・・・ＤＣバイアスポンディングバッド、４
・・・・ボンディングワイヤ、５φ・・・ＤＣバイアス
ワイヤ、６・・・・メタルインシュレータメタル（ＭＩ
Ｍ）キャパシタ、７・・・・メタルチップキャリア、８
ｍ＋８ｂ・・・φスルーホ−ル、 ・配線パターン、 ・・側 面メタライズ。FIG. 1 is a plan view showing the configuration of a microwave monolithic integrated circuit device according to an embodiment of the present invention when an MIM capacitor is grounded by a bonding wire, and FIG. 2 is a plan view showing a configuration of a MIM capacitor according to another embodiment of the present invention. FIG. 3 is a plan view showing the configuration of a conventional microwave monolithic integrated circuit device.
), 311...DC bias pounding pad, 4
...Bonding wire, 5φ...DC bias wire, 6...Metal insulator metal (MI
M) Capacitor, 7...Metal chip carrier, 8
m+8b...φ through hole, ・Wiring pattern, ・・Side metalization.

Claims (1)

【特許請求の範囲】[Claims] マイクロ波モノリシック集積回路のＤＣバイアスボンデ
ィングパッド近傍にメタルインシュレータメタルキャパ
シタを設けるとともにこのメタルインシュレータキャパ
シタを接地する接地手段を設け、このＤＣバイアスボン
ディングパッドを高周波的に短絡することを特徴とした
マイクロ波モノリシック集積回路装置。A microwave monolithic integrated circuit characterized in that a metal insulator metal capacitor is provided near a DC bias bonding pad of the microwave monolithic integrated circuit, and a grounding means for grounding this metal insulator capacitor is provided to short-circuit this DC bias bonding pad at a high frequency. Integrated circuit device.
JP63193943A 1988-08-03 1988-08-03 Microwave monolithic integrated circuit device Pending JPH0243761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63193943A JPH0243761A (en) 1988-08-03 1988-08-03 Microwave monolithic integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63193943A JPH0243761A (en) 1988-08-03 1988-08-03 Microwave monolithic integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0243761A true JPH0243761A (en) 1990-02-14

Family

ID=16316330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63193943A Pending JPH0243761A (en) 1988-08-03 1988-08-03 Microwave monolithic integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0243761A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11929317B2 (en) 2020-12-07 2024-03-12 Macom Technology Solutions Holdings, Inc. Capacitor networks for harmonic control in power devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11929317B2 (en) 2020-12-07 2024-03-12 Macom Technology Solutions Holdings, Inc. Capacitor networks for harmonic control in power devices

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