JPS624332A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS624332A JPS624332A JP60145013A JP14501385A JPS624332A JP S624332 A JPS624332 A JP S624332A JP 60145013 A JP60145013 A JP 60145013A JP 14501385 A JP14501385 A JP 14501385A JP S624332 A JPS624332 A JP S624332A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- electrode pad
- circuit device
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明畦半導体集積回路装置に関し、特に高周波回路装
置に使用する半導体集積回路装置のボンディング用電極
パッドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of a bonding electrode pad of a semiconductor integrated circuit device used in a high frequency circuit device.
従来、半導体集積回路装置に形成されるボンディング用
電極パッドは第４＠に示すように幅が約１２０μｍの正
方形の導電バター／により構成さにボンディングされた
ボンディングワイヤ、５は内部バタン、６は接触部であ
る。ボンディングワイヤｌとボンディング用電極パッド
１２と接触する部分は、接触部６０部分だけであるが、
ボンディング用電極パッド１２はボンディングの作業性
の向上のために接触部６よ多数倍大きい面積を必要とす
ゐ。Conventionally, a bonding electrode pad formed on a semiconductor integrated circuit device is made of a square conductive butter having a width of about 120 μm, as shown in the figure 4, and is bonded to a bonding wire made of conductive butter, 5 is an internal button, and 6 is a contact. Department. The only part that contacts the bonding wire l and the bonding electrode pad 12 is the contact part 60,
The bonding electrode pad 12 requires an area many times larger than the contact portion 6 in order to improve bonding workability.
このように従来のボンディング用電極パッド１２社、正
方形の導電パターンで形成されて−るため、基板との間
の静電容量が大きく、特に高周波のアナログ回路にｋい
て利得低下等の電気特性の劣化の原因となることが多か
った。例えば、−辺が、１２０μＩｎの正方形のボンデ
ィング用電極パッドと基板との間の静電容量は０．３ｐ
Ｆ程度となる。In this way, conventional bonding electrode pads are formed with square conductive patterns, so the capacitance between them and the substrate is large, which causes electrical characteristics such as gain reduction, especially in high-frequency analog circuits. This often caused deterioration. For example, the capacitance between a square bonding electrode pad whose negative side is 120μIn and the substrate is 0.3p.
It will be about F.
この静電容量は周波数ＩＱＨｚでは約５００Ωのインピ
ーダンスとなシ無視できないことが多い。This capacitance has an impedance of approximately 500Ω at a frequency of IQHz, and is often not negligible.
上述した従来のボンディング用電極パッドは、ボンディ
ング用電極パッド１２から接触部６を除いた部分は、基
板との間に不要な静電容量を発生するという欠点がらる
。The above-described conventional bonding electrode pad has the disadvantage that unnecessary capacitance is generated between the bonding electrode pad 12 and the substrate except for the contact portion 6.
本発明の目的は、上記欠点を除去し、基板との間に不要
な静電容量の発生を少くしたボンディング用電極パッド
を有する半導体集積回路装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a bonding electrode pad that eliminates the above drawbacks and reduces the generation of unnecessary capacitance between the device and the substrate.
本発明の半導体集積回路装置は、内部パターンの延長部
と、この内部パターンの延長部と分離されかつその周囲
に設けられた複数の分離されたパターンからなるボンデ
ィング補強部とから構成されたボンディング用電極パッ
ドを有するものである。A semiconductor integrated circuit device of the present invention is a bonding integrated circuit device that is composed of an extension of an internal pattern and a bonding reinforcing section that is separated from the extension of the internal pattern and is provided around the extension and is formed of a plurality of separated patterns. It has electrode pads.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing one embodiment of the present invention.
第１図において、ボンディング用電極パッド２は内部パ
ターン延長部３とその周囲に形成されたボンディング補
強部４とによシ構成されている。内部パターン延長部３
は内部パターン５と接続されておシ、さらにボンディン
グワイヤｌと電気的に接続される。In FIG. 1, a bonding electrode pad 2 is composed of an internal pattern extension part 3 and a bonding reinforcing part 4 formed around the inner pattern extension part 3. Internal pattern extension 3
is connected to the internal pattern 5, and is further electrically connected to the bonding wire l.
ボンディング補強部４は内部パターン延長部３と分離し
さらに個々に分離した小パターンの集合によシ構成され
ている。このボンディング用電極パッド２ヘボンデイン
グワイヤ１を接続する際はボンディングワイヤｌが内部
パターン延長部３と少なくとも１点で接触する様にボン
ディングを行う。ボンディングワイヤｌと内部パターン
延長部３との接触面積が少なりために、内部パターン延
長部３とボンディングワイヤ１間のボンディング接着強
度は弱いが、ボンディング補強部４の複数のパターンが
同時に接続されるためボンディング接着強度は従来のも
のに比べ低下することはな―。The bonding reinforcing portion 4 is separated from the internal pattern extension portion 3 and is composed of a set of individually separated small patterns. When connecting the bonding wire 1 to the bonding electrode pad 2, bonding is performed so that the bonding wire 1 contacts the internal pattern extension 3 at at least one point. Since the contact area between the bonding wire l and the internal pattern extension 3 is small, the bonding adhesive strength between the internal pattern extension 3 and the bonding wire 1 is weak, but multiple patterns of the bonding reinforcing part 4 are connected simultaneously. Therefore, the bonding adhesive strength does not decrease compared to conventional products.
このボンディング補強部４は内部パターン延長部３と分
離され、さらに個々に分離した小パターンの集合によシ
構成されているため、ボンディングワイヤ１と接触した
ボンディング補強部パターンのみボンディングワイヤ１
と電気的に接続し、それ以外のボンディング補強部のパ
ターンは電気的に絶縁されている。従って基板間と静電
容量を発生する部分は内部パターン延長部３および接触
部６だけとなる。This bonding reinforcing part 4 is separated from the internal pattern extension part 3 and is further composed of a set of individually separated small patterns, so that only the bonding reinforcing part pattern that is in contact with the bonding wire 1 is
The other bonding reinforcement patterns are electrically insulated. Therefore, the internal pattern extension portion 3 and the contact portion 6 are the only portions that generate capacitance between the substrates.
従りて、第４図にて説明した従来のボンディング用電極
パッド１２と比較し大幅に基板間の静電容量を減少させ
ることができる。接触部６０面積ることが可能でアシ、
静電容量は面積に比例するため従来のボンディング用電
極パッド１２に比較第２図および第３図は、本発明の第
２および第３の実施例であシ、内部パターン延長部の形
状を変化させボンディングワイヤ１と接触する確率を高
めたものである。Therefore, the capacitance between the substrates can be significantly reduced compared to the conventional bonding electrode pad 12 described in FIG. 4. It is possible to have a contact area of 60 reeds,
Since the capacitance is proportional to the area, compared to the conventional bonding electrode pad 12, FIGS. 2 and 3 show the second and third embodiments of the present invention, and the shape of the internal pattern extension is changed. This increases the probability of contact with the bonding wire 1.
以上説明したように本発明によれば、ボンディング用電
極パッド、を内部パターン延長部とボンディング補強部
によシ構成し、ボンディングワイヤの接触部以外のボン
ディング補強部が基板との間の静電容量に寄与しない構
造を有するようにし、基板間の静電容量を大幅に減少さ
せた半導体集積回路装置が得られるので、ｅＫ高周波に
て動作する回路を有する半導体集積回路装置においてそ
の効果は大きい。As explained above, according to the present invention, the bonding electrode pad is configured by the internal pattern extension part and the bonding reinforcing part, and the bonding reinforcing part other than the contact part of the bonding wire has a capacitance between it and the substrate. Since it is possible to obtain a semiconductor integrated circuit device having a structure that does not contribute to the electrostatic capacitance between the substrates and significantly reducing the electrostatic capacitance between the substrates, this effect is significant in a semiconductor integrated circuit device having a circuit that operates at eK high frequency.
第１図は本発明の一実施例の平面図、第２図および第３
図は本発咀の第２シよび第３の実施例の平面図、第４図
は従来の半導体集積回路装置のボンディング用電極パッ
ドの平面図である。
１・・・・・・ボンディングワイヤ、２．１２・・・・
・・ボンディング用電極パッド、３・：・・・・内部パ
ターン延長部、４・・・・・・ボンディング補強部、５
・・・・・・内部パターン、６・・・・・・接触部。
第 ２ 顆
Δ本所二ヅ補却師
率３０
率４図FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 and FIG.
The figures are plan views of the second and third embodiments of the present invention, and FIG. 4 is a plan view of a bonding electrode pad of a conventional semiconductor integrated circuit device. 1...Bonding wire, 2.12...
...Bonding electrode pad, 3: ...Internal pattern extension part, 4...Bonding reinforcement part, 5
...Internal pattern, 6...Contact part. 2nd condyle Δ Honjo Nizu Acupuncture rate 30 Rate 4 figure
Claims (1)
離されかつその周囲に設けられた複数の分離されたパタ
ーンからなるボンディング補強部とから構成されたボン
ディング用電極パッドを有することを特徴とする半導体
集積回路装置。It is characterized by having a bonding electrode pad composed of an extension part of an internal pattern and a bonding reinforcing part made up of a plurality of separated patterns, which is separated from and provided around the extension part of the internal pattern. Semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60145013A JPS624332A (en) | 1985-07-01 | 1985-07-01 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60145013A JPS624332A (en) | 1985-07-01 | 1985-07-01 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS624332A true JPS624332A (en) | 1987-01-10 |
Family
ID=15375424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60145013A Pending JPS624332A (en) | 1985-07-01 | 1985-07-01 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS624332A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959706A (en) * | 1988-05-23 | 1990-09-25 | United Technologies Corporation | Integrated circuit having an improved bond pad |
| JP2009135345A (en) * | 2007-11-30 | 2009-06-18 | Fujikura Ltd | Semiconductor device and manufacturing method thereof |
-
1985
- 1985-07-01 JP JP60145013A patent/JPS624332A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959706A (en) * | 1988-05-23 | 1990-09-25 | United Technologies Corporation | Integrated circuit having an improved bond pad |
| JP2009135345A (en) * | 2007-11-30 | 2009-06-18 | Fujikura Ltd | Semiconductor device and manufacturing method thereof |
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