JP2758322B2 - Circuit board for mounting electronic components - Google Patents
Circuit board for mounting electronic componentsInfo
- Publication number
- JP2758322B2 JP2758322B2 JP4261653A JP26165392A JP2758322B2 JP 2758322 B2 JP2758322 B2 JP 2758322B2 JP 4261653 A JP4261653 A JP 4261653A JP 26165392 A JP26165392 A JP 26165392A JP 2758322 B2 JP2758322 B2 JP 2758322B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- stage
- circuit board
- power supply
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は、回路基板、特に、電極
を有する電子部品を載置しかつ前記電極にワイヤを介し
て電気的に接続される電子部品搭載用回路基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board, and more particularly to a circuit board for mounting electronic components having electrodes thereon and electrically connected to the electrodes via wires.
【０００２】[0002]
【従来の技術及びその課題】半導体チップ等の電子部品
を搭載するための回路基板は、電子部品を載置するため
の基板本体と、電子部品に隣接して配置される電極パタ
ーンとを有している。電極パターンは、通常、ソース線
が集まる電源パターン，アース線が集まる接地パターン
及び各信号線が接続される信号パターンから成る。この
電極パターンは、ボンディングワイヤによって電子部品
の各電極と電気的に接続される。2. Description of the Related Art A circuit board for mounting an electronic component such as a semiconductor chip has a substrate main body for mounting the electronic component and an electrode pattern disposed adjacent to the electronic component. ing. The electrode pattern usually includes a power supply pattern where source lines are gathered, a ground pattern where earth lines are gathered, and a signal pattern to which each signal line is connected. This electrode pattern is electrically connected to each electrode of the electronic component by a bonding wire.
【０００３】前記従来の構成では、高速作動及び高密度
実装の要請から半導体チップ等の電子部品の端子数が増
加するのに伴い、基板本体において電子部品搭載部の周
囲には複数段のステージが形成され、それらのステージ
に電極パターンが形成されるようになってきている。こ
のため、回路基板に半導体チップ等の電子部品を搭載す
る場合、基板本体の載置部から外側のステージまでの距
離が長くなり、電子部品と電極パターンとを接続するボ
ンディングワイヤの長さが長くなるという問題が生じ
る。この結果、ワイヤのインダクタンスが高くなってし
まう。また、電極数が多くなるにしたがって、電極パタ
ーンの長さが長くならざるをえず、電極パターンのイン
ダクタンスが高くなる原因となる。In the above-described conventional configuration, a plurality of stages are provided around the electronic component mounting portion in the substrate body as the number of terminals of electronic components such as semiconductor chips increases due to the demand for high-speed operation and high-density mounting. And electrode patterns are being formed on those stages. Therefore, when electronic components such as semiconductor chips are mounted on the circuit board, the distance from the mounting portion of the substrate body to the outer stage becomes longer, and the length of the bonding wire connecting the electronic component and the electrode pattern becomes longer. Problem arises. As a result, the inductance of the wire increases. Further, as the number of electrodes increases, the length of the electrode pattern must be increased, which causes an increase in the inductance of the electrode pattern.
【０００４】ワイヤ及び電極パターンのインダクタンス
が高くなると、雑音特性を悪化させる原因となる。本発
明の目的は、電子部品搭載用回路基板の雑音特性を改善
することにある。[0004] When the inductance of the wire and the electrode pattern is increased, it causes the noise characteristics to deteriorate. An object of the present invention is to improve the noise characteristics of a circuit board for mounting electronic components.
【０００５】[0005]
【課題を解決するための手段】本発明に係る電子部品搭
載用回路基板は、電極を有する電子部品を載置し、電極
にワイヤを介して電気的に接続される電子部品搭載用回
路基板である。この回路基板は、基板本体と、電源パタ
ーンと、接地パターンと、信号パターンとを備えてい
る。基板本体は、電子部品を載置するための載置部と、
載置部に隣接して配置された第１ステージと、載置部と
共に第１ステージを挟む位置に配置された第２ステージ
とを有する。電源パターン及び接地パターンは、第１ス
テージの内周側に互い違いに前記ワイヤに接続するため
の端部パターンが配置され、一方の端部パターンが共通
パターンにより接続された櫛歯状に構成されている。信
号パターンは、第２ステージに配置され、ワイヤに接続
可能である。An electronic component mounting circuit board according to the present invention is an electronic component mounting circuit board on which an electronic component having electrodes is mounted and which is electrically connected to the electrodes via wires. is there. This circuit board includes a board body, a power supply pattern, a ground pattern, and a signal pattern. The substrate body has a mounting portion for mounting electronic components,
It has a first stage arranged adjacent to the mounting portion, and a second stage arranged at a position sandwiching the first stage together with the mounting portion. The power supply pattern and the ground pattern are configured such that end patterns for connecting to the wires are alternately arranged on the inner peripheral side of the first stage, and one end pattern is formed in a comb shape connected by a common pattern. I have. The signal pattern is located on the second stage and is connectable to a wire.
【０００６】[0006]
【作用】本発明に係る電子部品搭載用回路基板では、第
１ステージの内周側に互い違いに配置された電源パター
ン及び接地パターンの端部パターンと電子部品の電極と
がワイヤにより接続される。また、電子部品の電極と第
２ステージに配置された信号パターンとが別のワイヤに
より接続される。In the electronic component mounting circuit board according to the present invention, the end patterns of the power supply pattern and the ground pattern alternately arranged on the inner peripheral side of the first stage are connected to the electrodes of the electronic component by wires. In addition, the electrodes of the electronic component and the signal pattern arranged on the second stage are connected by another wire.
【０００７】このとき、電源パターン及び接地パターン
は、その一方が端部パターンを接続して櫛歯状となす共
通パターンを含んでいるので、パターンのインダクタン
スが低減される。さらに、電源パターン及び接地パター
ンを互いに近接して配置できるため、ワイヤにおけるイ
ンピーダンスが減少する。この結果、電子部品搭載用回
路基板における雑音特性が改善される。At this time, since the power supply pattern and the ground pattern include a common pattern in which one of the power supply pattern and the ground pattern is connected to the end pattern to form a comb-like shape, the inductance of the pattern is reduced. Further, the power supply pattern and the ground pattern can be arranged close to each other, so that the impedance in the wire is reduced. As a result, the noise characteristics of the electronic component mounting circuit board are improved.
【０００８】[0008]
【実施例】図１及び図２に、本発明の一実施例が採用さ
れた回路装置１を示す。この回路装置１は、矩形の板状
の基板本体２と、基板本体２の中央部に搭載された半導
体チップ６とを主として有している。基板本体２は、導
電性の電極パターンからなる電源パターン３，接地パタ
ーン４及び信号パターン５を有している。また、半導体
チップ６の電極（図示せず）と各電極パターン３，４，
５とは、多数本のボンディングワイヤ７によって接続さ
れている。1 and 2 show a circuit device 1 employing an embodiment of the present invention. The circuit device 1 mainly includes a rectangular plate-shaped substrate main body 2 and a semiconductor chip 6 mounted on a central portion of the substrate main body 2. The substrate body 2 has a power supply pattern 3, a ground pattern 4, and a signal pattern 5 made of a conductive electrode pattern. Further, the electrodes (not shown) of the semiconductor chip 6 and the respective electrode patterns 3, 4,
5 are connected by many bonding wires 7.
【０００９】基板本体２は、複数枚のセラミックグリー
ンシートを積層して一体焼結することにより得られたも
のである。基板本体２の中央部には、半導体チップ６を
載置するための平坦な載置部８が形成されている。載置
部８の周囲には、第１ステージ９が矩形帯状に形成され
ている。また、第１ステージ９の周囲には、第１ステー
ジ９よりも高い第２ステージ１０が矩形帯状に形成され
ている。第２ステージ１０の周囲には、蓋体１１を載置
するための外縁部１２が形成されている。外縁部１２に
は、載置部８の空間を封止するため、蓋体１１が接着さ
れている。The substrate body 2 is obtained by laminating a plurality of ceramic green sheets and integrally sintering them. A flat mounting portion 8 for mounting the semiconductor chip 6 is formed at the center of the substrate body 2. A first stage 9 is formed around the mounting section 8 in a rectangular band shape. Around the first stage 9, a second stage 10 that is higher than the first stage 9 is formed in a rectangular band shape. An outer edge 12 on which the lid 11 is placed is formed around the second stage 10. The lid 11 is adhered to the outer edge portion 12 to seal the space of the mounting portion 8.
【００１０】電源パターン３は、第１ステージ９の内周
部に形成されており、基板本体２を厚み方向に貫通する
導電性のスルーホール１３，１５及び内部配線層１４に
よりリード端子１６に接続されている。電源パターン３
は、図３に示すように、同一寸法の多数の矩形部から構
成されている。この矩形部は、第１ステージ９の内周縁
部９ａに沿って等間隔で配置され、さらに、半導体チッ
プ６の電源電極６ａの近傍に対向して設けられている。
電源電極６ａと電源パターン３とはボンディングワイヤ
２１によって接続されている。The power supply pattern 3 is formed on the inner periphery of the first stage 9 and is connected to the lead terminals 16 by conductive through holes 13 and 15 penetrating the substrate body 2 in the thickness direction and the internal wiring layer 14. Have been. Power supply pattern 3
Is composed of a large number of rectangular portions having the same dimensions as shown in FIG. The rectangular portions are arranged at equal intervals along the inner peripheral edge 9 a of the first stage 9, and are provided near the power supply electrodes 6 a of the semiconductor chip 6 so as to face each other.
The power supply electrode 6a and the power supply pattern 3 are connected by a bonding wire 21.
【００１１】接地パターン４は、第１ステージ９の上に
あって電源パターン３の外周側に配置され、電源パター
ン３と互い違いに配置された端部パターン４ａと、各端
部パターン４ａを接続する共通パターン４ｂとからなる
櫛歯状に構成されている。接地パターン４の内周側端部
は、各電源パターン３間に入り込んでいる。また、接地
パターン４の外周側部分は共通パターン４ｂとなって、
第２ステージ１０の下方に延びている（図２）。これに
より、接地パターン４が電源パターン３を三方より取り
囲む構成となる。共通パターン４ｂには複数のスルーホ
ール１７が接続されており、各スルーホール１７はリー
ド端子１８に接続されている。端部パターン４ａは、半
導体チップ６の対向する接地電極６ｂとワイヤ２２によ
り接続されている。The ground pattern 4 is disposed on the outer peripheral side of the power supply pattern 3 on the first stage 9 and connects the end patterns 4a alternately disposed with the power supply pattern 3 to the respective end patterns 4a. It is configured in a comb shape composed of the common pattern 4b. The inner peripheral end of the ground pattern 4 extends between the power patterns 3. The outer peripheral portion of the ground pattern 4 becomes a common pattern 4b,
It extends below the second stage 10 (FIG. 2). Thus, the ground pattern 4 surrounds the power supply pattern 3 from three sides. A plurality of through holes 17 are connected to the common pattern 4b, and each through hole 17 is connected to a lead terminal 18. The end pattern 4 a is connected to a ground electrode 6 b facing the semiconductor chip 6 by a wire 22.
【００１２】信号パターン５は、第２ステージ１０の上
に形成され、内周部が等間隔に配置された電極パターン
からなる。信号パターン５の他端部は外縁部１２の下方
に延び、それぞれが複数のスルーホール１９により各リ
ード端子２０に接続されている。信号パターン５の各電
極パターンは、ワイヤ２３により半導体チップ６の対向
する信号電極６ｃに接続されている。The signal pattern 5 is formed on the second stage 10 and is formed of an electrode pattern whose inner peripheral portions are arranged at equal intervals. The other end of the signal pattern 5 extends below the outer edge 12 and is connected to each lead terminal 20 by a plurality of through holes 19. Each electrode pattern of the signal pattern 5 is connected to the opposing signal electrode 6c of the semiconductor chip 6 by a wire 23.
【００１３】このように前記実施例においては、第１ス
テージ９に電源パターン３と接地パターン４とが接近し
て互い違いに配置されるとともに、両パターン３，４が
長い距離に渡って対向している。また、接地パターン４
は、共通パターン４ｂを有する櫛歯状に形成されてい
る。さらに、電源側及び接地側の各ワイヤ２１，２２は
互いに接近し配置されており、しかもワイヤ２３は、電
源パターン３及び接地パターン４の各ワイヤ２１，２２
間に接近して配置されている。これによって、パターン
部分及びワイヤ部分でのインダクタンスを低減できるよ
うになり、回路装置１の雑音特性を改善できる。As described above, in the above embodiment, the power supply pattern 3 and the ground pattern 4 are arranged close to each other on the first stage 9 and are alternately arranged, and the two patterns 3 and 4 are opposed to each other over a long distance. I have. Also, ground pattern 4
Are formed in a comb shape having a common pattern 4b. Furthermore, the wires 21 and 22 on the power supply side and the ground side are arranged close to each other, and the wires 23 are the wires 21 and 22 of the power supply pattern 3 and the ground pattern 4.
It is located in close proximity. Thereby, the inductance in the pattern portion and the wire portion can be reduced, and the noise characteristic of the circuit device 1 can be improved.
【００１４】〔他の実施例〕 （ａ） 前記実施例では、接地パターン４を櫛歯状に形
成する構成としたが、電源パターン３を櫛歯状に形成し
てもよい。 （ｂ） 前記実施例では、電極パターンを形成するステ
ージを２段に構成したが、電子部品の回路電極に応じ、
ステージの段数は３段以上でもよい。 （ｃ） 前記実施例では、接地パターン４の端部パター
ン４ａと電源パターン３とが互い違いに配置されていた
が、接地パターン４の端部パターン４ａは図４に示すよ
うに、電源パターン３の２つおきに配置する構成として
もよい。[Other Embodiments] (a) In the above embodiment, the ground pattern 4 is formed in a comb shape, but the power supply pattern 3 may be formed in a comb shape. (B) In the above embodiment, the stage for forming the electrode pattern is configured in two stages, but according to the circuit electrode of the electronic component,
The number of stages may be three or more. (C) In the above embodiment, the end pattern 4a of the ground pattern 4 and the power supply pattern 3 are arranged alternately, but the end pattern 4a of the ground pattern 4 is, as shown in FIG. It is good also as composition which arranges every two.
【００１５】[0015]
【発明の効果】本発明に係る電子部品搭載用回路基板で
は、電源パターン及び接地パターンが、第１ステージの
内周側に互い違いに端部パターンが配置され、少なくと
も一方の端部パターンが共通パターンにより接続された
櫛歯状に構成されるとともに、端部パターンがワイヤに
それぞれ接続される。これによって、パターンのインダ
クタンスを低減できる。また、電源パターンと接地パタ
ーンとに接続されるワイヤを近接して配置することがで
き、ワイヤにおけるインダクタンスを低減できる。よっ
て、電子部品搭載用回路基板における雑音特性を改善で
きる。In the electronic component mounting circuit board according to the present invention, the power supply pattern and the ground pattern are alternately arranged on the inner peripheral side of the first stage, and at least one of the end patterns is a common pattern. And the end patterns are connected to the wires, respectively. Thereby, the inductance of the pattern can be reduced. Further, wires connected to the power supply pattern and the ground pattern can be arranged close to each other, and the inductance of the wires can be reduced. Therefore, the noise characteristics of the electronic component mounting circuit board can be improved.
【図１】本発明の一実施例に係る回路装置の平面図であ
り、図２のＩ−Ｉ断面図。FIG. 1 is a plan view of a circuit device according to an embodiment of the present invention, and is a cross-sectional view taken along line II of FIG.
【図２】図１のII−II断面図。FIG. 2 is a sectional view taken along line II-II of FIG.
【図３】図１の一部拡大部分図。FIG. 3 is a partially enlarged partial view of FIG. 1;
【図４】他の実施例を示す図３に相当する図。FIG. 4 is a view corresponding to FIG. 3 showing another embodiment.
２ 基板本体 ３ 電源パターン ４ 接地パターン ５ 信号パターン ６ 半導体チップ ６ａ，６ｂ，６ｃ 電極 ８ 載置部 ９ 第１ステージ １０ 第２ステージ ２１，２２，２３ ワイヤ 2 Substrate body 3 Power supply pattern 4 Ground pattern 5 Signal pattern 6 Semiconductor chip 6a, 6b, 6c Electrode 8 Placement section 9 First stage 10 Second stage 21, 22, 23 Wire
Claims (1)
にワイヤを介して電気的に接続される電子部品搭載用回
路基板であって、 前記電子部品を載置するための載置部と、該載置部に隣
接して配置された第１ステージと、前記載置部と共に前
記第１ステージを挟む位置に配置された第２ステージと
を有する基板本体と、 前記第１ステージの内周側に互い違いに前記ワイヤに接
続するための端部パターンが配置され、一方の端部パタ
ーンが共通パターンにより接続された櫛歯状に構成され
ている電源パターン及び接地パターンと、 前記第２ステージに配置され、前記ワイヤに接続するた
めの信号パターンとを備えた電子部品搭載用回路基板。An electronic component mounting circuit board on which an electronic component having an electrode is mounted and which is electrically connected to the electrode via a wire, wherein a mounting portion for mounting the electronic component is provided. A substrate main body having a first stage disposed adjacent to the mounting portion, and a second stage disposed at a position sandwiching the first stage together with the mounting portion; Connect to the wire alternately on the circumferential side
End pattern for connection is arranged, one end pattern
Configured pectinate shape that over emissions are connected by a common pattern
And a power supply pattern and a ground pattern, which are arranged on the second stage and are connected to the wires .
Circuit board for mounting electronic components, comprising a signal pattern for
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4261653A JP2758322B2 (en) | 1992-09-30 | 1992-09-30 | Circuit board for mounting electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4261653A JP2758322B2 (en) | 1992-09-30 | 1992-09-30 | Circuit board for mounting electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06112359A JPH06112359A (en) | 1994-04-22 |
| JP2758322B2 true JP2758322B2 (en) | 1998-05-28 |
Family
ID=17364902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4261653A Expired - Fee Related JP2758322B2 (en) | 1992-09-30 | 1992-09-30 | Circuit board for mounting electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2758322B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4570868B2 (en) * | 2003-12-26 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2564297B2 (en) * | 1987-03-24 | 1996-12-18 | 新光電気工業株式会社 | Circuit board |
| JPS6448039U (en) * | 1987-09-21 | 1989-03-24 | ||
| JP2915983B2 (en) * | 1990-10-04 | 1999-07-05 | 新光電気工業株式会社 | Semiconductor storage device |
-
1992
- 1992-09-30 JP JP4261653A patent/JP2758322B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06112359A (en) | 1994-04-22 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |