JPH02238655A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH02238655A JPH02238655A JP5901889A JP5901889A JPH02238655A JP H02238655 A JPH02238655 A JP H02238655A JP 5901889 A JP5901889 A JP 5901889A JP 5901889 A JP5901889 A JP 5901889A JP H02238655 A JPH02238655 A JP H02238655A
- Authority
- JP
- Japan
- Prior art keywords
- lead part
- capacitor
- insulator
- semiconductor package
- inner lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 12
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 5
- 238000005219 brazing Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の改良されたパッケージの構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improved package structure for a semiconductor device.
従来、半導体パッケージに使用されているリードフレー
ムを用いたパッケージ構造の一例を第３図の断面図に示
す。即ち、リードフレーム１１は素子搭載部１２とリー
ド部１３を有しており、素子搭載部１２上に半導体素子
１５をマウント用ロー材１４によって搭載し、半導体素
子１５の電極とリード部１３とをポンディング用金属線
１６で接続している。そして、全体を封止樹脂１７で封
止して半導体パッケージを構成している。An example of a package structure using a lead frame conventionally used in semiconductor packages is shown in the cross-sectional view of FIG. That is, the lead frame 11 has an element mounting part 12 and a lead part 13. A semiconductor element 15 is mounted on the element mounting part 12 using a mounting brazing material 14, and the electrodes of the semiconductor element 15 and the lead parts 13 are connected. They are connected by a bonding metal wire 16. Then, the whole is sealed with a sealing resin 17 to form a semiconductor package.
上述した従来の半導体パッケージで構成される半導体装
置では、プリント回路基板等に実装する際にコンデンサ
やインダクタンスを接続する場合には、これらの部品を
外付け部品として実装する必要がある。このため、実装
に際しての部品数が増大し、実装作業が煩雑になるとと
もに、実装スペースが増大して実装密度が低下されると
いう問題がある。In the semiconductor device configured with the conventional semiconductor package described above, when connecting a capacitor or inductance when mounting it on a printed circuit board or the like, it is necessary to mount these components as external components. For this reason, there are problems in that the number of components required for mounting increases, the mounting work becomes complicated, and the mounting space also increases, resulting in a reduction in packaging density.
本発明は上述した問題を解消した半導体パッケージを提
供することを目的とする。An object of the present invention is to provide a semiconductor package that solves the above-mentioned problems.
本発明の半導体パッケージは、導電性材料からなるリー
ドフレームのリード部に絶縁体を介して導電性材料のイ
ンナリード部を接続し、リードフレームの素子搭載部に
搭載した半導体素子をこのインナリード部に電気接続し
た構成としている。In the semiconductor package of the present invention, an inner lead portion made of a conductive material is connected to a lead portion of a lead frame made of a conductive material via an insulator, and a semiconductor element mounted on an element mounting portion of the lead frame is mounted on the inner lead portion. The structure is electrically connected to the
上述した構成では、インナリード部．絶縁体及びリード
部でコンデンサを構成し、或いは絶縁体に設けたメタル
パターンでインダクタンス等の素子を構成し、これら受
動素子を半導体パッケージ内に一体的に形成する。In the above configuration, the inner lead part. An insulator and a lead portion constitute a capacitor, or a metal pattern provided on an insulator constitutes an element such as an inductance, and these passive elements are integrally formed within a semiconductor package.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
（第１実施例） 第１図は本発明の第１実施例の断面図である。(First example) FIG. 1 is a sectional view of a first embodiment of the present invention.
導電性材料からなるリードフレーム１は、半導体素子搭
載部２とリード部３とで構成される。前記素子搭載部２
にはロー材４を用いて半導体素子５を搭載している。ま
た、リード部３はインナリード部３ａを別体に構成し、
絶縁体８を介してリード部３の先端に一体的に接続した
構成としている。これにより、リード部３では絶縁体８
を誘電体とし、インナリード部３ａを他方の電極とする
コンデンサを構成することになる。A lead frame 1 made of a conductive material is composed of a semiconductor element mounting part 2 and a lead part 3. The element mounting section 2
A semiconductor element 5 is mounted using a brazing material 4. Further, the lead part 3 has an inner lead part 3a formed separately,
It has a structure in which it is integrally connected to the tip of the lead part 3 via an insulator 8. As a result, in the lead portion 3, the insulator 8
A capacitor is constructed in which the electrode is used as a dielectric and the inner lead portion 3a is used as the other electrode.
そして、半導体素子５の電極とリード部３とをボンディ
ング用金属線６によって相互に電気接続している。この
とき、コンデンサを接続する必要がある場合には、ポン
ディング用金属線６をインナリード部３ａに接続してい
る。しかる上で、全体を封止樹脂７により封止している
。The electrodes of the semiconductor element 5 and the lead portions 3 are electrically connected to each other by a bonding metal wire 6. At this time, if it is necessary to connect a capacitor, the bonding metal wire 6 is connected to the inner lead portion 3a. Then, the entire structure is sealed with a sealing resin 7.
この構成によれば、リード部３ではインナリード部３ａ
と絶縁体８によってコンデンサが構成されることになり
、ボンディング用金属線６をインナリード部３ａに接続
したときには、コンデンサが一体的に接続されることに
なる。そして、このコンデンサは半導体素子５と共に封
止樹脂７内に一体的に封止されるため、この半導体パッ
ケージを実装する際にはコンデンサを外付け部品として
用意する必要はなく、実装を容易にするとともに、実装
スペースの低減を実現できる。According to this configuration, in the lead portion 3, the inner lead portion 3a
A capacitor is constituted by the insulator 8, and when the bonding metal wire 6 is connected to the inner lead portion 3a, the capacitor is integrally connected. Since this capacitor is integrally sealed in the sealing resin 7 together with the semiconductor element 5, there is no need to prepare the capacitor as an external component when mounting this semiconductor package, which facilitates mounting. At the same time, the mounting space can be reduced.
（第２実施例） 第２図は本発明の第２実施例の平面図である。(Second example) FIG. 2 is a plan view of a second embodiment of the invention.
この第２実施例の断面構造は第１実施例と同じであり、
同一部分には同一符号を付してある。The cross-sectional structure of this second embodiment is the same as that of the first embodiment,
Identical parts are given the same reference numerals.
こ９実施例では、リード部３に設ける絶縁体８のうち、
一部の絶縁体８Ａを充分に長く形成し、かつこの絶縁体
８Ａの表面一部にインダクタンス用のメタルパターン９
を形成している。そして、インダクタンスの接続が必要
とされる場合には、このメタルパターン９に対応するイ
ンナリード部３ａにボンディング用金属線６を接続して
いる。In this ninth embodiment, among the insulators 8 provided in the lead portion 3,
A part of the insulator 8A is formed sufficiently long, and a metal pattern 9 for inductance is formed on a part of the surface of this insulator 8A.
is formed. When an inductance connection is required, a bonding metal wire 6 is connected to the inner lead portion 3a corresponding to the metal pattern 9.
したがって、絶縁体８Ａが充分に長いため、リード部３
とインナリード部３ａとの間はコンデンサとして構成さ
れるよりもインダクタンスとして構成されることになり
、結果として半導体パッケージ内にインダクタンスが一
体的に接続されることになる。他のリード部３ではコン
デンサが構成されることはいうまでもない。Therefore, since the insulator 8A is sufficiently long, the lead portion 3
The space between and the inner lead portion 3a is configured as an inductance rather than a capacitor, and as a result, the inductance is integrally connected within the semiconductor package. It goes without saying that the other lead portions 3 constitute a capacitor.
これにより、半導体パッケージの実装に際しては、イン
ダクタンスを外付け部品として用意する必要はなく、実
装の容易化、実装スペースの低減が実現できる。Thereby, when mounting a semiconductor package, there is no need to prepare an inductance as an external component, and it is possible to simplify the mounting and reduce the mounting space.
なお、同様にして絶縁体に抵抗素子を形成すれば、半導
体パッケージ内に抵抗を構成することも可能である。Note that by forming a resistive element on an insulator in the same manner, it is also possible to configure a resistor within a semiconductor package.
〔発明の効果］
以上説明したように本発明は、リードフレームのリード
部に絶縁体を介してインナリード部を接続し、これらイ
ンナリード部，絶縁体及びリード部でコンデンサを構成
し、或いは絶縁体に設けたメタルパターンでインダクタ
ンス等の素子を構成しているので、これら受動素子を一
体的に形成した半導体パッケージを構成でき、実装の容
易化を図るとともに、実装スペースの低減を図ることが
できる効果がある。[Effects of the Invention] As explained above, the present invention connects the inner lead portion to the lead portion of a lead frame via an insulator, and configures a capacitor with the inner lead portion, the insulator, and the lead portion, or Since elements such as inductance are constructed using metal patterns provided on the body, it is possible to construct a semiconductor package in which these passive elements are integrally formed, which facilitates mounting and reduces mounting space. effective.
第１図は本発明の第１実施例の縦断面図、第２図は本発
明の第２実施例の平面図、第３図は従来構造の縦断面図
である。
１．１１・・・リードフレーム、２．１２・・・素子搭
載部、３，１３・・・リード部、４．１４・・・ロー材
、５．１５・・・半導体素子、６．１６・・・ボンディ
ング用金属線、７，１７・・・封止樹脂、８，８Ａ・・
・絶縁体、９・・・メタルパターン（インダクタンス）
。
第２
図
９ノタルハフーン
第３
図FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a plan view of a second embodiment of the invention, and FIG. 3 is a longitudinal sectional view of a conventional structure. 1.11... Lead frame, 2.12... Element mounting part, 3, 13... Lead part, 4.14... Raw material, 5.15... Semiconductor element, 6.16. ...Metal wire for bonding, 7,17...Sealing resin, 8,8A...
・Insulator, 9...Metal pattern (inductance)
. 2nd figure 9 Notarhahoon 3rd figure
Claims (1)
縁体を介して導電性材料のインナリード部を接続し、前
記リードフレームの素子搭載部に搭載した半導体素子を
前記インナリード部に電気接続したことを特徴とする半
導体パッケージ。1. An inner lead part made of a conductive material was connected to a lead part of a lead frame made of a conductive material via an insulator, and a semiconductor element mounted on an element mounting part of the lead frame was electrically connected to the inner lead part. A semiconductor package characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5901889A JPH02238655A (en) | 1989-03-10 | 1989-03-10 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5901889A JPH02238655A (en) | 1989-03-10 | 1989-03-10 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02238655A true JPH02238655A (en) | 1990-09-20 |
Family
ID=13101131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5901889A Pending JPH02238655A (en) | 1989-03-10 | 1989-03-10 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02238655A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459350A (en) * | 1993-01-13 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Resin sealed type semiconductor device |
| US5589709A (en) * | 1992-12-03 | 1996-12-31 | Linear Technology Inc. | Lead frame capacitor and capacitively-coupled isolator circuit using same |
-
1989
- 1989-03-10 JP JP5901889A patent/JPH02238655A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5589709A (en) * | 1992-12-03 | 1996-12-31 | Linear Technology Inc. | Lead frame capacitor and capacitively-coupled isolator circuit using same |
| US5650357A (en) * | 1992-12-03 | 1997-07-22 | Linear Technology Corporation | Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same |
| US5926358A (en) * | 1992-12-03 | 1999-07-20 | Linear Technology Corporation | Lead frame capacitor and capacitively-coupled isolator circuit using same |
| US5945728A (en) * | 1992-12-03 | 1999-08-31 | Linear Technology Corporation | Lead frame capacitor and capacitively coupled isolator circuit |
| US5459350A (en) * | 1993-01-13 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Resin sealed type semiconductor device |
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