JPH0228958A - High-frequency high-output transistor - Google Patents
High-frequency high-output transistorInfo
- Publication number
- JPH0228958A JPH0228958A JP63179732A JP17973288A JPH0228958A JP H0228958 A JPH0228958 A JP H0228958A JP 63179732 A JP63179732 A JP 63179732A JP 17973288 A JP17973288 A JP 17973288A JP H0228958 A JPH0228958 A JP H0228958A
- Authority
- JP
- Japan
- Prior art keywords
- wires
- collector pad
- silicon
- output
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010931 gold Substances 0.000 claims abstract description 9
- 229910052737 gold Inorganic materials 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高周波トランジスタに係り、特に外囲器内
にＲＦクシヤント整合回路を設けた高周波高出力トラン
ジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high frequency transistor, and more particularly to a high frequency, high output transistor provided with an RF cushion matching circuit within an envelope.
（従来の技術〕
従来のこの種の高周波高出力トランジスタの概略構成を
第３図に示す。(Prior Art) FIG. 3 shows a schematic configuration of a conventional high frequency, high output transistor of this type.
この図において、１ａ、１ｂはトランジスタチップ、２
ａ、２ｂはエミッタ電極、３ａ、３ｂはベース電極、４
は誘電体基板面にパターニングされた金属部（コレクタ
パッド）で、各トランジスタチップｉａ、ｉｂのコレク
タ電極を共通に接続する。５ａ、５ｂはバイパス用のＭ
ＯＳコンデンサ、６．７は人力および出力リード、８ａ
、８ｂは入力ワイヤで、入カリードロからエミッタ電極
２ａ、２ｂに接続されている。９ａ、９ｂは接地ワイヤ
で、ベース電極３ａ、３ｂから接地導体１３へ接続され
ている。１０ａ、１０ｂは出力ワイヤで、コレクタパッ
ド４から出カリードアへ接続されている。１１ａ、１１
ｂはＲＦシャントワイヤで、コレクタパッド４からＭＯ
Ｓコンデンサ５ａ、５ｂに接続されている。１２は外囲
器、１４は絶縁部、１５は前記トランジスタチップ１ａ
、Ｉｂのダイボンド時に生じるはんだ流れ部である。In this figure, 1a and 1b are transistor chips, 2
a, 2b are emitter electrodes, 3a, 3b are base electrodes, 4
is a metal part (collector pad) patterned on the dielectric substrate surface, which commonly connects the collector electrodes of each transistor chip ia and ib. 5a and 5b are M for bypass
OS capacitor, 6.7 is human power and output lead, 8a
, 8b are input wires connected from the input wire to the emitter electrodes 2a, 2b. Ground wires 9a and 9b are connected from the base electrodes 3a and 3b to the ground conductor 13. 10a and 10b are output wires connected from the collector pad 4 to the output door. 11a, 11
b is the RF shunt wire, from collector pad 4 to MO
It is connected to S capacitors 5a and 5b. 12 is an envelope, 14 is an insulating part, and 15 is the transistor chip 1a.
, Ib is a solder flow portion that occurs during die bonding.
この従来例の構成にあっては、入カリードロに入力され
る高周波信号は、エミッタ電極２ａ。In the configuration of this conventional example, the high frequency signal input to the input electrode is transmitted to the emitter electrode 2a.
２ｂに接続される入力ワイヤ８ａ、８ｂを介し、エミッ
タに導かれて増幅され、コレクタから出力ワイヤ１０ａ
、１０ｂ、出カリ−ドアを経て出力される。2b to the emitter and is amplified, and from the collector to the output wire 10a.
, 10b, is outputted through the output carriage door.
なお、ＲＦシャントワイヤ１１ａ、１１ｂ、ＭｏＳコン
デンサ５ａ、５ｂおよび出力ワイヤ１゜ａ、１０ｂはＲ
Ｆシャント型の出力側内部整合回路を構成する。Note that the RF shunt wires 11a, 11b, MoS capacitors 5a, 5b, and output wires 1°a, 10b are R
Configures an F-shunt type output-side internal matching circuit.
（発明が解決しようとする課題）
上記のような従来の高周波高出力トランジスタは、トラ
ンジスタチップｉａ、ｉｂのダイボンド時に生じるはん
だ流れ部１５によりＲＦシャントワイヤ１１ａ、１１ｂ
をはんだ流れ部１５の上からワイヤボンディングする必
要があり、信頼性がそこなわれるという問題点があった
。(Problems to be Solved by the Invention) The conventional high-frequency, high-output transistor as described above has the RF shunt wires 11a, 11b caused by the solder flow portion 15 generated during die bonding of the transistor chips ia, ib.
It is necessary to perform wire bonding from above the solder flow portion 15, which poses a problem in that reliability is impaired.
この発明は、上記のような問題点を解消するためになさ
れたもので、はんだ流れ部の上からワイヤを接続するこ
となく、信頼度の高い高周波高出力トランジスタを得る
ことを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a highly reliable high-frequency, high-output transistor without connecting wires from above the solder flow area.
この発明に係る高周波高出力トランジスタは、コレクタ
パッド上に表裏に金蒸着した低抵抗のシリコン片を設置
し、このシリコン片上からワイヤを接続したものである
。The high-frequency, high-output transistor according to the present invention has a low-resistance silicon piece with gold vapor deposited on both sides placed on a collector pad, and a wire is connected from above the silicon piece.
（作用）
この発明においては、コレクタパッド上に表裏が金蒸着
された低抵抗のシリコン片を設け、このシリコン片上か
らワイヤを接続する構成としたことから、高周波特性を
低下させることなく、ワイヤボンディングを、はんだで
汚れていないシリコン片上へ行うことができ信頼性が向
上する。(Function) In this invention, a low-resistance silicon piece whose front and back sides are gold-deposited is provided on the collector pad, and a wire is connected from above this silicon piece, so wire bonding can be performed without deteriorating high frequency characteristics. The solder can be done on a clean piece of silicon, improving reliability.
第１図はこの発明の高周波高出力トランジスタの一実施
例の概略構成を示すものである。FIG. 1 shows a schematic configuration of an embodiment of a high frequency, high output transistor of the present invention.
この図において、第３図と同一符号は同一構成部分を示
すが、この実施例におけるＲＦシャントワイヤｌｌａ、
１１ｂは、コレクタパッド４上に設置された表裏に金蒸
着したシリコン（サブストレート）片１６ａ、１６ｂ上
からバイパス用のＭＯＳコンデンサ５ａ、５ｂに接続さ
れる。In this figure, the same reference numerals as in FIG. 3 indicate the same components, but the RF shunt wires lla,
11b is connected to bypass MOS capacitors 5a, 5b from above silicon (substrate) pieces 16a, 16b, which are placed on the collector pad 4 and have gold vapor deposited on the front and back sides.
第２図はシリコン（サブストレート）片１６ａ、１６ｂ
の断面側面図である。低抵抗のシリコン片１６ａ（１６
ｂ）の表裏にメタル金１６ｃが蒸着されている。Figure 2 shows silicon (substrate) pieces 16a and 16b.
FIG. Low resistance silicon piece 16a (16
Metal gold 16c is deposited on the front and back sides of b).
このように、ＲＦシャントワイヤ１１ａ、１１ｂを低抵
抗のシリコン（サブストレート）片１６ａ、１６ｂ上か
ら接続することにより、はんだで汚れたコレクタパッド
４にワイヤボンディングする必要はなくなる。By connecting the RF shunt wires 11a and 11b from above the low-resistance silicon (substrate) pieces 16a and 16b in this way, there is no need for wire bonding to the collector pad 4 contaminated with solder.
なお、上記実施例では、内部整合回路が出力側のＲＦク
シヤント整合回路のみの場合を示したが、入力側および
出力側にその他の整合回路を設ける場合も同様である。In the above embodiments, the case where the internal matching circuit is only the RF cushion matching circuit on the output side is shown, but the same applies to the case where other matching circuits are provided on the input side and the output side.
また、上記実施例ではＲＦシャントワイヤ１１ａ、１１
ｂの場合を示したが、出力ワイヤ１゜ａ、１０ｂの場合
も同様の効果が得られる。Further, in the above embodiment, the RF shunt wires 11a, 11
Although case b is shown, similar effects can be obtained in case of output wires 1°a and 10b.
この発明は以上説明したとおり、コレクタパッド上に表
裏に金蒸着したシリコン片を設け、このシリコン片上か
らワイヤを接続したので、コレクタパッド上にトランジ
スタチップをダイボンドした際のはんだ流れの状態のコ
レクタパッド上にワイヤを接続しなくてすみ、はんだで
汚れていないメタル金玉へワイヤボンディングができる
。したがって、ボンディングの信頼性が向上し、高周波
特性を低下させることなく、高信頼性の高周波高出力ト
ランジスタが得られる。As explained above, in this invention, a silicon piece with gold evaporated on the front and back sides is provided on the collector pad, and a wire is connected from above the silicon piece, so that the collector pad is in the state of solder flow when a transistor chip is die-bonded on the collector pad. There is no need to connect wires on top, and wire bonding can be done to metal balls that are not contaminated with solder. Therefore, bonding reliability is improved, and a highly reliable high frequency, high output transistor can be obtained without deteriorating high frequency characteristics.
第１図はこの発明の高周波高出力トランジスタの一実施
例を示す平面図、第２図はこの発明に使用するシリコン
（サブストレート）片の断面側面図、第３図は従来の高
周波高出力トランジスタを示す平面図である。
図において、１ａ、１ｂはトランジスタチップ、２ａ、
２ｂはエミッタ電極、３ａ、３．ｂはベース電極、４は
コレクタパッド、５ａ、５ｂはＭｏＳコンデンサ、６は
入力リード、７は出力リード、８ａ、 ８ｂは入力ワイ
ヤ、９ａ、９ｂは接地ワイヤ、１０ａ、１０ｂは出力ワ
イヤ、１１ａ。
１１ｂはＲＦシャントワイヤ、１２は外囲器、１３は接
地導体、１４は絶縁部、１５ははんだ流れ部、１６ａ、
１６ｂはシリコン（サブストレート）片、１６ｃはメタ
ル金である。
なお、各図中の同一符号は同一または相当部分を示す。Fig. 1 is a plan view showing an embodiment of a high-frequency, high-output transistor of the present invention, Fig. 2 is a cross-sectional side view of a silicon (substrate) piece used in this invention, and Fig. 3 is a conventional high-frequency, high-output transistor. FIG. In the figure, 1a and 1b are transistor chips, 2a,
2b is an emitter electrode; 3a, 3. b is a base electrode, 4 is a collector pad, 5a and 5b are MoS capacitors, 6 is an input lead, 7 is an output lead, 8a and 8b are input wires, 9a and 9b are ground wires, 10a and 10b are output wires, and 11a. 11b is an RF shunt wire, 12 is an envelope, 13 is a ground conductor, 14 is an insulation part, 15 is a solder flow part, 16a,
16b is a silicon (substrate) piece, and 16c is metal gold. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
ジスタチップとバイパス用のコンデンサを備え、前記ト
ランジスタチップがダイボンドされるコレクタパッド上
から前記コンデンサおよび出力リードにそれぞれワイヤ
で接続され内部整合回路が構成される高周波高出力トラ
ンジスタにおいて、前記コレクタパッド上に表裏に金蒸
着したシリコン片を設け、このシリコン片上から前記ワ
イヤを接続したことを特徴とする高周波高出力トランジ
スタ。A transistor chip and a bypass capacitor are provided between the input lead and the output lead in the envelope, and an internal matching circuit is connected to the capacitor and the output lead by wires from above the collector pad to which the transistor chip is die-bonded. A high-frequency, high-output transistor comprising a high-frequency, high-output transistor, characterized in that a silicon piece with gold evaporated on the front and back sides is provided on the collector pad, and the wire is connected from above the silicon piece.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63179732A JPH0228958A (en) | 1988-07-18 | 1988-07-18 | High-frequency high-output transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63179732A JPH0228958A (en) | 1988-07-18 | 1988-07-18 | High-frequency high-output transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0228958A true JPH0228958A (en) | 1990-01-31 |
Family
ID=16070901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63179732A Pending JPH0228958A (en) | 1988-07-18 | 1988-07-18 | High-frequency high-output transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0228958A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0600694A1 (en) * | 1992-11-30 | 1994-06-08 | STMicroelectronics, Inc. | Improved transistor device layout |
-
1988
- 1988-07-18 JP JP63179732A patent/JPH0228958A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0600694A1 (en) * | 1992-11-30 | 1994-06-08 | STMicroelectronics, Inc. | Improved transistor device layout |
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