JPH0697203A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0697203A
JPH0697203A JP4136441A JP13644192A JPH0697203A JP H0697203 A JPH0697203 A JP H0697203A JP 4136441 A JP4136441 A JP 4136441A JP 13644192 A JP13644192 A JP 13644192A JP H0697203 A JPH0697203 A JP H0697203A
Authority
JP
Japan
Prior art keywords
source
semiconductor device
bonding pad
bonding wire
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4136441A
Other languages
Japanese (ja)
Inventor
Osamu Shiozaki
修 塩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4136441A priority Critical patent/JPH0697203A/en
Publication of JPH0697203A publication Critical patent/JPH0697203A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve power gain by a method wherein capacitance is formed in the form of direct connection against an earth inductance component and it is series-resonated. CONSTITUTION:A field effect transistor chip 3 and a chip capacitor 4 are mounted on the flange 2 in a package using the soldering material such as gold, tin and the like. The source bonding pad 5 of the transistor chip 3 and the chip capacitor 4 are connected by the bonding wire 6 of gold and the like. In this case, when the earth inductance, to be formed on the bonding wire 6, is set at L, the capacitance of the chip capacitor 4 is set at C and operating frequency is set at (f), the bonding wire 6 and the chip capacitor 4 are set in such a manner that the relational expression of f=1/(2pisq. rt. LC) will be formed. An effective earth inductance component is brought into an almost zero state, and this contributes greatly to the improvement of power gain in a high frequency operation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
高周波，高出力用途にて使用する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device used for high frequency and high power applications.

【０００２】[0002]

【従来の技術】従来の高周波，高出力用途のＧａＡｓ系
の電界効果トランジスタチップを有する半導体装置の場
合、図３に示すように、放熱性を良くするために電界効
果トランジスタチップ３を銅等の放熱性の良い金属でで
きているフランジ２に直接マウントする。さらに、フラ
ンジ２は、電気的に接地されている。そこで、電界効果
トランジスタチップ３の接地領域、即ち、ソース領域と
フランジ２との間の電気的接続は、金線等のボンディン
グワイヤ６により接続することにより実現する。2. Description of the Related Art In the case of a conventional semiconductor device having a GaAs-based field effect transistor chip for high frequency and high output use, as shown in FIG. It is mounted directly on the flange 2 made of metal with good heat dissipation. Further, the flange 2 is electrically grounded. Therefore, the grounding area of the field effect transistor chip 3, that is, the electrical connection between the source area and the flange 2 is realized by connecting the bonding wire 6 such as a gold wire.

【０００３】一方、ソース部（ストライプ部またはボン
ディングパッド部）にバイアホールを備えた電界効果ト
ランジスタチップを有する半導体装置の場合は、直接マ
ウントすることにより、電界効果トランジスタチップ３
の接地とフランジ２は電気的に接続される。On the other hand, in the case of a semiconductor device having a field effect transistor chip having a via hole in the source part (stripe part or bonding pad part), the field effect transistor chip 3 is mounted by directly mounting.
And the flange 2 are electrically connected.

【０００４】どちらの場合においても、高周波的には完
全なショートではなく、ある値のインダクタンス成分を
介して電界効果トランジスタチップ３のソース部と外部
接地であるフランジ２が接続されることは避けられな
い。In either case, it is possible to avoid connecting the source portion of the field effect transistor chip 3 and the flange 2 which is the external ground via an inductance component of a certain value, not a complete short circuit in terms of high frequency. Absent.

【０００５】[0005]

【発明が解決しようとする課題】このような従来構造の
半導体装置の場合は、金線等のボンディングワイヤによ
る接地接続にしろ、ソース部に施したバイアホールによ
る接地接続にしろ高周波的にはある値のインダクタンス
成分が介在し、高周波で動作する場合には、インダクタ
ンス成分が損失となって半導体装置の利得等の低下をひ
き起こし高周波動作が不安定になるという問題点があっ
た。In the case of a semiconductor device having such a conventional structure, whether it is grounded by a bonding wire such as a gold wire or grounded by a via hole provided in the source portion is available in terms of high frequency. When operating at a high frequency due to the presence of an inductance component of the value, there is a problem that the inductance component becomes a loss, which causes a decrease in the gain of the semiconductor device and the like, and the high frequency operation becomes unstable.

【０００６】本発明の目的は、インダクタンス成分の損
失による利得等の低下がなく、高周波動作が安定な半導
体装置を提供することにある。An object of the present invention is to provide a semiconductor device in which high-frequency operation is stable without a decrease in gain and the like due to loss of an inductance component.

【０００７】[0007]

【課題を解決するための手段】本発明は、（１）ソース
と該ソースに接続するソースボンディングパッドとを備
えた電界効果トランジスタチップと、該電界効果トラン
ジスタチップの前記ソースボンディングパッドに金線を
含むボンディングワイヤを介して接続するチップキャパ
シタとを同一パッケージ内に装着した半導体装置におい
て、前記ボンディングワイヤにて形成される接地インダ
クタンスをＬ，前記チップキャパシタが持つ容量をＣ，
動作周波数をｆとしたときに、The present invention provides (1) a field effect transistor chip having a source and a source bonding pad connected to the source, and a gold wire on the source bonding pad of the field effect transistor chip. In a semiconductor device in which a chip capacitor connected via a bonding wire including the same is mounted in the same package, a ground inductance formed by the bonding wire is L, a capacity of the chip capacitor is C,
When the operating frequency is f,

【０００８】 [0008]

【０００９】の関係式が成立することを特徴とする。It is characterized in that the relational expression of is satisfied.

【００１０】（２）ソースと該ソースに接続するソース
ボンディングパッドと該ソースボンディングパッドを接
地面に電気的に接続する金線を含むボンディングワイヤ
と前記ソースボンディングパッドの裏面に形成された有
底の非貫通バイアホールと該バイアホールの内面全面に
形成されたメタライズ層とを備えた電界効果トランジス
タチップをパッケージ内に装着した半導体装置におい
て、前記ボンディングワイヤにて形成される接地インダ
クタンスをＬ，前記バイアホール底部の前記メタライズ
層と前記ソースボンディングパッド間に形成されるキャ
パシタの容量をＣ，動作周波数をｆとしたときに、(2) A source, a source bonding pad connected to the source, a bonding wire including a gold wire electrically connecting the source bonding pad to a ground plane, and a bottomed bottom formed on the back surface of the source bonding pad. In a semiconductor device in which a field effect transistor chip including a non-penetrating via hole and a metallization layer formed on the entire inner surface of the via hole is mounted in a package, a grounding inductance formed by the bonding wire is L, and the via is formed. When the capacitance of the capacitor formed between the metallization layer at the bottom of the hole and the source bonding pad is C and the operating frequency is f,

【００１１】 [0011]

【００１２】の関係式が成立することを特徴とする。It is characterized in that the relational expression of is satisfied.

【００１３】[0013]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.

【００１４】図１は本発明の第１の実施例の平面図であ
る。FIG. 1 is a plan view of the first embodiment of the present invention.

【００１５】第１の実施例は、図１に示すように、ま
ず、半導体装置のパッケージ１内のフランジ２に電界効
果トランジスタチップ３とチップキャパシタ４を金−ス
ズ等のろう材によってマウントする。In the first embodiment, as shown in FIG. 1, first, a field effect transistor chip 3 and a chip capacitor 4 are mounted on a flange 2 in a package 1 of a semiconductor device with a brazing material such as gold-tin.

【００１６】次に、電界効果トランジスタチップ３のソ
ースボンディングパッド５とチップキャパシタ４を金線
等のボンディングワイヤ６にて接続する。Next, the source bonding pad 5 of the field effect transistor chip 3 and the chip capacitor 4 are connected by a bonding wire 6 such as a gold wire.

【００１７】この場合、ボンディングワイヤ６にて形成
される接地インダクタンスをＬ，チップキャパシタ４が
持つ容量をＣ，そして半導体装置の動作周波数をｆとす
ると、In this case, if the ground inductance formed by the bonding wire 6 is L, the capacitance of the chip capacitor 4 is C, and the operating frequency of the semiconductor device is f,

【００１８】 [0018]

【００１９】の関係式が成立するようにボンディングワ
イヤ６とチップキャパシタ４を設定する。The bonding wire 6 and the chip capacitor 4 are set so that the relational expression of is satisfied.

【００２０】図２は本発明の第２の実施例のバイアホー
ル部の部分拡大断面図である。FIG. 2 is a partially enlarged sectional view of the via hole portion according to the second embodiment of the present invention.

【００２１】第２の実施例は、図２に示すように、ま
ず、電界効果トランジスタチップ３の表面にソースボン
ディングパッド７を設ける。In the second embodiment, as shown in FIG. 2, first, the source bonding pad 7 is provided on the surface of the field effect transistor chip 3.

【００２２】次に、電界効果トランジスタチップのＧａ
Ａｓ層９の裏面よりバイアホール８をエッチング等によ
り形成する。ここで、図２より明かなように、バイアホ
ール８を表面のソースボンディングパッド７まで貫通さ
せないで、ある厚さのＧａＡｓ層９が残るように形成す
る。Next, Ga of the field effect transistor chip
The via hole 8 is formed from the back surface of the As layer 9 by etching or the like. Here, as is clear from FIG. 2, the GaAs layer 9 having a certain thickness is formed without penetrating the via hole 8 to the source bonding pad 7 on the surface.

【００２３】次に、バイアホール８の内面全面にバイア
ホール内面メタライズ層１０をなめらかに形成する。Next, the via hole inner surface metallized layer 10 is formed smoothly on the entire inner surface of the via hole 8.

【００２４】ここで、ソースボンディングパッド７を接
地する金線等のボンディングワイヤにて形成される接地
インダクタンスをＬ，バイアホール内面メタライズ層１
０とソースボンディングパッド７の間にある厚さのＧａ
Ａｓ層９が持つキャパシタンスの容量をＣ，半導体装置
の動作周波数をｆとすると、Here, the ground inductance formed by a bonding wire such as a gold wire for grounding the source bonding pad 7 is L, and the via hole inner surface metallization layer 1
Ga of the thickness between 0 and the source bonding pad 7
When the capacitance of the capacitance of the As layer 9 is C and the operating frequency of the semiconductor device is f,

【００２５】 [0025]

【００２６】の関係式が成立するような厚さのＧａＡｓ
層９を残すようにバイアホール８のエッチングを実施す
る。GaAs having a thickness such that the relational expression of
The via holes 8 are etched so that the layer 9 remains.

【００２７】[0027]

【発明の効果】以上説明したように本発明は、ボンディ
ングワイヤまたはバイアホール内面メタライズ層が持つ
接地インダクタンスをそのインダクタンス成分に対し直
列接続の形でキャパシタンスを形成し、そのキャパシタ
ンスが持つ容量の値を半導体装置が動作周波数でインダ
クタンスと直列共振するように設定することにより、実
効的に半導体装置の動作周波数にて接地のインダクタン
ス成分が殆ど零の状態になり、高周波動作における電力
利得の向上に大いに寄与する効果がある。As described above, according to the present invention, the grounding inductance of the bonding wire or via hole inner surface metallized layer is connected in series to the inductance component to form a capacitance, and the capacitance value of the capacitance is calculated. By setting the semiconductor device so that it resonates in series with the inductance at the operating frequency, the ground inductance component is effectively zero at the operating frequency of the semiconductor device, greatly contributing to the improvement of the power gain in high-frequency operation. Has the effect of

【００２８】この利点は、動作周波数が高ければ高いほ
ど顕著となる。This advantage becomes more remarkable as the operating frequency is higher.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の平面図である。FIG. 1 is a plan view of a first embodiment of the present invention.

【図２】本発明の第２の実施例のバイアホール部の部分
拡大断面図である。FIG. 2 is a partially enlarged sectional view of a via hole portion according to a second embodiment of the present invention.

【図３】従来の電界効果トランジスタチップを有する半
導体装置の一例の平面図である。FIG. 3 is a plan view of an example of a semiconductor device having a conventional field effect transistor chip.

【符号の説明】[Explanation of symbols]

１ パッケージ ２ フランジ ３ 電界効果トランジスタチップ ４ チップキャパシタ ５，７ ソースボンディングパッド ６ ボンディングワイヤ ８ バイアホール ９ ＧａＡｓ層 １０ バイアホール内面メタライズ層 1 Package 2 Flange 3 Field Effect Transistor Chip 4 Chip Capacitor 5,7 Source Bonding Pad 6 Bonding Wire 8 Via Hole 9 GaAs Layer 10 Via Hole Inner Metallization Layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ソースと該ソースに接続するソースボン
ディングパッドとを備えた電界効果トランジスタチップ
と、該電界効果トランジスタチップの前記ソースボンデ
ィングパッドに金線を含むボンディングワイヤを介して
接続するチップキャパシタとを同一パッケージ内に装着
した半導体装置において、前記ボンディングワイヤにて
形成される接地インダクタンスをＬ，前記チップキャパ
シタが持つ容量をＣ，動作周波数をｆとしたときに、 の関係式が成立することを特徴とする半導体装置。1. A field effect transistor chip including a source and a source bonding pad connected to the source, and a chip capacitor connected to the source bonding pad of the field effect transistor chip via a bonding wire including a gold wire. In a semiconductor device in which is mounted in the same package, when the ground inductance formed by the bonding wire is L, the capacitance of the chip capacitor is C, and the operating frequency is f, A semiconductor device characterized in that the relational expression is satisfied. 【請求項２】 ソースと該ソースに接続するソースボン
ディングパッドと該ソースボンディングパッドを接地面
に電気的に接続する金線を含むボンディングワイヤと前
記ソースボンディングパッドの裏面に形成された有底の
非貫通バイアホールと該バイアホールの内面全面に形成
されたメタライズ層とを備えた電界効果トランジスタチ
ップをパッケージ内に装着した半導体装置において、前
記ボンディングワイヤにて形成される接地インダクタン
スをＬ，前記バイアホール底部の前記メタライズ層と前
記ソースボンディングパッド間に形成されるキャパシタ
の容量をＣ，動作周波数をｆとしたときに、 の関係式が成立することを特徴とする半導体装置。2. A source, a source bonding pad connected to the source, a bonding wire including a gold wire electrically connecting the source bonding pad to a ground plane, and a bottomed non-contact formed on the back surface of the source bonding pad. In a semiconductor device in which a field effect transistor chip having a through via hole and a metallization layer formed on the entire inner surface of the via hole is mounted in a package, a grounding inductance formed by the bonding wire is L, and the via hole is When the capacitance of the capacitor formed between the bottom metallization layer and the source bonding pad is C and the operating frequency is f, A semiconductor device characterized in that the relational expression is satisfied.
JP4136441A 1992-05-28 1992-05-28 Semiconductor device Withdrawn JPH0697203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4136441A JPH0697203A (en) 1992-05-28 1992-05-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4136441A JPH0697203A (en) 1992-05-28 1992-05-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0697203A true JPH0697203A (en) 1994-04-08

Family

ID=15175196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4136441A Withdrawn JPH0697203A (en) 1992-05-28 1992-05-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697203A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063246A3 (en) * 2002-01-24 2004-03-11 Koninkl Philips Electronics Nv Rf amplifier
JP2010226606A (en) * 2009-03-25 2010-10-07 Denso Corp Load control apparatus, and capacitor impedance adjustment method
JP2011103399A (en) * 2009-11-11 2011-05-26 Canon Inc Semiconductor device
JP2017531914A (en) * 2014-09-23 2017-10-26 ホアウェイ・テクノロジーズ・カンパニー・リミテッド Radio frequency power component and radio frequency signal transmitting and receiving device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063246A3 (en) * 2002-01-24 2004-03-11 Koninkl Philips Electronics Nv Rf amplifier
JP2010226606A (en) * 2009-03-25 2010-10-07 Denso Corp Load control apparatus, and capacitor impedance adjustment method
JP2011103399A (en) * 2009-11-11 2011-05-26 Canon Inc Semiconductor device
JP2017531914A (en) * 2014-09-23 2017-10-26 ホアウェイ・テクノロジーズ・カンパニー・リミテッド Radio frequency power component and radio frequency signal transmitting and receiving device

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