JPS6190454A - High-frequency ground structure of semiconductor chip - Google Patents

High-frequency ground structure of semiconductor chip

Info

Publication number
JPS6190454A
JPS6190454A JP59213218A JP21321884A JPS6190454A JP S6190454 A JPS6190454 A JP S6190454A JP 59213218 A JP59213218 A JP 59213218A JP 21321884 A JP21321884 A JP 21321884A JP S6190454 A JPS6190454 A JP S6190454A
Authority
JP
Japan
Prior art keywords
capacitor
semiconductor chip
electrode
grounded
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59213218A
Other languages
Japanese (ja)
Inventor
Seizo Akasaka
赤坂　清三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59213218A priority Critical patent/JPS6190454A/en
Publication of JPS6190454A publication Critical patent/JPS6190454A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H01L2223/665—Bias feed arrangements
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

PURPOSE:To enable the minimization of the inductance of a ground capacitance including the connection length, by a method wherein the titled structure has a ground capacitor, one electrode surface of which has been grounded, and the other electrode surface of this capacitor is directly coated with the grounded surface of a semiconductor chip. CONSTITUTION:The ground capacitor 1 is joined by adhesion onto a ground conductor 3 with a piece of alloy solder of Au-Ge or Au-Sn or with a conductive adhesive material. Similarly, a semiconductor chip 2 is joined by adhesion to the upper surface of the capacitor 1, and the grounded electrode surface of this semiconductor chip 2 is joined by coating the upper electrode of the capacitor 1. In this case, the electrode surface of the capacitor 1 should be larger than the grounded surface of the chip 2, and the upper electrode of this capacitor should serve as the DC bias supply electrode for the chip 2. Direct coat of the ground capacitor electrode with a semiconductor chip enables substantially high-frequency ground with the lowest inductance.

Description

【発明の詳細な説明】 炎地且１ 本発明は半聯体チップの高周波接地構造に関し、特に安
定な動作が要求される高周波回路である例えばマイクロ
波増幅装置等のための半導体チップの高周波接地構造に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-frequency grounding structure for a semi-articulated chip, and in particular to a high-frequency grounding structure for a semiconductor chip for a high-frequency circuit that requires stable operation, such as a microwave amplification device. Regarding structure.

」１且Ｉ 特に１０ＧＨ２以上の周波数帯のマイクロ波増幅装置を
構成するに際して、この増幅装置を構成する半導体チッ
プの被接地面を接地する必要が生じるが、かかる場合、
接地インダクタンスが極力小さい高周波バイパス方法が
要求される。従来、小型で低インダクタンスのいわゆる
超高周波用のコンデンサがこの高周波バイパス用として
使用されているが、このコンデンサと半導体チップとの
接続長さが、両者の構成や形状等に起因する制約により
短くすることができず、よって当該接続長さを含むコン
デンサのインダクタンスを小さくすることが不可能とな
っている。1 and I In particular, when constructing a microwave amplification device for a frequency band of 10GH2 or higher, it is necessary to ground the grounded surface of the semiconductor chip that constitutes this amplification device.
A high-frequency bypass method with as low grounding inductance as possible is required. Conventionally, small, low-inductance capacitors for so-called ultra-high frequencies have been used for this high-frequency bypass, but the connection length between this capacitor and the semiconductor chip has to be shortened due to restrictions due to the configuration and shape of both. Therefore, it is impossible to reduce the inductance of the capacitor including the connection length.

１亘立旦刀 本発明は接続長さを含む接地用コンデンサのインダクタ
ンスを最小とし得る半導体チップの高周波接地構造を提
供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency grounding structure for a semiconductor chip that can minimize the inductance of a grounding capacitor including the connection length.

発明の構成 本発明による半導体チップの高周波接地ｖ４造は、一方
の電極面が接地された接地用コンデンサを有し、このコ
ンデンサの他方の’Ｗ＋４面上に半導体チップの被接地
面を直接被着してなることを特徴とする。Structure of the Invention The high-frequency grounding V4 structure for a semiconductor chip according to the present invention has a grounding capacitor with one electrode surface grounded, and the grounded surface of the semiconductor chip is directly adhered to the other 'W+4 surface of this capacitor. It is characterized by:

好ましくは、半導体チップの被接地面を直接被着するコ
ンデンサの電極を当該半導体チップの被接地面よりも大
きい面積としてこの電極を介して半導体チップの直流バ
イアスを供給可能とするのが良い。Preferably, the electrode of the capacitor that is directly attached to the grounded surface of the semiconductor chip has a larger area than the grounded surface of the semiconductor chip, so that a DC bias can be supplied to the semiconductor chip through this electrode.

実流例 以下、図面を用いて本発明の詳細な説明する。Actual flow example Hereinafter, the present invention will be explained in detail using the drawings.

第１図及び第２図は本発明の実施例の平面図及び側面図
であり、接地用のコンデンサ１が接地導体３の上に、金
−ゲルマニュウムや金−錫等の合金ろう材片または導電
性の接着剤を用いて接む接合されている。このコンデン
サ１の上面には半導体チップ２が被着されており、この
半導体チップ２の被接地電極面がコンデンサ１の上面電
極に上記と同様の方法で被着接合されている。1 and 2 are a plan view and a side view of an embodiment of the present invention, in which a grounding capacitor 1 is placed on a grounding conductor 3 using a piece of alloy brazing material such as gold-germanium or gold-tin or a conductive material. They are joined together using a sterile adhesive. A semiconductor chip 2 is attached to the upper surface of the capacitor 1, and the grounded electrode surface of the semiconductor chip 2 is bonded to the upper surface electrode of the capacitor 1 in the same manner as described above.

この場合、コンデンサ１の電極面は半々体チ・ンブ２の
被接地面よりも大きい面積を有しており、このコンデン
サの上面電極は半導体チップ２の直流バイアス供給電極
をも兼ね備えたものとなっている。そして、通常のワイ
ヤボンディング手段により入力回路部４．出力回路部５
及び直流バイアス回路部６とが夫々接続され、また必要
に応じて半導体チップ２とコンデンサ１とが同様なワイ
ヤボンディングにより接続されることによって、半導体
チップの電気的動作が可能となる。In this case, the electrode surface of the capacitor 1 has a larger area than the grounded surface of the half-chip 2, and the upper surface electrode of this capacitor also serves as the DC bias supply electrode for the semiconductor chip 2. ing. Then, the input circuit section 4. is connected by ordinary wire bonding means. Output circuit section 5
and the DC bias circuit section 6, and if necessary, the semiconductor chip 2 and the capacitor 1 are connected by similar wire bonding, thereby enabling the semiconductor chip to operate electrically.

第３図は第１．２図の実施例の等価回路の一例を示すも
のであり、半導体チップとして電界効果トランジスタ２
が使用されている。このトランジスタ２は、゛半導体で
あるガリウム砒素により構成したものであり、そのソー
ス電極（Ｓ）が高周波接地されるべくコンデンサ１を介
してアースされていると共に直流バイアス供給端子６が
このコンデンサ１の電極から導出されている。Fig. 3 shows an example of an equivalent circuit of the embodiment shown in Fig. 1.2, in which a field effect transistor 2 is used as a semiconductor chip.
is used. This transistor 2 is made of gallium arsenide, which is a semiconductor, and its source electrode (S) is grounded via the capacitor 1 for high frequency grounding, and the DC bias supply terminal 6 is connected to the capacitor 1. It is derived from the electrode.

コンデンサ１の静電容量は動作周波数により決定される
が、１０ＧＨｚ以上の場合１０ｐＦ以上の静電言回を有
するコンデンサが望ましい。第４図は接地用コンデンサ
１の斜視図であり、酸化チタンまたはチタン酸バリウム
系セラミック１０を約０．１ｍｍ程度の厚さとしその両
面に導電材１１゜１２によってメタライズすることによ
り容易に１昇られる。このコンデンサ１は低抵抗シリコ
ンウェハーの片面にシリコン酸化膜と窒化膜とを形成し
て、前述と同様Ｃにメタライズをなすことによっても容
易に得ることができる。The capacitance of the capacitor 1 is determined by the operating frequency, but if the frequency is 10 GHz or higher, a capacitor having a capacitance of 10 pF or higher is desirable. FIG. 4 is a perspective view of the grounding capacitor 1, which can be easily raised by making titanium oxide or barium titanate ceramic 10 about 0.1 mm thick and metallizing both sides with conductive material 11 and 12. . This capacitor 1 can also be easily obtained by forming a silicon oxide film and a nitride film on one side of a low-resistance silicon wafer, and metallizing the film as described above.

上記においては、半導体チップ２として電界効果トラン
ジスタの例を示したが、半導体チップの裏面に電極の一
部を有する例えばバイポーラトランジスタチップやダイ
オードチップ等をも使用可能であることは明白である。In the above, a field effect transistor is shown as an example of the semiconductor chip 2, but it is clear that a bipolar transistor chip, a diode chip, etc., which have a part of an electrode on the back surface of the semiconductor chip, can also be used.

発明の効果 本発明によれば、半導体チップを接地用コンデンサの電
極に直接に被着することによって、実質的な高周波接地
を最も低インダクタンスをもって可能となり１、特に、
コンデンサの電極を半導体チップの被接地電極よりも大
きな面積構造とすることにより、コンデンサの電極の一
部から半導体チップの直流バイアスをも供給することが
可能となる。これにより、マイクロ波のみならずミリ波
及びサブミリ波帯における半導体チップの実装において
困難であった接地用ワイヤボンディング等のインダクタ
ンスを最小とすることができ、超高周波能動素子を含む
回路特に増幅回路の低インダクタンス接地が可能となる
。Effects of the Invention According to the present invention, by directly attaching a semiconductor chip to the electrode of a grounding capacitor, substantial high-frequency grounding can be achieved with the lowest inductance.
By making the electrode of the capacitor have a larger area than the grounded electrode of the semiconductor chip, it becomes possible to also supply DC bias to the semiconductor chip from a part of the electrode of the capacitor. This makes it possible to minimize the inductance of grounding wire bonding, etc., which is difficult when mounting semiconductor chips not only for microwaves but also for millimeter and submillimeter waves. Low inductance grounding is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は本発明の実施例の平面図及び側面図
、第３図は第１．２図の装置の等価回路の例を示す図、
第４図は接地用コンデンサの斜視図である。。 主要部分の符号の説明1 and 2 are a plan view and a side view of an embodiment of the present invention, and FIG. 3 is a diagram showing an example of an equivalent circuit of the device shown in FIGS. 1 and 2.
FIG. 4 is a perspective view of the grounding capacitor. . Explanation of symbols of main parts

Claims (2)

【特許請求の範囲】[Claims] （１）一方の電極面が接地された接地用コンデンサを有
し、このコンデンサの他方の電極面上に半導体チップの
被接地面を直接被着してなることを特徴とする半導体チ
ップの高周波接地構造。(1) High-frequency grounding of a semiconductor chip characterized by having a grounding capacitor with one electrode surface grounded, and the grounded surface of the semiconductor chip being directly adhered to the other electrode surface of the capacitor. structure. （２）前記コンデンサの他方の電極面は前記半導体チッ
プの被接地面よりも大なる面積を有し、前記他方の電極
を介して前記半導体チップへの直流バイアスを印加自在
としてなることを特徴とする特許請求の範囲第１項の半
導体チップの高周波接地構造。(2) The other electrode surface of the capacitor has a larger area than the grounded surface of the semiconductor chip, and a DC bias can be freely applied to the semiconductor chip via the other electrode. A high frequency grounding structure for a semiconductor chip according to claim 1.
JP59213218A 1984-10-11 1984-10-11 High-frequency ground structure of semiconductor chip Pending JPS6190454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59213218A JPS6190454A (en) 1984-10-11 1984-10-11 High-frequency ground structure of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59213218A JPS6190454A (en) 1984-10-11 1984-10-11 High-frequency ground structure of semiconductor chip

Publications (1)

Publication Number Publication Date
JPS6190454A true JPS6190454A (en) 1986-05-08

Family

ID=16635485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59213218A Pending JPS6190454A (en) 1984-10-11 1984-10-11 High-frequency ground structure of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS6190454A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063246A3 (en) * 2002-01-24 2004-03-11 Koninkl Philips Electronics Nv Rf amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063246A3 (en) * 2002-01-24 2004-03-11 Koninkl Philips Electronics Nv Rf amplifier

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