JPH04320041A - Thick film hybrid integrated circuit - Google Patents
Thick film hybrid integrated circuitInfo
- Publication number
- JPH04320041A JPH04320041A JP3116899A JP11689991A JPH04320041A JP H04320041 A JPH04320041 A JP H04320041A JP 3116899 A JP3116899 A JP 3116899A JP 11689991 A JP11689991 A JP 11689991A JP H04320041 A JPH04320041 A JP H04320041A
- Authority
- JP
- Japan
- Prior art keywords
- grounding
- hole
- grounding conductor
- conductor film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000005219 brazing Methods 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、厚膜混成集積回路に
関し、特に半導体素子とグランド間のインダクタンス成
分とキャパシタンス成分を低減できる厚膜混成集積回路
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film hybrid integrated circuit, and more particularly to a thick film hybrid integrated circuit capable of reducing inductance and capacitance components between a semiconductor element and ground.
【０００２】0002
【従来の技術】図４は、従来の厚膜混成集積回路の斜視
図を示し、図５は図４における図中Ｖ−Ｖ線における断
面図である。2. Description of the Related Art FIG. 4 shows a perspective view of a conventional thick film hybrid integrated circuit, and FIG. 5 is a sectional view taken along line V--V in FIG. 4.
【０００３】図において、アルミナ基板等からなる絶縁
性基板１の表裏の両面にはメタライズされた導体膜であ
る入力用導体膜２，出力用導体膜３，接地用導体膜４が
それぞれ形成されている。そして、出力用導体膜３の上
面にはろう付けにより固着したＮＰＮ型バイポーラトラ
ンジスタからなる半導体素子５が設けられ、半導体素子
５に備えられた入力用ボンディングパッド５ａと接地用
ボンディングパッド５ｂは金線等からなるワイヤ６ａ，
６ｂによりそれぞれ入力用導体膜２と前記接地用導体膜
４に接続されている。そして、図５に示すように接地用
導体膜４は絶縁性基板１を貫通し形成されたスルーホー
ル７の内面を通して基板表面から裏面へ連続して形成さ
れている。また、スルーホール７に形成された接地用導
体膜４の表面はスルーホール７の角のハンダくわれを防
止するためにガラスコート８が施されている。一方、絶
縁性基板１の表面には図示しないバイアス回路，整合回
路が形成され、絶縁性基板１の裏面には図示しない放熱
効果を高めるための放熱板が形成されている。In the figure, an input conductor film 2, an output conductor film 3, and a ground conductor film 4, which are metallized conductor films, are respectively formed on the front and back surfaces of an insulating substrate 1 made of an alumina substrate or the like. There is. A semiconductor element 5 consisting of an NPN bipolar transistor fixed by brazing is provided on the upper surface of the output conductor film 3, and an input bonding pad 5a and a grounding bonding pad 5b provided on the semiconductor element 5 are made of gold wire. Wire 6a, etc.
6b are connected to the input conductor film 2 and the ground conductor film 4, respectively. As shown in FIG. 5, the grounding conductor film 4 is formed continuously from the front surface to the back surface of the substrate through the inner surface of a through hole 7 formed through the insulating substrate 1. Further, the surface of the grounding conductive film 4 formed in the through hole 7 is coated with a glass coat 8 to prevent solder cracking at the corners of the through hole 7. On the other hand, a bias circuit and a matching circuit (not shown) are formed on the front surface of the insulating substrate 1, and a heat sink (not shown) for enhancing the heat radiation effect is formed on the back surface of the insulating substrate 1.
【０００４】次に、動作について説明する。上記のよう
に構成された厚膜混成集積回路において、半導体素子５
の接地は半導体素子５に備えられた接地用ボンディング
パッド５ｂから該接地用ボンディングパッド５ｂに接続
されたワイヤ６ｂを通じ、該ワイヤ６ｂに接続された絶
縁性基板１の表面の接地用導体膜４からスルーホール７
の内面を通して絶縁性基板１の裏面へ敷設された接地用
導体膜４へ通じて行われる。Next, the operation will be explained. In the thick film hybrid integrated circuit configured as described above, the semiconductor element 5
The grounding is from a grounding bonding pad 5b provided on the semiconductor element 5 through a wire 6b connected to the grounding bonding pad 5b, and from the grounding conductor film 4 on the surface of the insulating substrate 1 connected to the wire 6b. Through hole 7
The conductor film 4 for grounding is laid on the back surface of the insulating substrate 1 through the inner surface of the insulating substrate 1.
【０００５】また、近年、無線通信装置の電力増幅部を
上記のようなハイブリッド型の集積回路としたものが多
く提供され、これらはより小型化する傾向にある。[0005] Furthermore, in recent years, many wireless communication devices in which the power amplification section is made of the above-mentioned hybrid type integrated circuit have been provided, and there is a tendency for these devices to become smaller.
【０００６】[0006]
【発明が解決しようとする課題】従来の厚膜混成集積回
路は以上のように構成されており、半導体素子５の接地
は半導体素子５に備えられた接地用ボンディングパッド
５ｂからワイヤ６ｂ、ワイヤ６ｂから絶縁性基板１の表
面からスルーホールの内面を通って裏面へつながる接地
用導体膜４を通して行われるので、半導体素子５からグ
ランドまでの導通路が長く、この間のインダクタンス成
分とキャパシタンス成分が大きく高周波特性に悪影響を
与える問題点があった。The conventional thick film hybrid integrated circuit is constructed as described above, and the semiconductor element 5 is grounded from the grounding bonding pad 5b provided on the semiconductor element 5 to the wire 6b and the wire 6b. Since the grounding conductor film 4 is connected from the front surface of the insulating substrate 1 to the back surface through the inner surface of the through-hole, the conduction path from the semiconductor element 5 to the ground is long, and the inductance and capacitance components during this period are large and high frequency There were problems that adversely affected the characteristics.
【０００７】また、上記の従来の厚膜混成集積回路は、
絶縁性基板１の表面の接地用導体膜の占める割合が大き
く、装置を充分に小型化することができないという問題
点があった。[0007] Furthermore, the above conventional thick film hybrid integrated circuit has the following characteristics:
There was a problem in that the proportion of the grounding conductor film on the surface of the insulating substrate 1 was large, making it impossible to sufficiently miniaturize the device.
【０００８】この発明は上記のような問題点を解消する
ためになされたもので、高周波特性を改善するとともに
、装置を小型化できる厚膜混成集積回路を得ることを目
的とする。The present invention has been made to solve the above-mentioned problems, and aims to provide a thick film hybrid integrated circuit which can improve high frequency characteristics and make the device smaller.
【０００９】[0009]
【課題を解決するための手段】この発明にかかる厚膜混
成集積回路は、絶縁性基板の第１の主面上に敷設された
出力用導体膜上の半導体素子の近傍に該絶縁性基板の第
１の主面と第２の主面を貫通するスルーホールを形成す
るとともに、該スルーホールを通して前記絶縁性基板の
第１の主面と第２の主面が導通するように接地用導体膜
を形成し、更に、前記スルーホールの周辺に形成された
接地用導体膜の一部に接続され前記スルーホールを覆う
ように配設した接地用導体板を設け、該接地用導体板と
前記半導体素子とをワイヤにより接続したものである。[Means for Solving the Problems] A thick film hybrid integrated circuit according to the present invention has a structure in which an insulating substrate is placed near a semiconductor element on an output conductor film laid on a first main surface of the insulating substrate. A grounding conductor film is formed to form a through hole penetrating the first main surface and the second main surface, and to connect the first main surface and the second main surface of the insulating substrate through the through hole. further provided is a grounding conductor plate connected to a part of the grounding conductor film formed around the through hole and disposed so as to cover the through hole, and the grounding conductor plate and the semiconductor The elements are connected by wires.
【００１０】0010
【作用】この発明の厚膜混成集積回路においては、出力
用導体膜上に設けられた半導体素子の接地用導体基板を
接続するワイヤが短くなり、更に、絶縁性基板の表面と
裏面との導通をとる接地用導体膜が短くなるため、半導
体素子の接地を行うための導通路のインダクタンス成分
とキャパシタンス成分が低減でき、また、前記絶縁性基
板表面を占める接地用導体膜の面積を小さくできる。[Function] In the thick film hybrid integrated circuit of the present invention, the wire connecting the grounding conductor substrate of the semiconductor element provided on the output conductor film is shortened, and furthermore, the conduction between the front and back surfaces of the insulating substrate is shortened. Since the grounding conductor film becomes shorter, the inductance component and capacitance component of the conductive path for grounding the semiconductor element can be reduced, and the area of the grounding conductor film occupying the surface of the insulating substrate can be reduced.
【００１１】[0011]
【実施例】以下、この発明の一実施例を図について説明
する。図１はこの発明の一実施例による厚膜混成集積回
路の一部分を示す斜視図であり、図２は図１中のＩＩ−
ＩＩ線における断面の斜視図である。尚、図１及び図２
において図４及び図５と同符号は同一或いは相当する部
分を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing a part of a thick film hybrid integrated circuit according to an embodiment of the present invention, and FIG.
FIG. 2 is a perspective view of a cross section taken along line II. Furthermore, Figures 1 and 2
The same reference numerals as in FIGS. 4 and 5 indicate the same or corresponding parts.
【００１２】図において、アルミナ基板等からなる絶縁
性基板１上にメタライズされた導体膜からなる入力用導
体膜２，出力用導体膜３が形成され、該出力用導体膜３
の上面に、ＮＰＮ型バイポーラトランジスタからなる半
導体素子５がろう付けにて固着され、該半導体素子５に
備えられた入力用ボンディングパッド５ａは入力用導体
膜２と金線からなるワイヤ６ａにより接続される。また
、半導体素子５に備えられた接地用ボンディングパッド
５ｂは、図２に示すようにコの字状でスルーホール７の
周囲の接地用導体膜４上に凸部９ａを図中１０で示すよ
うにろう付けし、スルーホール７を覆うように取り付け
られた接地用導体板９とワイヤ６ｂにて接続されている
。スルーホール７は図２に示すように絶縁性基板１を貫
通して形成され、接地用導体膜４は絶縁性基板１の表裏
面が通じるように表面からスルーホール７の内面を通っ
て裏面へ連続して形成されている。また、前記スルーホ
ール７に形成されたの接地用導体膜４の表面にはスルー
ホール７の角のハンダくわれを防止するためにガラスコ
ート８が施されている。また、絶縁性基板１の表面には
図示しないバイアス回路，整合回路が形成され、絶縁性
基板１の裏面には図示しない放熱効果を高めるための放
熱板が形成されて厚膜混成集積回路が構成されている。In the figure, an input conductor film 2 and an output conductor film 3 made of metallized conductor films are formed on an insulating substrate 1 made of an alumina substrate or the like.
A semiconductor element 5 made of an NPN type bipolar transistor is fixed to the upper surface by brazing, and an input bonding pad 5a provided on the semiconductor element 5 is connected to the input conductor film 2 by a wire 6a made of a gold wire. Ru. The grounding bonding pad 5b provided on the semiconductor element 5 has a U-shape as shown in FIG. It is connected to a grounding conductor plate 9, which is attached to cover the through hole 7, by a wire 6b. The through hole 7 is formed to penetrate the insulating substrate 1 as shown in FIG. 2, and the grounding conductor film 4 is formed from the front surface to the back surface through the inner surface of the through hole 7 so that the front and back surfaces of the insulating substrate 1 are connected. formed continuously. Further, a glass coat 8 is applied to the surface of the grounding conductive film 4 formed in the through hole 7 to prevent solder cracking at the corners of the through hole 7. Further, a bias circuit and a matching circuit (not shown) are formed on the front surface of the insulating substrate 1, and a heat dissipation plate (not shown) for enhancing the heat dissipation effect is formed on the back surface of the insulating substrate 1, thereby forming a thick film hybrid integrated circuit. has been done.
【００１３】次に動作について説明する。半導体素子５
の接地は、半導体素子５に備えられた接地用ボンディン
グパッド５ｂから接地用ボンディングパッド５ｂに接続
されたワイヤ６ｂ、ワイヤ６ｂからワイヤ６ｂに接続さ
れた接地用導体板９、接地用導体板９から接地用導体板
９の凸部９ａと接続された絶縁性基板１の表面の接地用
導体膜４に通じ、絶縁性基板１の表面の接地用導体膜４
からスールホール７を介して絶縁性基板１裏面の接地用
導体膜４に通じ、接地される。Next, the operation will be explained. Semiconductor element 5
The grounding is performed by a wire 6b connected from a grounding bonding pad 5b provided on the semiconductor element 5 to the grounding bonding pad 5b, a grounding conductor plate 9 connected from the wire 6b to the wire 6b, and a grounding conductor plate 9 connected to the grounding conductor plate 9. The grounding conductor film 4 on the surface of the insulating substrate 1 is connected to the convex portion 9a of the grounding conductor plate 9 to the grounding conductor film 4 on the surface of the insulating substrate 1.
This is connected to the grounding conductor film 4 on the back surface of the insulating substrate 1 through the through hole 7, and is grounded.
【００１４】このような本実施例による厚膜混成集積回
路では、半導体素子５の近傍の入力用導体膜２と出力用
導体膜３との間にスルーホール７を形成し、該スルーホ
ール７を通して絶縁性基板１の表裏面に接地用導体膜４
を敷設し、該スールーホール７の上方に接地用ワイヤ６
ｂと接続する接地用導体板９を設け、該接地用導体板９
と接地用導体膜４とろう付けして接続したので、半導体
素子５の接地用ボンディングパッド５ｂと接地用導体板
９を接続する接地用ワイヤ６ｂの長さと接地用導体板９
から絶縁性基板１の裏面の接地用導体膜４への導通路が
共に短くなり、半導体素子５とグランド間のインダクタ
ンス成分とキャパシタンス成分を低減することができ、
また、絶縁性基板１表面を占める接地用導体膜の面積も
少なくなるので基板を小さくできる。In the thick film hybrid integrated circuit according to this embodiment, a through hole 7 is formed between the input conductor film 2 and the output conductor film 3 near the semiconductor element 5, and the through hole 7 is A grounding conductive film 4 is provided on the front and back surfaces of the insulating substrate 1.
A grounding wire 6 is laid above the through-hole 7.
A grounding conductor plate 9 connected to b is provided, and the grounding conductor plate 9
Since the grounding conductor film 4 and the grounding conductor film 4 are connected by brazing, the length of the grounding wire 6b connecting the grounding bonding pad 5b of the semiconductor element 5 and the grounding conductor plate 9 and the grounding conductor plate 9 are determined.
The conductive path from the insulating substrate 1 to the grounding conductor film 4 on the back surface of the insulating substrate 1 is shortened, and the inductance component and capacitance component between the semiconductor element 5 and the ground can be reduced.
Further, since the area of the grounding conductor film occupying the surface of the insulating substrate 1 is also reduced, the substrate can be made smaller.
【００１５】図３はこの発明の他の実施例による接地用
導体板の斜視図であり、図に示すように接地用導体板１
１はスルーホールに嵌め込むための棒状部１１ａを有し
ており、スルーホールに棒状部１１ａを嵌め込んでろう
付けして取り付けてもよい。FIG. 3 is a perspective view of a grounding conductor plate according to another embodiment of the present invention, and as shown in the figure, the grounding conductor plate 1
1 has a rod-shaped portion 11a to be fitted into a through-hole, and may be attached by fitting the rod-shaped portion 11a into the through-hole and brazing.
【００１６】[0016]
【発明の効果】以上のように、この発明の厚膜混成集積
回路によれば、半導体素子の近傍にスルーホールを形成
するとともに、スルーホールの周囲の接地用導体膜に一
部が接続し前記スルーホールを覆うように配設された接
地用導体板を設け、前記半導体素子と前記接地用導体板
とをワイヤにより接続したので、接地用の導通路のイン
ダクタンス成分とキャパシタンス成分が低減し、基板が
小型化できるため、高周波特性に優れた小型の厚膜混成
集積回路を得ることができる効果がある。As described above, according to the thick film hybrid integrated circuit of the present invention, a through hole is formed in the vicinity of a semiconductor element, and a part of the through hole is connected to a grounding conductor film around the through hole. Since a grounding conductor plate is provided to cover the through hole and the semiconductor element and the grounding conductor plate are connected by wire, the inductance component and capacitance component of the grounding conductive path are reduced, and the substrate Since the structure can be made smaller, it is possible to obtain a compact thick film hybrid integrated circuit with excellent high frequency characteristics.
【図１】本発明の一実施例による厚膜混成集積回路の斜
視図である。FIG. 1 is a perspective view of a thick film hybrid integrated circuit according to an embodiment of the present invention.
【図２】図１ＩＩ−ＩＩ線に沿った断面図である。FIG. 2 is a sectional view taken along the line II-II in FIG.
【図３】本発明の他の実施例による接地用導体板の斜視
図である。FIG. 3 is a perspective view of a grounding conductor plate according to another embodiment of the present invention.
【図４】従来の一実施例による厚膜混成集積回路の斜視
図である。FIG. 4 is a perspective view of a thick film hybrid integrated circuit according to a conventional embodiment.
【図５】図４Ｖ−Ｖ線に沿った断面図である。FIG. 5 is a sectional view taken along line V-V in FIG. 4;
１ 絶縁基板 ２ 入力用導体膜 ３ 出力用導体膜 ４ 接地用導体膜 ５ 半導体素子 ６ａ ワイヤ ６ｂ ワイヤ ７ スルーホール ９ 接地用導体板 １０ ろう付け部 １１ 接地用導体板 １１ａ 接地用導体板 1 Insulating substrate 2 Input conductor film 3 Output conductor film 4 Grounding conductor film 5 Semiconductor device 6a Wire 6b Wire 7 Through hole 9 Grounding conductor plate 10 Brazing part 11 Grounding conductor plate 11a Grounding conductor plate
Claims (1)
た出力用導体膜と該出力用導体膜上に設けられた半導体
素子と、前記絶縁性基板の第１の主面と第２の主面を貫
通するスルーホールを通して第１の主面と第２の主面が
導通するように敷設した接地用導体膜とを有する厚膜混
成集積回路において、前記半導体素子の近傍に形成され
たスルーホールと、前記スルーホールの周囲の接地用導
体膜に一部が接続し、前記スルーホールを覆うように配
設された接地用導体板と、前記半導体素子と前記接地用
導体板とを接続するワイヤと、を備えたことを特徴とす
る厚膜混成集積回路。1. An output conductor film laid on a first main surface of an insulating substrate, a semiconductor element provided on the output conductor film, and an output conductor film laid on a first main surface of the insulating substrate, In the thick film hybrid integrated circuit, the thick film hybrid integrated circuit has a grounding conductor film laid so that the first main surface and the second main surface are electrically connected through a through hole penetrating the main surface of the second main surface. a through hole, a grounding conductor plate that is partially connected to a grounding conductor film around the through hole and disposed to cover the through hole, and the semiconductor element and the grounding conductor plate. A thick film hybrid integrated circuit comprising: a connecting wire;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3116899A JPH04320041A (en) | 1991-04-18 | 1991-04-18 | Thick film hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3116899A JPH04320041A (en) | 1991-04-18 | 1991-04-18 | Thick film hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04320041A true JPH04320041A (en) | 1992-11-10 |
Family
ID=14698399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3116899A Pending JPH04320041A (en) | 1991-04-18 | 1991-04-18 | Thick film hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04320041A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012109547A (en) * | 2010-10-18 | 2012-06-07 | Kyocera Corp | Substrate for mounting light-emitting element and light-emitting device |
-
1991
- 1991-04-18 JP JP3116899A patent/JPH04320041A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012109547A (en) * | 2010-10-18 | 2012-06-07 | Kyocera Corp | Substrate for mounting light-emitting element and light-emitting device |
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