JPS60157240A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the performance of the titled device of high frequency and high output by increasing the series equivalent resistance viewed from a base terminal by a method wherein a MOS capacitor is connected in parallel with base bonding wires. CONSTITUTION:A transistor chip 1, the first MOS capacitor 2, and the base terminal 5 are provided; then, the above-mentioned transistor chip 1 is connected to the MOS capacitor 2, and this MOS capacitor 2 is connected to a base electrode 5 by means of the base bonding wires 3 and MOS capacitor bonding wires 4, respectively. Such a semiconductor device is provided with the second MOS capacitor 2 in parallel with said base bonding wires 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high frequency semiconductor device, and particularly to a high frequency, high power semiconductor device having an internal matching circuit.

[Prior art]

FIGS. 1(a) and 1(b) are a side view and a plan view showing the assembled structure of a general high-frequency, high-output transistor, in which 1 is a transistor chip, 2 is a first MOS capacitor for internal matching, and 3 is the above-mentioned a base bonding wire connecting the base electrode on the transistor chip 1 and the first MOS capacitor 2; 4 a MOS capacitor bonding wire connecting the first MOS capacitor 2 and the base terminal 5;
6 is an emitter bridge for connecting an emitter bonding wire T7 connecting the emitter electrode of the transistor chip 1 and the case. 8 is the collector terminal,
Reference numeral 9 denotes a transistor package, which is electrically connected to the emitter of the transistor.

FIG. 2 is an equivalent circuit diagram of FIG. 1, where 10 is the resistance of the transistor chip 1 due to the pace spreading resistance value of the transistor chip 1, and 11 is the pace bonding wire 3.
, 12 is the bias capacitance of the first MOS capacitor 2 for internal matching, 13 is the inductance due to the MOS capacitor bonding wire 4, and 14 is the inductance of the first MOS capacitor 2 for internal matching.
a&! This is the equivalent resistance seen from the pace terminal 5.

In Figure 2, the series equivalent resistance R seen from the base terminal 5
, (Ω) is r (Ω): Resistance Lb (H) of transistor chip 1:
Inductance C (F) of base bonding wire 3: Capacitance ω (rad/5ec) of MOS capacitor 2: 2πf In equation (1), when the circuit is in a resonant state, equation (2) shows that Series equivalent resistance R0 (Ω) is R, = x/Yb = r (ωLb)”/r(1+Q”
(Ω) -...-431. However, Q-ωLH/r ・・・・・・・・・・・・・・・−
・・・・・・・・・・・・(4) Here, Parts (3) and (4)
Estimated series resistance R, (Ω)y from the pace from the formula! - To make the circuit thicker, it is necessary to increase the Q of the circuit.If the resistance r(Ω) of the transistor chip 1 is constant, the Q of the circuit is high, so the busy state is ωLb(!2)y! However, due to the mechanical reliability of the semiconductor device and the size of the transistor package 9, the inductance Lb (H) due to the pace bonding wire 3 must be increased.
Y! l- There is a limit to being big. Therefore 1
When the frequency f(H,) becomes low, the Q' of the circuit becomes high (
Therefore, the series equivalent resistance R, (Ω) seen from the base terminal 5 cannot be increased.

[Summary of the invention]

This invention was devised to improve the above-mentioned drawbacks, and its purpose is to increase the effective inductance Lbe(H) w of the paceponding wire by connecting a capacitance in parallel to the paceponding wire. This is what I did.

[Embodiments of the invention]

The present invention will be explained below based on the drawings.

FIGS. 3(a) and 3(b) are a side view and a plan view of an assembled structure of a high-frequency, high-output transistor showing an embodiment of the present invention, and the same reference numerals as in FIGS. 1 and 2 refer to the same parts. show. In FIG. 3, 15 is a second MOS capacitor connected in parallel to the paceponding wire 3I/C, and 16 is a bond connecting the second MOS capacitor 15 and the transistor chip 1wm. / wire.

FIG. 4 is an equivalent circuit diagram of FIG. 3, and 17 is the capacitance of the second MOS capacitor 15 of the present invention, 14b
is the equivalent resistance seen from the base terminal 5.

In Figure 4, the parallel interference between Lb and C1 (
Ω) becomes . However, therefore, the effective inductance Lb due to the paceponding wire 3, (H) is r G) L,,
= r*L"〒kof/fo)・te, that is, Lb, =Lb/(1-(f/fo)2(H) ・・−・
---(6+. However, f < f o.

From formula 6, 4 of the circuit according to the present invention is Q'=Q/+f/f, )"]
・・・・・・・・・・・・・・・(7)

From equation (7), the operating frequency of the transistor f(H,)v
f = 0.8f, when closed Q' = Q / (1-0,8" l 22.78Q ・
...(8).

Therefore, even if the inductance Lb'Y due to the pace pounding wire 3 is not increased by 2.78 times, L,
Resonant frequency f with respect to Vc. It is clear that this can be realized by connecting capacitances CgttLb' in parallel such as -flo and S.

Depending on the values of T,−,Lb and C8, the effective value is, ,(H)
can be controlled. D, ie, QY can be controlled and R,yIl- can be controlled.

[Effects of the Invention] As explained above, in this generator 8A, since a capacitance is connected in parallel to the paceponding wire, the series equivalent resistance seen from the base terminal can be increased, and it is suitable for high frequency and high power semiconductor devices. This has the advantage of improving performance.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a side view and a plan view showing the main parts of the assembled structure of a general high-frequency, high-output transistor, and FIG.
The figure is an equivalent circuit diagram of Fig. 1, and Fig. 3 (a). (b) shows an assembled structure of a high-frequency, high-output transistor showing one embodiment of the present invention! FIG. 4 is an equivalent circuit diagram of FIG. 3. In the figure, 1 is a transistor chip, 2 is a first MOS capacitor, 3 is a base bonding wire, 4 is a MOS capacitor bonding wire, 5 is a base terminal, 6 is an emitter bridge, 7 is an emitter bonding wire, 8
10 is a collector terminal, 9 is a transistor package, 1o is a resistance, 11.13 is an inductance, 12 and 17 are capacitances, 14m and 14bn are equivalent resistances, 15 & 2 are second MOS capacitors, and 16 is a bonding wire. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 4 Procedure amendment (voluntary) 1. Description of the case Japanese Patent Application No. 59-013715 2 Title of the invention Semiconductor device 3 To the representative of the person making the amendment Katayuni Department ~\, 1 Office\ 5. Detailed description of the invention in the specification subject to the amendment Explanation column 6, Self-answer for correction (11 Correct equation (3) on page 3, line 15 of the specification as follows: rR, = l/lb = r (1 + Q)" (Ω month = - ---
-= (31 (2) Similarly, on page 5, lines 12-13, [parallel impedance (Ω) is] is corrected to "parallel impedance (Ω) is,"). Correct the equation (6) in row as follows: rLbe=Lb/(1(f/fo)J(H)J --(
61(4) Similarly, formula (7) on page 6, line 7 is corrected as follows. IQ'=Q/(x-(f/fo)21''...
−−・−m or more

Claims (1)

[Claims] A transistor chip and a first MOS capacitor. and a base terminal, and a base bonding wire and an M
A semiconductor device in which an OS capacitor is connected by a bonding wire, and a second MOS capacitor is provided in parallel with the pace bonding wire.