JPS63258053A - Fet bias circuit - Google Patents

Fet bias circuit

Info

Publication number
JPS63258053A
JPS63258053A JP62091032A JP9103287A JPS63258053A JP S63258053 A JPS63258053 A JP S63258053A JP 62091032 A JP62091032 A JP 62091032A JP 9103287 A JP9103287 A JP 9103287A JP S63258053 A JPS63258053 A JP S63258053A
Authority
JP
Japan
Prior art keywords
fet
capacitor
circuit
resistor
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62091032A
Other languages
Japanese (ja)
Inventor
Toshio Saikai
西海　敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62091032A priority Critical patent/JPS63258053A/en
Publication of JPS63258053A publication Critical patent/JPS63258053A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Amplifiers (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Waveguide Connection Structure (AREA)

Abstract

PURPOSE:To simplify a circuit structure as well as to prevent from being restricted by an output matching circuit pattern, by a method wherein the capacitor for bias and the resistor of a FET are integrally formed as a chip capacitor, and this chip capacitor is provided with wire connection to the FET in a state independent of an input circuit board and an output circuit board. CONSTITUTION:In a bias circuit of a FET amplifier, which is constituted of an input circuit board 10, an output circuit board 11 and a FET 1, and the like, a capacitor 3 for bias and a resistor 5 of the FET 1 are integrally formed as a chip capacitor 12 and this chip capacitor is provided with wire connection to the FET 1 in a state independent from then input circuit board 10 and the output circuit board 11. For example, a source of the FET 1 and the chip capacitor 12 are connected by a wire 13 to connect to the capacitor 3 and the connection of the source to the resistor 5 is executed by a pattern on the chip capacitor 12. Moreover, the wiring between the capacitor 3 and the other end of the resistor 5 and the ground is executed by a wire 14. Thereby, the connection of a parallel circuit consisting a circuit of the capacitor and the resistor is facilitated to simplify a circuit structure and the structure can be prevented from being restricted by an output matching circuit pattern.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路における電界効果トランジスタ（
ＦＥＴ）増幅回路のバイアス回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to field effect transistors (field effect transistors) in hybrid integrated circuits.
FET) relates to a bias circuit for an amplifier circuit.

〔従来の技術〕[Conventional technology]

従来の混成集積回路におけるＦＥＴバイアス回路、特に
単一電源で動作するＦＥＴバイアス回路の一例を第３図
に示し、第４図にその実装状態の平面図を示す。図にお
いて、ｌはＦＥＴ、２は電源端子、３は高周波のバスコ
ンデンサ、４はゲートバイアス用抵抗、５はソース抵抗
、６は入力端子、７は出力端子、８．９はコンデンサで
ある。FIG. 3 shows an example of a FET bias circuit in a conventional hybrid integrated circuit, particularly an FET bias circuit that operates with a single power supply, and FIG. 4 shows a plan view of its mounting state. In the figure, l is an FET, 2 is a power supply terminal, 3 is a high frequency bus capacitor, 4 is a gate bias resistor, 5 is a source resistor, 6 is an input terminal, 7 is an output terminal, and 8.9 is a capacitor.

また、この回路は、入力回路の誘電体基板１０及び出力
回路誘電体基板１１を用いて構成しである。Further, this circuit is constructed using a dielectric substrate 10 for an input circuit and a dielectric substrate 11 for an output circuit.

そして、ＦＥＴバイアス用としてソース・グランド間に
並列接続されているコンデンサ３と抵抗５は、コンデン
サ３が前記誘電体基板１０．１１間に配置され、抵抗５
が誘電体基板ｌｌ上に配置されている。A capacitor 3 and a resistor 5 are connected in parallel between the source and ground for FET bias, and the capacitor 3 is arranged between the dielectric substrates 10 and 11, and the resistor 5
is placed on the dielectric substrate ll.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のＦＥＴバイアス回路は、第４図に示すよ
うに、抵抗５とコンデンサ３は別々の基板に構成されて
いるため、これらでバイアス回路を構成するためにはコ
ンデンサ３及び誘電体基板１０．１１間での配線が必要
になり、回路構造が複雑になる。また、抵抗５のパター
ンは出力回路誘電体基板１１上に形成されているため、
ＦＥＴの出力整合回路パターンの制約を受けるという問
題がある。In the conventional FET bias circuit described above, as shown in FIG. 4, the resistor 5 and capacitor 3 are configured on separate substrates. .11 is required, making the circuit structure complicated. Furthermore, since the pattern of the resistor 5 is formed on the output circuit dielectric substrate 11,
There is a problem in that it is limited by the output matching circuit pattern of the FET.

本発明は回路構造を簡易化するとともに出力整合回路パ
ターンの制約を受けることのないＦＥＴバイアス回路を
提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a FET bias circuit that has a simplified circuit structure and is not subject to restrictions of output matching circuit patterns.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のＦＥＴバイアス回路は、入力回路基板。 The FET bias circuit of the present invention is an input circuit board.

出力回路基板及びＦＥＴで構成したＦＥＴ増幅器等のバ
イアス回路において、ＦＥＴのバイアス用コンデンサ及
び抵抗をチップコンデンサとして一体形成し、これを入
力回路基板及び出力回路基板とは独立した状態でＦＥＴ
にワイヤ接続した構成としている。In a bias circuit such as an FET amplifier configured with an output circuit board and a FET, the bias capacitor and resistor of the FET are integrally formed as a chip capacitor, and this is connected to the FET in a state independent from the input circuit board and the output circuit board.
The configuration is such that the wires are connected to the

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の回路図、第２図はその実装
状態の平面図を示しており、前記従来例と同一部分には
同一符号を附している。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a plan view of its mounting state, and the same parts as in the conventional example are given the same reference numerals.

第１図において、ｌはＦＥＴ、２は電源端子、３はコン
デンサ、４はゲート抵抗、５はソース抵抗、６は入力端
子、７は出力端子、８．９はコンデンサである。このバ
イアス回路は、第２図のように、ＦＥＴＩ、入力回路誘
電体基板１０．出力回路誘電体基板１１及びチップコン
デンサ１２を用いて実装しである。In FIG. 1, l is an FET, 2 is a power supply terminal, 3 is a capacitor, 4 is a gate resistor, 5 is a source resistor, 6 is an input terminal, 7 is an output terminal, and 8.9 is a capacitor. As shown in FIG. 2, this bias circuit includes an FETI, an input circuit dielectric substrate 10. The output circuit is mounted using a dielectric substrate 11 and a chip capacitor 12.

このチップコンデンサ１２は前記コンデンサ３を構成し
、かつその一部には抵抗５を構成しである。そして、Ｆ
ＥＴＩのバイアス用としてのコンデンサ３と抵抗５の接
続に際しては、ＦＥＴＩのソースとチップコンデンサ１
２とをワイヤ１３で接続してコンデンサ３に接続する。This chip capacitor 12 constitutes the capacitor 3, and a portion thereof constitutes the resistor 5. And F
When connecting capacitor 3 and resistor 5 for ETI bias, connect the source of FETI and chip capacitor 1.
2 is connected to the capacitor 3 by a wire 13.

また抵抗５への接続はチップコンデンサ１２上のパター
ンで行われる。更にコンデンサ３及び抵抗５の他端から
グランド間への配線はワイヤ１４にて行なっている。Further, connection to the resistor 5 is made through a pattern on the chip capacitor 12. Further, wiring from the other ends of the capacitor 3 and the resistor 5 to the ground is performed by a wire 14.

したがってこの構成によれば、ＦＥＴＩのソースからグ
ランド間に接続されるコンデンサ３と抵抗５の並列回路
が１つのチップコンデンサ１２で構成されるため、配線
用としてのワイヤ数は従来構造に比較して低減できる。Therefore, according to this configuration, the parallel circuit of the capacitor 3 and the resistor 5 connected between the source of the FETI and the ground is composed of one chip capacitor 12, so the number of wiring wires is smaller than that of the conventional structure. Can be reduced.

また、抵抗５を出力回路誘電体基板１１に形成していな
いため、出力整合回路のパターンが制約されることもな
い。Furthermore, since the resistor 5 is not formed on the output circuit dielectric substrate 11, the pattern of the output matching circuit is not restricted.

ここで、本発明は第１図に示した回路以外のバイアス回
路においても、ＦＥＴに抵抗とコンデンサを並列接続す
るバイアス回路に同様に適用できることはいうまでもな
い。It goes without saying that the present invention is equally applicable to bias circuits other than the circuit shown in FIG. 1, in which a resistor and a capacitor are connected in parallel to an FET.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＦＥＴのバイアス用コン
デンサ及び抵抗をチップコンデンサとして一体形成し、
これを入力回路基板及び出力回路基板とは独立した状態
でＦＥＴにワイヤ接続してバイアス回路を構成している
ので、これらコンデンサ及び抵抗の並列回路の接続を容
易にして構造の簡易化を図ることができ、かつ出力整合
回路パターンの制約を受けなくなるという効果がある。As explained above, the present invention integrally forms the FET bias capacitor and resistor as a chip capacitor,
Since this is connected to the FET by wire independently from the input circuit board and the output circuit board to form a bias circuit, it is easy to connect the parallel circuit of these capacitors and resistors to simplify the structure. This has the effect of not being restricted by the output matching circuit pattern.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の回路図、第２図は第１図の
実施例の実装平面図、第３図は従来のＦＥＴバイアス回
路の回路図、第４図は第３図の回路の実装平面図である
。 ｌ・・・ＦＥＴ、２・・・電源端子、３・・・コンデン
サ、４・・・ゲート抵抗、５・・・ソース抵抗、６・・
・入力端子、７・・・ゲート抵抗、８．９・・・コンデ
ンサ、ＩＯ・・・入力回路誘電体基板、１１・・・出力
回路誘電体基板、１２・・・チップコンデンサ、１３．
１４・・・ワイヤ。 第１図 第２図 １０効■路艶倉不級１１已１回冶履舊籾第３図 ？ 第４図Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a mounting plan view of the embodiment of Fig. 1, Fig. 3 is a circuit diagram of a conventional FET bias circuit, and Fig. 4 is a circuit diagram of the embodiment of Fig. 3. FIG. 3 is a plan view of the circuit implementation. 1...FET, 2...Power supply terminal, 3...Capacitor, 4...Gate resistance, 5...Source resistance, 6...
- Input terminal, 7... Gate resistor, 8.9... Capacitor, IO... Input circuit dielectric substrate, 11... Output circuit dielectric substrate, 12... Chip capacitor, 13.
14...Wire. Fig. 1 Fig. 2 10 effects■Roo Yan Cang Ungrade 11 已1 time Jyori 舊芊Fig. 3? Figure 4

Claims (1)

【特許請求の範囲】[Claims] （１）入力回路基板、出力回路基板及びＦＥＴで構成し
たＦＥＴ増幅器等のバイアス回路において、前記ＦＥＴ
のバイアス用コンデンサ及び抵抗をチップコンデンサと
して一体形成し、これを前記入力回路基板及び出力回路
基板とは独立した状態で前記ＦＥＴにワイヤ接続したこ
とを特徴とするＦＥＴバイアス回路。(1) In a bias circuit such as an FET amplifier configured with an input circuit board, an output circuit board, and an FET, the FET
An FET bias circuit characterized in that a bias capacitor and a resistor are integrally formed as a chip capacitor, and this is connected to the FET by wire independently of the input circuit board and the output circuit board.
JP62091032A 1987-04-15 1987-04-15 Fet bias circuit Pending JPS63258053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62091032A JPS63258053A (en) 1987-04-15 1987-04-15 Fet bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62091032A JPS63258053A (en) 1987-04-15 1987-04-15 Fet bias circuit

Publications (1)

Publication Number Publication Date
JPS63258053A true JPS63258053A (en) 1988-10-25

Family

ID=14015171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62091032A Pending JPS63258053A (en) 1987-04-15 1987-04-15 Fet bias circuit

Country Status (1)

Country Link
JP (1) JPS63258053A (en)

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