JP2003124383A5 - - Google Patents
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- JP2003124383A5 JP2003124383A5 JP2001320554A JP2001320554A JP2003124383A5 JP 2003124383 A5 JP2003124383 A5 JP 2003124383A5 JP 2001320554 A JP2001320554 A JP 2001320554A JP 2001320554 A JP2001320554 A JP 2001320554A JP 2003124383 A5 JP2003124383 A5 JP 2003124383A5
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Claims (30)
上記半導体チップは、
内部回路と、
上記内部回路で形成された信号を出力する複数の出力回路と、
上記内部回路に対して動作電圧を供給する第１電圧供給電極と、
上記複数の出力回路に対して動作電圧を供給する複数の第２電圧供給電極とを備え、
上記パッケージ基板は、
上記半導体チップの搭載面に設けられ、上記半導体チップの上記第１電圧供給電極に一端が接続される第１電極と、
上記半導体チップの搭載面に設けられ、上記半導体チップの上記複数の第２電圧供給電極に一端がそれぞれ接続される複数の第２電極と、
上記第１及び第２電極が形成される配線層とは異なる配線層を含み、上記第２電極をそれぞれを共通に接続する第１配線手段と、
上記第１電極と上記外部端子の対応するものとを接続する第２配線手段と、
上記第１配線手段と上記第２電極よりも少ない数に集約された数の外部端子の複数とをそれぞれ接続する複数の第３配線手段とを備えてなることを特徴とする半導体装置。A semiconductor chip is mounted, and includes a plurality of external terminals and a package substrate having a plurality of wiring layers connected thereto,
The semiconductor chip is
Internal circuitry,
A plurality of output circuits for outputting signals formed by the internal circuit;
A first voltage supply electrode for supplying an operating voltage to the internal circuit;
A plurality of second voltage supply electrodes for supplying an operating voltage to the plurality of output circuits,
The package substrate is
A first electrode provided on a mounting surface of the semiconductor chip and having one end connected to the first voltage supply electrode of the semiconductor chip;
A plurality of second electrodes provided on a mounting surface of the semiconductor chip, each having one end connected to the plurality of second voltage supply electrodes of the semiconductor chip;
First wiring means including a wiring layer different from the wiring layer on which the first and second electrodes are formed, and connecting the second electrodes in common;
Second wiring means for connecting the first electrode and the corresponding one of the external terminals;
A semiconductor device comprising: a plurality of third wiring means for respectively connecting the first wiring means and a plurality of external terminals aggregated to a smaller number than the second electrodes.
上記半導体チップは、
内部回路と、
上記内部回路で形成された信号を出力する複数の出力回路と、
上記内部回路に対して動作電圧を供給する第１電圧供給電極と、
上記複数の出力回路に対して動作電圧を供給する複数の第２電圧供給電極とを備え、
上記パッケージ基板は、
上記半導体チップが搭載される基板表面に設けられ、上記半導体チップの上記第１電圧供給電極に一端が接続される第１電極と、
上記半導体チップが搭載される基板表面に設けられ、上記半導体チップの上記複数の第２電圧供給電極に一端がそれぞれ接続される複数の第２電極と、
上記第１及び第２電極が形成される配線層とは異なる配線層を含み、上記第２電極をそれぞれを共通に接続する第１配線手段と、
上記第１電極と上記裏面に設けられた上記外部端子の対応するものとを接続する第２配線手段と、
上記第１配線手段と上記裏面に設けられた上記第２電極よりも少ない数に集約された数の外部端子の複数とをそれぞれ接続する複数の第３配線手段とを備えてなることを特徴とする半導体装置。A package substrate having a plurality of wiring layers with a semiconductor chip mounted on the front surface and external terminals provided on the back surface;
The semiconductor chip is
Internal circuitry,
A plurality of output circuits for outputting signals formed by the internal circuit;
A first voltage supply electrode for supplying an operating voltage to the internal circuit;
A plurality of second voltage supply electrodes for supplying an operating voltage to the plurality of output circuits,
The package substrate is
A first electrode provided on a surface of the substrate on which the semiconductor chip is mounted and having one end connected to the first voltage supply electrode of the semiconductor chip;
A plurality of second electrodes provided on a surface of the substrate on which the semiconductor chip is mounted, each having one end connected to the plurality of second voltage supply electrodes of the semiconductor chip;
First wiring means including a wiring layer different from the wiring layer on which the first and second electrodes are formed, and connecting the second electrodes in common;
A second wiring means for connecting the first electrode and a corresponding one of the external terminals provided on the back surface;
A plurality of third wiring means that respectively connect the first wiring means and a plurality of external terminals that are aggregated in a smaller number than the second electrodes provided on the back surface. Semiconductor device.
上記パッケージ基板には、上記第１及び第２電極が形成される配線層とは異なる配線層を含み、上記半導体チップの内部回路及び複数の出力回路に対して回路の接地電位を共通に与える第４配線手段及びこれらの第４配線手段を介して接続される複数の外部端子を備えてなることを特徴とする半導体装置。In claim 1 or 2,
The package substrate includes a wiring layer different from the wiring layer on which the first and second electrodes are formed, and a circuit ground potential is commonly applied to the internal circuit and the plurality of output circuits of the semiconductor chip. A semiconductor device comprising four wiring means and a plurality of external terminals connected via the fourth wiring means.
上記第２電極よりも少ない数に集約された数は４以上であり、
これら４以上の外部端子は上記裏面に外部端子が形成される領域を４等分した領域に分散して配置されるものであることを特徴とする半導体装置。In claim 1 or 2,
The number aggregated into a smaller number than the second electrode is 4 or more,
These four or more external terminals are distributed in a region obtained by dividing the region where the external terminals are formed on the back surface into four equal parts.
上記第２電極をそれぞれを共通に接続する第１配線手段は、電気的に分離して２以上の組に分割され、それぞれの組に対して外部端子から異なる動作電圧の供給を可能とすることを特徴とする半導体装置。In claim 4,
The first wiring means for connecting the second electrodes in common is electrically separated and divided into two or more sets, and each set can be supplied with a different operating voltage from an external terminal. A semiconductor device characterized by the above.
上記半導体チップと上記パッケージ基板の対応する電極同士の接続は、フリップチップ構成にされるものであることを特徴とする半導体装置。In claim 5,
The semiconductor device is characterized in that the connection between corresponding electrodes of the semiconductor chip and the package substrate is a flip chip configuration.
上記半導体チップと上記パッケージ基板の対応する電極同士の接続は、ワイヤボンディング構成にされるものであることを特徴とする半導体装置。In claim 5,
A connection between the corresponding electrodes of the semiconductor chip and the package substrate is a wire bonding configuration.
上記半導体チップが搭載された位置に対応した裏面の内側に、上記内部回路に動作電圧を供給する外部端子が設けられ、
上記半導体チップが搭載された位置に対応した裏面の外側に、上記出力回路に動作電圧を供給する外部端子及び信号の入力又は出力用の外部端子が設けられるものであることを特徴とする特徴とする半導体装置。In claim 6,
Inside the back surface corresponding to the position where the semiconductor chip is mounted, an external terminal for supplying an operating voltage to the internal circuit is provided,
An external terminal for supplying an operating voltage to the output circuit and an external terminal for signal input or output are provided outside the back surface corresponding to the position where the semiconductor chip is mounted. Semiconductor device.
上記半導体チップは、２以上からなることを特徴とする半導体装置。In claim 2,
2. The semiconductor device according to claim 1, wherein the semiconductor chip comprises two or more.
上記２以上の半導体チップは、上記パッケージ基板上の表面にそれぞれが搭載されるものであることを特徴とする半導体装置。In claim 9,
2. The semiconductor device according to claim 1, wherein each of the two or more semiconductor chips is mounted on a surface of the package substrate.
上記外部端子は、グリットアレイタイプであることを特徴とする半導体装置。In claim 2,
The external device is a grit array type semiconductor device.
上記半導体装置は、
動作電圧を供給する複数の電源端子と、
回路の接地電位を供給する複数の接地端子とを備え、
上記実装基板は、
上記半導体装置が搭載される基板表面に設けられ、上記半導体装置の上記複数の電源端子一端がそれぞれ接続される複数の第１電極と、
上記半導体装置が搭載される基板表面に設けられ、上記半導体装置の上記複数の接地端子一端がそれぞれ接続される複数の第２電極と、
上記第１電極が形成される配線層とは異なる配線層を含み、上記第１電極を共通に接続する第１配線手段と、
上記第２電極が形成される配線層とは異なる配線層を含み、上記第２電極を共通に接続する第２配線手段と、
上記第１配線手段と上記裏面に設けられた上記第１電極よりも少ない数に集約された数の第３電極とを接続する第３配線手段と、
上記第２配線手段と上記裏面に設けられた上記第２電極よりも少ない数に集約された数の第４電極を接続する第４配線手段と、
上記第３電極と第４電極間に設けられたバイパスコンデンサとを備えてなることを特徴とする電子装置。A semiconductor device and a mounting substrate on which the semiconductor device is mounted on the front surface and a bypass capacitor is provided on the back surface;
The semiconductor device is
A plurality of power supply terminals for supplying operating voltage;
A plurality of ground terminals for supplying a circuit ground potential;
The mounting board is
A plurality of first electrodes provided on a substrate surface on which the semiconductor device is mounted, to which one ends of the plurality of power supply terminals of the semiconductor device are respectively connected;
A plurality of second electrodes provided on a surface of the substrate on which the semiconductor device is mounted, to which one ends of the plurality of ground terminals of the semiconductor device are respectively connected;
A first wiring means including a wiring layer different from the wiring layer on which the first electrode is formed, and connecting the first electrodes in common;
A second wiring means including a wiring layer different from the wiring layer on which the second electrode is formed, and connecting the second electrode in common;
A third wiring means for connecting the first wiring means and a number of third electrodes aggregated to a smaller number than the first electrodes provided on the back surface;
A fourth wiring means for connecting the second wiring means and a number of fourth electrodes aggregated to a smaller number than the second electrodes provided on the back surface;
An electronic device comprising a bypass capacitor provided between the third electrode and the fourth electrode.
上記半導体装置は、外部端子がグリットアレイタイプであることを特徴とする電子装置。In claim 12,
In the semiconductor device, the external terminal is a grid array type.
上記パッケージ基板の表面に搭載される半導体チップとを備え、
上記半導体チップは、
内部回路と、
上記内部回路と外部装置の間で信号のインターフェースを行う入出力回路と、
上記内部回路に対して第１動作電圧を供給する第１電圧供給電極と、
上記入出力回路に対して上記第１動作電圧とは異なる第２動作電圧を供給する第２電圧供給電極とを有し、
上記パッケージ基板は、
上記パッケージ基板の表面に設けられ、かつ、上記半導体チップの上記第１電圧供給電極と電気的に接続される第１電極と、
上記パッケージ基板の表面に設けられ、かつ、上記半導体チップの上記第２電圧供給電極と電気的に接続される第２電極と、
上記第１及び第２電極とは異なる配線層であり、かつ、スルーホールを介して第１電極と電気的に接続する第１配線プレーンと、
上記第１配線プレーンと同じ配線層に形成され、かつ、スルーホールを介して上記第２電極と電気的に接続する第２配線プレーンと、
上記第１及び第２配線プレーンと上記第１及び第２電極とは異なる配線層であり、かつ、上記半導体チップの内部回路と入出力回路に対して基準電位を共通に供給する第３配線プレーンと、
上記パッケージ基板の表面と反対側の裏面に設けられた第３電極とを有し、
上記第３電極は上記パッケージ基板の外部端子として用いられ、
上記第１及び第２配線プレーンは、平面において、互いに分離されていることを特徴とする半導体装置。A package substrate having a multilayer structure;
A semiconductor chip mounted on the surface of the package substrate,
The semiconductor chip is
Internal circuitry,
An input / output circuit for interfacing signals between the internal circuit and an external device;
A first voltage supply electrode for supplying a first operating voltage to the internal circuit;
A second voltage supply electrode for supplying a second operating voltage different from the first operating voltage to the input / output circuit;
The package substrate is
A first electrode provided on a surface of the package substrate and electrically connected to the first voltage supply electrode of the semiconductor chip;
A second electrode provided on the surface of the package substrate and electrically connected to the second voltage supply electrode of the semiconductor chip;
A first wiring plane that is a wiring layer different from the first and second electrodes and is electrically connected to the first electrode through a through hole;
A second wiring plane formed in the same wiring layer as the first wiring plane and electrically connected to the second electrode through a through hole;
The first and second wiring planes and the first and second electrodes are different wiring layers, and a third wiring plane that supplies a common reference potential to the internal circuit and the input / output circuit of the semiconductor chip. When,
A third electrode provided on the back surface opposite to the front surface of the package substrate,
The third electrode is used as an external terminal of the package substrate;
The semiconductor device according to claim 1, wherein the first and second wiring planes are separated from each other in a plane.
上記半導体チップは、
上記内部回路で形成された信号をそれぞれ出力する複数の入出力回路と、
上記複数の入出力回路に対してそれぞれ異なった動作電圧を供給する複数の第２電圧供給電極とを有することを特徴とする半導体装置。In claim 14,
The semiconductor chip is
A plurality of input / output circuits each outputting a signal formed by the internal circuit;
A semiconductor device comprising: a plurality of second voltage supply electrodes for supplying different operating voltages to the plurality of input / output circuits.
上記第２配線プレーンは、平面において、互いに分離されている複数の配線層を有することを特徴とする半導体装置。In claim 14,
The second wiring plane includes a plurality of wiring layers separated from each other in a plane.
上記パッケージ基板には上記第１、第２及び第３配線プレーンと上記第１及び第２電極が形成される配線層とは異なる第４配線プレーンを介して接続される複数の外部端子が設けられていることを特徴とする半導体装置。In claim 14,
The package substrate is provided with a plurality of external terminals connected via a fourth wiring plane different from the wiring layer on which the first, second and third wiring planes and the first and second electrodes are formed. A semiconductor device characterized by that.
上記第２配線プレーンは、電気的に分離して２以上の組に分割され、それぞれの組に対して外部端子から異なる動作電圧の供給を可能とすることを特徴とする半導体装置。In claim 16,
The second wiring plane is electrically separated and divided into two or more groups, and a different operating voltage can be supplied from an external terminal to each group.
上記半導体チップと上記パッケージ基板の対応する電極同士の接続は、フリップチップ構成にされるものであることを特徴とする半導体装置。In claim 18,
The semiconductor device is characterized in that the connection between corresponding electrodes of the semiconductor chip and the package substrate is a flip chip configuration.
上記半導体チップと上記パッケージ基板の対応する電極同士の接続は、ワイヤボンディング構成にされるものであることを特徴とする半導体装置。In claim 18,
A connection between the corresponding electrodes of the semiconductor chip and the package substrate is a wire bonding configuration.
上記半導体チップが搭載された位置に対応した裏面の内側に、上記内部回路に動作電圧を供給する外部端子が設けられ、
上記半導体チップが搭載された位置に対応した裏面の外側に、上記入出力回路に動作電圧を供給する外部端子及び信号の入力又は出力用の外部端子が設けられるものであることを特徴とする特徴とする半導体装置。In claim 14,
Inside the back surface corresponding to the position where the semiconductor chip is mounted, an external terminal for supplying an operating voltage to the internal circuit is provided,
An external terminal for supplying an operating voltage to the input / output circuit and an external terminal for signal input or output are provided outside the back surface corresponding to the position where the semiconductor chip is mounted. A semiconductor device.
前記パッケージ基板の表面に搭載される半導体チップとを備え、
上記半導体チップは、
内部回路と、
上記内部回路と外部装置の間で信号のインターフェースを行う入出力回路と、
上記内部回路に対して第１動作電圧を供給する第１電圧供給電極と、
上記入出力回路に対して上記第１動作電圧とは異なる第２動作電圧を供給する第２電圧供給電極とを有し、
上記パッケージ基板は、
上記パッケージ基板の表面に設けられ、かつ、上記半導体チップの上記第１電圧供給電極と電気的に接続される第１電極と、
上記パッケージ基板の表面に設けられ、かつ、上記半導体チップの上記第２電圧供給電極と電気的に接続される第２電極と、
上記第１及び第２電極とは異なる配線層であり、かつ、スルーホールを介して第１電極と電気的に接続する第１配線プレーンと、
上記第１配線プレーンと同じ配線層に形成され、かつ、上記第１配線プレーンの外側に形成され、かつ、スルーホールを介して上記第２電極と電気的に接続する第２配線プレーンと、
上記第１及び第２配線プレーンと上記第１及び第２電極とは異なる配線層であり、かつ、上記半導体チップの内部回路と入出力回路に対して基準電位を共通に供給する第３配線プレーンと、
上記パッケージ基板の表面と反対側の裏面に設けられた第３電極とを有し、
上記第３電極は上記パッケージ基板の外部端子として用いられ、
上記第１及び第２配線プレーンは、平面において、互いに分離されていることを特徴とする半導体装置。A package substrate having a multilayer structure;
A semiconductor chip mounted on the surface of the package substrate,
The semiconductor chip is
Internal circuitry,
An input / output circuit for interfacing signals between the internal circuit and an external device;
A first voltage supply electrode for supplying a first operating voltage to the internal circuit;
A second voltage supply electrode for supplying a second operating voltage different from the first operating voltage to the input / output circuit;
The package substrate is
A first electrode provided on a surface of the package substrate and electrically connected to the first voltage supply electrode of the semiconductor chip;
A second electrode provided on the surface of the package substrate and electrically connected to the second voltage supply electrode of the semiconductor chip;
A first wiring plane that is a wiring layer different from the first and second electrodes and is electrically connected to the first electrode through a through hole;
A second wiring plane formed in the same wiring layer as the first wiring plane and formed outside the first wiring plane and electrically connected to the second electrode through a through hole;
The first and second wiring planes and the first and second electrodes are different wiring layers, and a third wiring plane that supplies a common reference potential to the internal circuit and the input / output circuit of the semiconductor chip. When,
A third electrode provided on the back surface opposite to the front surface of the package substrate,
The third electrode is used as an external terminal of the package substrate;
The semiconductor device according to claim 1, wherein the first and second wiring planes are separated from each other in a plane.
上記半導体チップは、
上記内部回路で形成された信号をそれぞれ出力する複数の入出力回路と、
上記複数の入出力回路に対してそれぞれ異なった動作電圧を供給する複数の第２電圧供給電極とを有することを特徴とする半導体装置。In claim 22,
The semiconductor chip is
A plurality of input / output circuits each outputting a signal formed by the internal circuit;
A semiconductor device comprising: a plurality of second voltage supply electrodes for supplying different operating voltages to the plurality of input / output circuits.
上記第２配線プレーンは、平面において、互いに分離されている複数の配線層を有することを特徴とする半導体装置。In claim 22,
The second wiring plane includes a plurality of wiring layers separated from each other in a plane.
上記パッケージ基板には上記第１、第２及び第３配線プレーンと上記第１及び第２電極が形成される配線層とは異なる第４配線プレーンを介して接続される複数の外部端子が設けられていることを特徴とする半導体装置。In claim 22,
The package substrate is provided with a plurality of external terminals connected via a fourth wiring plane different from the wiring layer on which the first, second and third wiring planes and the first and second electrodes are formed. A semiconductor device characterized by that.
上記第２配線プレーンは、電気的に分離して２以上の組に分割され、それぞれの組に対して外部端子から異なる動作電圧の供給を可能とすることを特徴とする半導体装置。In claim 24,
The second wiring plane is electrically separated and divided into two or more groups, and a different operating voltage can be supplied from an external terminal to each group.
前記パッケージ基板の表面に搭載される半導体チップとを備え、
上記半導体チップは、
内部回路と、
上記内部回路と外部装置の間で信号のインターフェースを行う入出力回路と、
上記内部回路に対して第１動作電圧を供給する第１電圧供給電極と、
上記入出力回路に対して上記第２動作電圧とは異なる第１動作電圧を供給する第２電圧供給電極とを有し、
上記パッケージ基板は、
上記パッケージ基板の表面に設けられ、かつ、上記半導体チップの上記第１電圧供給電極に電気的に接続される第１電極と、
上記パッケージ基板の表面に設けられ、かつ、上記半導体チップの上記第２電圧供給電極に電気的に接続される第２電極と、
上記第１及び第２電極とは異なる配線層であり、かつ、スルーホールを介して第１電極と電気的に接続する第１配線プレーンと、
上記第１配線プレーンと同じ配線層に形成され、かつ、スルーホールを介して上記第２電極と電気的に接続する第２配線プレーンと、
上記第１及び第２配線プレーンと上記第１及び第２電極とは異なる配線層であり、かつ、上記半導体チップの内部回路と入出力回路に対して基準電位を共通に供給する第３配線プレーンと、
上記パッケージ基板の表面と反対側の裏面に設けられた第３電極とを有し、
上記第３電極は上記パッケージ基板の外部端子として用いられ、
上記外部端子及び上記第２配線プレーンは、上記パッケージの１辺と上記第１配線プレーンとの間に設けられ、
上記外部端子は、上記パッケージの上記１辺と上記第２配線プレーンとの間に設けられ、
上記第１及び第２配線プレーンは、平面において、互いに分離されていることを特徴とする半導体装置。A package substrate having a rectangular plane and a plurality of multilayer structures;
A semiconductor chip mounted on the surface of the package substrate,
The semiconductor chip is
Internal circuitry,
An input / output circuit for interfacing signals between the internal circuit and an external device;
A first voltage supply electrode for supplying a first operating voltage to the internal circuit;
A second voltage supply electrode for supplying a first operating voltage different from the second operating voltage to the input / output circuit;
The package substrate is
A first electrode provided on a surface of the package substrate and electrically connected to the first voltage supply electrode of the semiconductor chip;
A second electrode provided on the surface of the package substrate and electrically connected to the second voltage supply electrode of the semiconductor chip;
A first wiring plane that is a wiring layer different from the first and second electrodes and is electrically connected to the first electrode through a through hole;
A second wiring plane formed in the same wiring layer as the first wiring plane and electrically connected to the second electrode through a through hole;
The first and second wiring planes and the first and second electrodes are different wiring layers, and a third wiring plane that supplies a common reference potential to the internal circuit and the input / output circuit of the semiconductor chip. When,
A third electrode provided on the back surface opposite to the front surface of the package substrate,
The third electrode is used as an external terminal of the package substrate;
The external terminal and the second wiring plane are provided between one side of the package and the first wiring plane,
The external terminal is provided between the one side of the package and the second wiring plane,
The semiconductor device according to claim 1, wherein the first and second wiring planes are separated from each other in a plane.
上記外部端子及び上記第２配線プレーンは、上記パッケージの上記１辺と対向する対辺と上記第１配線プレーンとの間に設けられ、
上記外部端子は、上記パッケージの上記対辺と上記第２配線プレーンとの間に設けられていることを特徴とする半導体装置。In claim 27,
The external terminal and the second wiring plane are provided between a side opposite to the one side of the package and the first wiring plane,
The semiconductor device according to claim 1, wherein the external terminal is provided between the opposite side of the package and the second wiring plane.
上記パッケージ基板には上記第１、第２及び第３配線プレーンと上記第１及び第２電極が形成される配線層とは異なる第４配線プレーンを介して接続される複数の外部端子が設けられていることを特徴とする半導体装置。In claim 27,
The package substrate is provided with a plurality of external terminals connected via a fourth wiring plane different from the wiring layer on which the first, second and third wiring planes and the first and second electrodes are formed. A semiconductor device characterized by that.
上記第２配線プレーンは、電気的に分離して２以上の組に分割され、それぞれの組に対して外部端子から異なる動作電圧の供給を可能とすることを特徴とする半導体装置。In claim 28,
The second wiring plane is electrically separated and divided into two or more groups, and a different operating voltage can be supplied from an external terminal to each group.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001320554A JP4387076B2 (en) | 2001-10-18 | 2001-10-18 | Semiconductor device |
| TW091123439A TW586211B (en) | 2001-10-18 | 2002-10-11 | Semiconductor device and electronic device |
| US10/268,700 US6803659B2 (en) | 2001-10-18 | 2002-10-11 | Semiconductor device and an electronic device |
| KR1020020063624A KR100929620B1 (en) | 2001-10-18 | 2002-10-17 | Semiconductor device and electronic device |
| US10/939,491 US7095117B2 (en) | 2001-10-18 | 2004-09-14 | Semiconductor device and an electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001320554A JP4387076B2 (en) | 2001-10-18 | 2001-10-18 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006154886A Division JP2006245613A (en) | 2006-06-02 | 2006-06-02 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003124383A JP2003124383A (en) | 2003-04-25 |
| JP2003124383A5 true JP2003124383A5 (en) | 2005-06-16 |
| JP4387076B2 JP4387076B2 (en) | 2009-12-16 |
Family
ID=19137927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001320554A Expired - Fee Related JP4387076B2 (en) | 2001-10-18 | 2001-10-18 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6803659B2 (en) |
| JP (1) | JP4387076B2 (en) |
| KR (1) | KR100929620B1 (en) |
| TW (1) | TW586211B (en) |
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| TW571375B (en) * | 2002-11-13 | 2004-01-11 | Advanced Semiconductor Eng | Semiconductor package structure with ground and method for manufacturing thereof |
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| US7183786B2 (en) * | 2003-03-04 | 2007-02-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Modifying a semiconductor device to provide electrical parameter monitoring |
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| JP4195883B2 (en) * | 2004-02-04 | 2008-12-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Multilayer module |
| JP3999759B2 (en) * | 2004-04-02 | 2007-10-31 | 富士通株式会社 | Substrate and electronic equipment |
| JP4647243B2 (en) * | 2004-05-24 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP4552524B2 (en) * | 2004-06-10 | 2010-09-29 | パナソニック株式会社 | Composite electronic components |
| TWI237380B (en) * | 2004-11-19 | 2005-08-01 | Advanced Semiconductor Eng | Build-up via for suppressing simultaneous switching noise |
| JP4640950B2 (en) * | 2005-05-16 | 2011-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US7250673B2 (en) * | 2005-06-06 | 2007-07-31 | Triquint Semiconductor, Inc. | Signal isolation in a package substrate |
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| US8063480B2 (en) * | 2006-02-28 | 2011-11-22 | Canon Kabushiki Kaisha | Printed board and semiconductor integrated circuit |
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| JP2009111138A (en) * | 2007-10-30 | 2009-05-21 | Mitsubishi Electric Corp | Semiconductor integrated circuit package and circuit substrate |
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| JP6207422B2 (en) * | 2014-02-19 | 2017-10-04 | ルネサスエレクトロニクス株式会社 | Electronic equipment |
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-
2002
- 2002-10-11 US US10/268,700 patent/US6803659B2/en not_active Expired - Fee Related
- 2002-10-11 TW TW091123439A patent/TW586211B/en not_active IP Right Cessation
- 2002-10-17 KR KR1020020063624A patent/KR100929620B1/en not_active IP Right Cessation
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2004
- 2004-09-14 US US10/939,491 patent/US7095117B2/en not_active Expired - Fee Related
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