JP2745932B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2745932B2 JP2745932B2 JP2937292A JP2937292A JP2745932B2 JP 2745932 B2 JP2745932 B2 JP 2745932B2 JP 2937292 A JP2937292 A JP 2937292A JP 2937292 A JP2937292 A JP 2937292A JP 2745932 B2 JP2745932 B2 JP 2745932B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- power supply
- thin film
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
バイパスコンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a bypass capacitor.
【０００２】[0002]
【従来の技術】近年、トランジスタの駆動能力の向上に
よる半導体装置の動作の高速化や回路の集積度の増大に
より、半導体素子内における電源ノイズΔＶにる電位変
動が回路の動作性能を著しく制限するようになってい
る。半導体チップ内で同時動作する出力バッファ数を
Ｎ，動作時の出力バッファの電流変化をｄｉ／ｄｔ，電
源及びＧＮＤ配線のインダクタンス成分をＬとすれば電
源ノイズΔＶは次式により与えられる。2. Description of the Related Art In recent years, due to an increase in the operation speed of a semiconductor device and an increase in the degree of integration of a circuit due to an improvement in the driving capability of a transistor, a potential fluctuation due to a power supply noise ΔV in a semiconductor element significantly limits the operation performance of the circuit. It has become. Assuming that the number of output buffers operating simultaneously in the semiconductor chip is N, the current change of the output buffers during operation is di / dt, and the inductance components of the power supply and the GND wiring are L, the power supply noise ΔV is given by the following equation.
【０００３】ΔＶ＝Ｎ×Ｌ ｄｉ／ｄｔ この電源ノイズΔＶにより半導体素子の誤動作、機能低
下が生じている。ΔV = N × L di / dt This power supply noise ΔV causes a malfunction and a decrease in function of a semiconductor element.
【０００４】従来の半導体装置の第１の例は、図３に示
すように、プリント基板１０上に搭載した半導体装置９
の電源ピンとＧＮＤピンの間に接続して半導体装置９近
傍のプリント基板１０上にチップ形積層セラミックコン
デンサ１１を設置して電源ノイズをバイパスしていた。A first example of a conventional semiconductor device is a semiconductor device 9 mounted on a printed circuit board 10 as shown in FIG.
A chip-type multilayer ceramic capacitor 11 is connected between a power supply pin and a GND pin of the semiconductor device 9 and is mounted on a printed circuit board 10 near the semiconductor device 9 to bypass power supply noise.
【０００５】また、従来の半導体装置の第２の例は、図
４（ａ），（ｂ）に示すように、半導体装置９のパッケ
ージ上にチップ形セラミックコンデンサ１１を搭載し
て、パケージ内のリード６に接続し、パッケージに搭載
した半導体チップ１の電源電極とＧＮＤ電極との間に金
属細線７を介して接続している。In a second example of a conventional semiconductor device, a chip type ceramic capacitor 11 is mounted on a package of a semiconductor device 9 as shown in FIGS. It is connected to a lead 6 and is connected via a thin metal wire 7 between a power supply electrode of the semiconductor chip 1 mounted on the package and a GND electrode.
【０００６】また、従来の半導体装置の第３の例は、図
５に示すように、パッケージ上に搭載した半導体チップ
１の上面に設けた薄膜コンデンサ１３を半導体チップ１
の電源電極２とＧＮＤ電極３との間に金属細線７により
接続していた。In a third example of a conventional semiconductor device, as shown in FIG. 5, a thin film capacitor 13 provided on the upper surface of a semiconductor chip 1 mounted on a package is connected to the semiconductor chip 1.
Between the power supply electrode 2 and the GND electrode 3 by a thin metal wire 7.
【０００７】[0007]
【発明が解決しようとする課題】従来の半導体装置は、
バイパスコンデンサをプリント基板上又はパッケージ上
に搭載したものでは半導体チップと内部リード間を接続
する金属細線及び内部リードによるインダクタンス成分
により、生ずる電源ノイズは除去できなかった。A conventional semiconductor device is:
In the case where the bypass capacitor is mounted on a printed circuit board or a package, power supply noise generated due to an inductance component due to a thin metal wire connecting the semiconductor chip and the internal lead and the internal lead cannot be removed.
【０００８】また、半導体チップ上に薄膜コンデンサを
形成するものでは、すべての電源およびＧＮＤ電極に接
続するために容量を大きくしなければならず高周波特性
が悪くなるという欠点があった。Further, in the case of forming a thin film capacitor on a semiconductor chip, there is a disadvantage that the capacitance must be increased in order to connect to all the power supplies and the GND electrodes, so that high frequency characteristics are deteriorated.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置は、
集積回路を形成した半導体チップと、前記半導体チップ
の上面に設けた絶縁膜の上にアレイ状に配置して設け且
つ前記半導体チップに設けた複数の電源電極とＧＮＤ電
極とのそれぞれの間に個々に接続された薄膜チップコン
デンサとを備えている。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip on which an integrated circuit is formed, and a plurality of power supply electrodes provided on the semiconductor chip and arranged in an array on an insulating film provided on the semiconductor chip; And a thin film chip capacitor connected to the
【００１０】[0010]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【００１１】図１は本発明の第１の実施例を示すレイア
ウト図である。FIG. 1 is a layout diagram showing a first embodiment of the present invention.
【００１２】図１に示すように、半導体集積回路を形成
した半導体チップ１の上に絶縁膜４を形成し、絶縁膜４
の上に薄膜チップコンデンサ５を複数個アレイ状に配置
して搭載する。ここで、薄膜チップコンデンサ５は例え
ば、シリコン基板上に選択的に設けた金属薄膜を下層電
極とし、チタン酸ストロンチウム等の誘電体膜を介して
上層電極となる金属薄膜を対向させて設けたコンデンサ
をチップ状に分割したもので１個のチップ上に１個又は
複数のコンデンサを形成している。As shown in FIG. 1, an insulating film 4 is formed on a semiconductor chip 1 on which a semiconductor integrated circuit is formed.
A plurality of thin film chip capacitors 5 are arranged in an array and mounted thereon. Here, the thin film chip capacitor 5 is, for example, a capacitor in which a metal thin film selectively provided on a silicon substrate is used as a lower electrode, and a metal thin film serving as an upper electrode is opposed to the metal thin film via a dielectric film such as strontium titanate. Is divided into chips, and one or a plurality of capacitors are formed on one chip.
【００１３】次に、半導体チップ１に設けたそれぞれの
電源電極２とＧＮＤ電極３の間に薄膜チップコンデンサ
５のそれぞれを金属細線７で接続し、電源電極２，ＧＮ
Ｄ電極３のそれぞれはパッケージの内部リード６とそれ
ぞれ金属細線７で接続する。Next, each of the thin-film chip capacitors 5 is connected between the respective power supply electrodes 2 provided on the semiconductor chip 1 and the GND electrode 3 by a thin metal wire 7, and the power supply electrodes 2 and GND are connected.
Each of the D electrodes 3 is connected to an internal lead 6 of the package by a thin metal wire 7.
【００１４】このように、薄膜チップコンデンサ５は半
導体チップ１の電源電極２のそれぞれに対して個々に接
続できるので、比較的小さい容量のコンデンサで電源ノ
イズをバイパスすることができ、高周波特性にも優れ
る。As described above, since the thin film chip capacitor 5 can be individually connected to each of the power supply electrodes 2 of the semiconductor chip 1, power supply noise can be bypassed by a capacitor having a relatively small capacity, and high frequency characteristics can be reduced. Excellent.
【００１５】図２は本発明の第２の実施例を示すレイア
ウト図である。FIG. 2 is a layout diagram showing a second embodiment of the present invention.
【００１６】図２に示すように、アレイ状に配置した薄
膜チップコンデンサ５の周囲の絶縁膜４の上に枠状にＧ
ＮＤ配線８を設けた以外は第１の実施例と同様の構成を
有しており、ＧＮＤ配線８を介して薄膜チップコンデン
サ５とＧＮＤ電極３との間を接続することにより、ＧＮ
Ｄ側のインダクタンスを低減できる利点がある。As shown in FIG. 2, a frame-like G is formed on the insulating film 4 around the thin film chip capacitors 5 arranged in an array.
The configuration is the same as that of the first embodiment except that the ND wiring 8 is provided. By connecting the thin film chip capacitor 5 and the GND electrode 3 via the GND wiring 8, the GN wiring is achieved.
There is an advantage that the inductance on the D side can be reduced.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、半導体装
置内の半導体チップ上に薄膜チップコンデンサをアレイ
状に搭載して半導体チップ上の各電源電極毎に薄膜チッ
プコンデンサを接続することにより、電源電位とＧＮＤ
電位との間に生ずる電源ノイズをバイパスして電源ノイ
ズが低減できるという効果を有する。As described above, according to the present invention, thin-film chip capacitors are mounted in an array on a semiconductor chip in a semiconductor device and connected to each power supply electrode on the semiconductor chip. Power supply potential and GND
There is an effect that power supply noise can be reduced by bypassing power supply noise generated between the power supply voltage and the potential.
【００１８】また、各電源電極毎に個々の薄膜チップコ
ンデンサを接続することができるので各薄膜チップコン
デンサの容量が小さくても良く高周波特性にも優れると
いう利点を有する。Further, since an individual thin film chip capacitor can be connected to each power supply electrode, there is an advantage that the capacity of each thin film chip capacitor can be small and the high frequency characteristics are excellent.
【図１】本発明の第１の実施例を示すレイアウト図。FIG. 1 is a layout diagram showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示すレイアウト図。FIG. 2 is a layout diagram showing a second embodiment of the present invention.
【図３】従来の半導体装置の第１の例を示す斜視図。FIG. 3 is a perspective view showing a first example of a conventional semiconductor device.
【図４】従来の半導体装置の第２の例を示す斜視図及び
模式的断面図。FIG. 4 is a perspective view and a schematic cross-sectional view showing a second example of a conventional semiconductor device.
【図５】従来の半導体装置の第３の例を示す模式的断面
図。FIG. 5 is a schematic cross-sectional view showing a third example of a conventional semiconductor device.
１ 半導体チップ ２ 電源電極 ３ ＧＮＤ電極 ４ 絶縁膜 ５ 薄膜チップコンデンサ ６ 内部リード ７ 金属細線 ８ ＧＮＤ配線 ９ 半導体装置 １０ プリント基板 １１ チップ形セラミックコンデンサ １２ 外部リード １３ 薄膜コンデンサ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Power supply electrode 3 GND electrode 4 Insulating film 5 Thin film chip capacitor 6 Internal lead 7 Fine metal wire 8 GND wiring 9 Semiconductor device 10 Printed circuit board 11 Chip type ceramic capacitor 12 External lead 13 Thin film capacitor
Claims (2)
記半導体チップの上面に設けた絶縁膜の上にアレイ状に
配置して設け且つ前記半導体チップに設けた複数の電源
電極とＧＮＤ電極とのそれぞれの間に個々に接続された
薄膜チップコンデンサとを備えたことを特徴とする半導
体装置。1. A semiconductor chip on which an integrated circuit is formed, and a plurality of power supply electrodes and a GND electrode provided in an array on an insulating film provided on an upper surface of the semiconductor chip and provided on the semiconductor chip. A semiconductor device comprising: a thin-film chip capacitor connected between each of them.
サの周囲の絶縁膜上に設けた枠状のＧＮＤ配線を有する
請求項１記載の半導体装置。2. The semiconductor device according to claim 1, further comprising a frame-shaped GND wiring provided on the insulating film around the thin film chip capacitors arranged in an array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2937292A JP2745932B2 (en) | 1992-02-17 | 1992-02-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2937292A JP2745932B2 (en) | 1992-02-17 | 1992-02-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05251635A JPH05251635A (en) | 1993-09-28 |
| JP2745932B2 true JP2745932B2 (en) | 1998-04-28 |
Family
ID=12274320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2937292A Expired - Fee Related JP2745932B2 (en) | 1992-02-17 | 1992-02-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2745932B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633785A (en) * | 1994-12-30 | 1997-05-27 | University Of Southern California | Integrated circuit component package with integral passive component |
| US7615856B2 (en) | 2004-09-01 | 2009-11-10 | Sanyo Electric Co., Ltd. | Integrated antenna type circuit apparatus |
-
1992
- 1992-02-17 JP JP2937292A patent/JP2745932B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05251635A (en) | 1993-09-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980113 |
|
| LAPS | Cancellation because of no payment of annual fees |