JPS6177354A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the reduction of manufacturing cost by reducing the by-pass capacitance and unnecessitating installation by a method wherein a by-pass capacitor is incorporated in a semiconductor chip. CONSTITUTION:A P<+> type impurity-diffused region 2 is formed in an N-Si substrate, and further an Si oxide layer 3 is grown on its surface. After a con tact hole CONT is formed in the Si oxide layer 3, a bonding pad (e.g. aluminum) is deposited, thus finishing the production of the title device. The bonding pad 4 of this device is electrically connected to package leads 5 by wire bonding 6. For example, in this case, VCC(GND) is impressed on the substrate 1, and VEE (-5V) is impressed on the pad 4 via leads 5. In other words, reverse bias is impressed on the P-N junction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to improvements in its power input section.

Conventional technology Generally, a semiconductor integrated circuit chip is sealed in a package.
This is mounted on a printed circuit board, etc., and a bypass capacitor is externally attached to the power input terminal, thereby eliminating the effects of wiring impedance and other power supply noise.

Problems to be Solved by the Invention However, in the above-mentioned external bypass capacitor, the capacitance is large, and as a result, the installation area becomes large.
There is a problem in that the manufacturing cost of devices using semiconductor integrated circuits increases due to the required installation work.

Means to Solve the Problems In view of the above-mentioned problems, an object of the present invention is to reduce the capacitance of the bypass capacitor by incorporating the bypass capacitor into a semiconductor chip, and to reduce manufacturing costs by eliminating the need for mounting work. The goal is to reduce However, the present invention is applicable to semiconductor chips that have recently become thicker due to the increase in capacity.
Therefore, we found an area in the semiconductor chip where it is possible to manufacture PN junction capacitors, and used PN junction capacitors as bypass capacitors.
This is an attempt to form an N-junction capacitor on a semiconductor chip.

Effect: When a bypass capacitor is built into a semiconductor chip as described above, the capacitor is connected after the lead inductance, bonding wire inductance, etc., so its capacitance can be small.

Example Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In FIG. 1, for example, a P type impurity diffusion region 2 is formed on an N-silicon substrate, and a silicon oxide layer 3 is further grown on the surface thereof. After forming the contact hole C0NT in the silicon oxide layer 3, a bonding pad (for example, aluminum) is deposited to complete the manufacturing of the semiconductor device.

The bonding pad 4 of the semiconductor device described above is electrically connected to a package (not shown) glue 5 by wire bonding 6. For example, in this case, Vcc (GND) is applied to the substrate 1, and VER (5V) is applied to the pad 4 via the solder 5. In other words, a reverse bias is applied to the PN junction.

FIG. 2 shows the equinodal circuit of FIG. In other words, human power supply V
EE is applied to the pad 4 via an inductance L1 caused by the lead 5 and an inductance L2 caused by the bonding wire 6, and is further applied to the pad 4 and the silicon substrate 1.
It is supplied to the internal circuit via the capacitance C1 and the PN junction capacitor C2. Of course, in this case, C1<
<C2.

As described in detail, according to the present invention, the bypass capacitor is formed as a PN junction capacitor within the semiconductor chip, so no external capacitor is required, and therefore manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1. 1: Silicon substrate (N-) 2: Impurity diffusion region (P+) 3 Silicon dioxide film 4: Bonding pad 5: Lead 6: Bonding wire C2: PN junction capacitor

Claims (1)

[Claims] 1. A semiconductor device in which a PN junction capacitor for a bypass capacitor is formed in a semiconductor chip, and the PN junction capacitor is connected to a power supply pad of the chip.