JP3059767B2 - Hybrid integrated circuit input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a hybrid integrated circuit, and more particularly, to a circuit for preventing a malfunction of a hybrid integrated circuit due to electric charges charged in a capacitance of a control signal line.

[0002]

2. Description of the Related Art An input circuit of a conventional hybrid integrated circuit will be described with reference to FIG. Although only a single arm represented by power transistors Q13 and Q14 is shown in the figure, for example, a three-phase inverter control device includes three such arms. The power transistors Q13, Q14, etc. of each arm connected between the DC voltages + VCC and -VCC are supplied with the control signal VI having the opposite phase.
Switching is performed at N1 and VIN2, and a pulse VOUT is output.

A power circuit composed of power transistors Q13, Q14 and the like is realized as a hybrid integrated circuit (50) on an insulating metal substrate. Further, a circuit configured by a micro computer or the like and controlling the power circuit is realized on, for example, a PC board (40). The hybrid integrated circuit (50) and the PC board (40) are connected by a plurality of lines (60).

Now, a control signal VS is applied to a reference potential VN1.
When 1 goes to a high level (VS2 goes to a low level), a transistor Q11 to which a high level VS1 is inputted as a base is turned on via a voltage dividing circuit composed of resistors R11 and R12, and the upper arm driver circuit Hi is driven. Is done. At this time, the high-level control signal VS1 charges the line capacitance C11 formed by the control signal line (60) and the internal wiring capacitance C12 of the hybrid integrated circuit (50). Although not shown, the midpoint potential VN1 is also charged to the wiring capacitance of the corresponding line (60).

Next, at a predetermined timing, the reference potential VN
When the control signal S2 becomes high level (VS1 is low level) with respect to the transistor 2, the transistor Q12 to which the high level VS2 is base-inputted via the voltage dividing circuit composed of the resistors R13 and R14 turns on and goes down. The driver circuit Lo of the arm is driven. As a result, the reference potential VN1 decreases accompanyingly. At this time, since the control signal line (60) has a relatively high impedance, the line capacitance C
11 and the internal wiring capacitance C12 are gradually discharged, while the line (6
0) is low impedance, so that the midpoint potential VN1
The electric charge charged in the wiring capacitance of the line (60) corresponding to the line is rapidly discharged.

Therefore, at the timing when the control signal VS2 changes to the high level with respect to the reference potential VN2, the control signal VS1 changes to the high level with respect to the reference potential VN1 instantaneously, and the driver circuit Hi of the upper arm is driven. You. As a result, power transistors Q13 and Q14
Are turned on at the same time, so that there is a problem that power consumption increases and that power transistors Q13 and Q14 are destroyed. Such a problem also exists in the input circuit of the lower arm.

[0007]

A problem to be solved is to prevent a control signal level with respect to a reference potential from unexpectedly changing due to a difference between a parasitic capacitance and a line impedance of a control signal line. Accordingly, an object of the present invention is to provide an input circuit of a hybrid integrated circuit in which a malfunction can be prevented, power consumption can be suppressed, and a power transistor can be protected.

[0008]

SUMMARY OF THE INVENTION According to the present invention, at the timing when the level of a control signal changes from high to low, the line impedance of the control signal is made equal to the line impedance of its reference potential, thereby reducing the parasitic capacitance of those lines. The main characteristic is to make the discharge time constant of the electric charge charged equal to the above and to guarantee the potential relation between these lines.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An application range of the present invention is not limited to an inverter control device, but one embodiment will be described with reference to FIG. 1 showing an application example to an inverter control device. FIG.
Since the basic operations of the inverter control device shown in FIG. 4 and the inverter control device of FIG. 4 described above do not change, the lower arm circuit is omitted in FIG. In the description of the embodiments, the description of the overlapping parts will be omitted.

A hybrid integrated circuit (20) according to the present invention comprises a transistor Q0 having a collector and an emitter connected between a control signal VS and a reference potential thereof, and a resistor R connected in parallel to a base and an emitter of the transistor Q0.
3, and a capacitor C3 having one end connected to the base of the transistor Q0 is newly provided in the conventional hybrid integrated circuit. The capacitance C3 will be described in detail in the description of the structure of the hybrid integrated circuit (20).

In the circuit of FIG. 1, the PC board (1
When the control signal VS supplied from 0) goes high with respect to the reference potential VN, the transistor Q1 is turned on, and the driver circuit Hi of the upper arm is driven. At this time, the high-level control signal VS charges the line capacitance C1 formed by the control signal line (36) and the internal wiring capacitance C2 of the hybrid integrated circuit (20). Although not shown, the midpoint potential VN is charged to the wiring capacitance of the corresponding line (36), and is also charged to the capacitance C3 via the resistor R3.

Next, at a predetermined timing, the reference potential VN
When the control signal VS changes to a low level and the reference potential VN decreases, the emitter potential of the transistor Q0 decreases. Then, the transistor Q0 is turned on by the charging voltage of the capacitor C3, and the control signal VS and the reference potential V
N decreases with the same time constant with the difference of only the collector-emitter saturation voltage of the transistor Q0. Accordingly, the voltage input between the base and the emitter of the transistor Q1 has a low value that turns off the transistor Q1, and is divided by the resistors R1 and R2 to sufficiently turn off the transistor Q1.

Next, the structure of the hybrid integrated circuit (20) of the present invention will be described with reference to FIGS. FIG. 3 is a sectional view taken along line II of FIG. The hybrid integrated circuit (2) of the present invention
A metal substrate (22) of anodized aluminum or the like is used as the substrate of (0), and a copper foil is adhered to the metal substrate (22) using an insulating adhesive (24). An external lead pad (28), a die bond pad (30), a wire bonding pad (32), or a conductive path (34) is formed in a predetermined shape by, for example, photo-etching a copper foil.

The chip resistors R1 and R2 are fixed to predetermined pads by soldering, and the transistors Q0 and Q1 are fixed by using a brazing material such as Al / Si eutectic or solder. For the transistor Q0 of the embodiment, a composite element in which the resistor R3 of FIG. 1 is internally formed is used. The capacitance C3 is determined by conducting a conductive path (34) or a pad (28) by photo-etching a copper foil.
(30) At the same time as forming (32), the control signal line VS is formed in an arbitrary shape with a copper foil to have a size corresponding to the parasitic capacitance of the control signal line VS, and a capacitance C3 is formed between the control signal line VS and the metal substrate (22). However, the capacitance C3 may be a single capacitance such as a chip capacitor. In this case, the capacitance C3 is connected between the base of the transistor Q0 and the metal substrate (22). As described above, an embodiment of the present invention has been described using an inverter control device as an example. However, the present invention is not limited to the embodiment, and can be widely applied to a hybrid integrated circuit having a reference potential circuit other than the ground potential. It is also noted that the method is effective as a countermeasure against the capacitance parasitic on the wiring inside the hybrid integrated circuit.

[0015]

As described above, according to the present invention, at the timing when the level of the control signal changes from high to low, the line impedance of the control signal is made equal to the line impedance of the reference potential.
Since the discharge time constants of the charges charged to the parasitic capacitances of the lines are equalized and the potential relationship between the lines is guaranteed, malfunction, power consumption, element destruction, and the like are avoided. According to the embodiment in which the capacitance is formed simultaneously with the formation of the conductive path by photo-etching the copper foil, there is an advantage that the number of components is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an inverter control device for explaining the present invention.

FIG. 2 is a plan view of a main part of one embodiment of the present invention.

FIG. 3 is a sectional view taken along line II of FIG. 2;

FIG. 4 is a circuit block diagram of an inverter control device for explaining a conventional hybrid integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 PC board 20 Hybrid integrated circuit 22 Metal substrate 24 Insulating adhesive 28 External lead pad 30 Die bond pad 32 Wire bonding pad 34 Conductive path

Claims (5)

(57) [Claims] A transistor having a base connected to one end of a capacitor and having a resistor connected in parallel between the base and the emitter is provided on a conductive path of the integrated circuit substrate, and the potential of the conductive path to which a control signal is input decreases. Wherein the potential of a conductive path to which a control signal is input by the transistor is used as the reference potential. 2. The input circuit for a hybrid integrated circuit according to claim 1, wherein an insulating metal substrate is used as said integrated circuit substrate. 3. The input circuit of a hybrid integrated circuit according to claim 1, wherein said capacitor is formed by the same material and by the same process as the conductive path. 4. The input circuit of a hybrid integrated circuit according to claim 1, wherein said hybrid integrated circuit is an output circuit of an inverter control device. 5. The input circuit according to claim 1, wherein a composite element is used as the transistor and the resistor.