JPH0498859A - Chip case of semiconductor integrated circuit - Google Patents

Chip case of semiconductor integrated circuit

Info

Publication number
JPH0498859A
JPH0498859A JP2216795A JP21679590A JPH0498859A JP H0498859 A JPH0498859 A JP H0498859A JP 2216795 A JP2216795 A JP 2216795A JP 21679590 A JP21679590 A JP 21679590A JP H0498859 A JPH0498859 A JP H0498859A
Authority
JP
Japan
Prior art keywords
wiring
case
printed board
chip case
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2216795A
Other languages
Japanese (ja)
Inventor
Tatsuya Ogasawara
達也 小笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2216795A priority Critical patent/JPH0498859A/en
Publication of JPH0498859A publication Critical patent/JPH0498859A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent through-holes or pads from affecting the wiring of a printed board by a method wherein case leads connected to an unused external input-output terminal inside a chip case are electrically connected together to serve as a board wiring at the mounting of a chip main body on the printed board. CONSTITUTION:Case leads 2a and 2b connected to an unused external input- output terminals which are not connected to a semiconductor substrate 3 inside a chip case are electrically connected together. That is, the case leads 2a and 2b connected to an unused external input-output terminal 7 on a printed board inside an integrated chip case are electrically connected together with a bonding wire 5, one end of a wiring pattern 8 on the printed board is connected to an unused external terminal 7a, and the other end is connected to an unused external terminal 7b, whereby the wiring pattern 8 can be connected through the shortest route and made to serve as the wiring of the printed board. By this setup, a partial channel neck can be relaxed, the number of layers of a board is lessened as much as possible, and such a printed board can be realized at a low cost.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は大規模集積回路のチップケースの構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a chip case for a large-scale integrated circuit.

〔従来の技術〕[Conventional technology]

従来、この種の大規模集積回路のチップケースにおける
未使用の外部入力端子は、チップの補強用電源丈たはグ
ランドとして使用するか、あるいは電気的に未接続とな
っていた。このようなチップケースを実装するプリント
基板においては、第２図（ｂ）に示すように、未使用外
部端子１７ａ。Conventionally, unused external input terminals in the chip case of this type of large-scale integrated circuit have been used as a power source for reinforcing the chip or as a ground, or have been left electrically unconnected. In the printed circuit board on which such a chip case is mounted, as shown in FIG. 2(b), there are unused external terminals 17a.

１７ｂ間は直接に接続せず、迂回させた配線パターン１
８によって接続していた。Wiring pattern 1 where 17b is not connected directly but is detoured.
It was connected by 8.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の大規模集積回路のチップケースでは、プ
リント基板上に実装する時、たとえ未使用の外部端子で
も、スルーホールあるいはパッドを設けなければならな
いため、そのスルーホールやパッドがプリント基板上の
配線に影響を与えてしまう欠点がある。In the conventional large-scale integrated circuit chip cases mentioned above, when mounting on a printed circuit board, through holes or pads must be provided even for unused external terminals; There is a drawback that it affects the wiring.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路のチップケースは、チップケー
ス本体の内部にて使用しない外部入出力端子とつながる
ケースリード間を電気的に接続し、前記チップケース本
体のプリント基板への実装時にプリント基板配線として
用いるようにしたことを特徴とする特 〔実施例〕 次に、本発明について図面を参照して説明する。The chip case of the semiconductor integrated circuit of the present invention electrically connects the case leads connected to external input/output terminals that are not used inside the chip case body, and the printed circuit board wiring when the chip case body is mounted on the printed circuit board. [Embodiment] Next, the present invention will be described with reference to the drawings.

第１図は本発明の一実施例の斜視図、第２図（ａ）は本
実施例のチップケースを７リント基板上に搭載した時の
配線図である。FIG. 1 is a perspective view of one embodiment of the present invention, and FIG. 2(a) is a wiring diagram when the chip case of this embodiment is mounted on a 7-lint board.

本実施例は集積回路チップケース１の内部にて半導体基
板（チップ）３とは接続しない未使用の外部入出力端子
とつながらケースリード２ａ、２ｂ間を電気的に接続し
てなっている。In this embodiment, inside an integrated circuit chip case 1, case leads 2a and 2b are electrically connected to unused external input/output terminals that are not connected to a semiconductor substrate (chip) 3.

即ち、プリント基板上の未使用外部端子７につながる集
積回路チップケース１内の、ケースリード２ａ、２ｂ間
をボンディングワイヤ５で接続し、プリント基板上の配
線パターン８の一方を未使用外部端子７ａに、もう一方
を７ｂにそれぞれ接続することにより、配線パターン８
の最短接続ができ、かつこれをプリント基板配線に利用
することによって集積回路周辺の部分的配線集中を緩和
することが可能となる。That is, case leads 2a and 2b in the integrated circuit chip case 1 connected to an unused external terminal 7 on the printed circuit board are connected by a bonding wire 5, and one of the wiring patterns 8 on the printed circuit board is connected to the unused external terminal 7a. By connecting the other end to 7b, the wiring pattern 8
By using this connection for printed circuit board wiring, it is possible to alleviate the local concentration of wiring around the integrated circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、大規模集Ｗｔ回路のチッ
プケース内部で、未使用外部端子間を接続し、その外部
端子をプリント基板上での配線に利用することにより、
部分的チャネルネックを緩和でき、基板層数を出来る限
り抑え、安価なプリント基板を実現出来る効果がある。As explained above, the present invention connects unused external terminals inside the chip case of a large-scale integrated Wt circuit, and uses the external terminals for wiring on a printed circuit board.
Partial channel necks can be alleviated, the number of board layers can be kept to a minimum, and an inexpensive printed circuit board can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の斜視図、第２図（ａ）は本
実施例の集積回路チップケースをプリント基板上に搭載
した時の配線図、第２図＜ｂ）は従来のチップケースを
搭載した時の配線図である。Fig. 1 is a perspective view of one embodiment of the present invention, Fig. 2(a) is a wiring diagram when the integrated circuit chip case of this embodiment is mounted on a printed circuit board, and Fig. 2<b) is a wiring diagram of the conventional integrated circuit chip case. It is a wiring diagram when a chip case is mounted.

Claims (1)

【特許請求の範囲】[Claims] 　チップケース本体の内部にて使用しない外部入出力端
子とつながるケースリード間を電気的に接続し、前記チ
ップケース本体のプリント基板への実装時にプリント基
板配線として用いるようにしたことを特徴とする半導体
集積回路のチップケース。A semiconductor characterized in that case leads connected to unused external input/output terminals inside a chip case body are electrically connected and used as printed circuit board wiring when the chip case body is mounted on a printed circuit board. Integrated circuit chip case.
JP2216795A 1990-08-17 1990-08-17 Chip case of semiconductor integrated circuit Pending JPH0498859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2216795A JPH0498859A (en) 1990-08-17 1990-08-17 Chip case of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2216795A JPH0498859A (en) 1990-08-17 1990-08-17 Chip case of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0498859A true JPH0498859A (en) 1992-03-31

Family

ID=16693999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2216795A Pending JPH0498859A (en) 1990-08-17 1990-08-17 Chip case of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0498859A (en)

Similar Documents

Publication Publication Date Title
JPH05160290A (en) Circuit module
JPH0740790B2 (en) High power power module
JPH0498859A (en) Chip case of semiconductor integrated circuit
JPS6257258B2 (en)
JP2662156B2 (en) Noise reduction device for integrated circuits
JPS5980957A (en) Semiconductor device
JPS6022348A (en) Semiconductor device
JPS63258053A (en) Fet bias circuit
JPH01205457A (en) Systematized semiconductor device
JPH0222886A (en) Hybrid integrated circuit
JPH01114003A (en) Resistor chip
JPH01316948A (en) Semiconductor integrated circuit
JPS6380543A (en) Integrated circuit device
JPH05190674A (en) Semiconductor integrated circuit device
JPS62168657U (en)
JPH02239577A (en) Hybrid integrated circuit for surface mounting
JPH03261079A (en) Hybrid integrated circuit
JPH10270648A (en) Semiconductor package
JPH1098137A (en) Switching noise-reducing package
JPH1187909A (en) Ic connecting apparatus and auxiliary board for connecting ic
JPH04144270A (en) Integrated circuit case
JPH1012660A (en) Integrated circuit for surface mounting
JPH04101452A (en) Semiconductor package
JPH03192756A (en) Hybrid integrated circuit
JPS59143355A (en) Semiconductor integrated circuit device