JPH10270648A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH10270648A JPH10270648A JP9091608A JP9160897A JPH10270648A JP H10270648 A JPH10270648 A JP H10270648A JP 9091608 A JP9091608 A JP 9091608A JP 9160897 A JP9160897 A JP 9160897A JP H10270648 A JPH10270648 A JP H10270648A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- semiconductor package
- pads
- power supply
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケージ
に関し、特に入力側伝送路との整合を図った半導体パッ
ケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a semiconductor package that is matched with an input side transmission line.
【０００２】[0002]
【従来の技術】従来、分布定数回路として扱われる高周
波用の送受信回路が形成された半導体パッケージには、
伝送路との整合を図るため終端抵抗が形成されている。
この終端抵抗を内蔵する集積回路を有する半導体パッケ
ージの従来例が特開平１ー１５８７６２号及び特開昭６
２ー１７６１５３号公報に開示されている。2. Description of the Related Art Conventionally, a semiconductor package formed with a high frequency transmitter / receiver circuit treated as a distributed constant circuit is
A terminating resistor is formed to match with the transmission line.
Conventional examples of a semiconductor package having an integrated circuit incorporating this terminating resistor are disclosed in Japanese Patent Application Laid-Open Nos.
It is disclosed in Japanese Patent Laid-Open No. 2-176153.
【０００３】特開平１ー１５８７６２号公報には、終端
抵抗を内蔵した集積回路において、複数の異なる終端抵
抗の一端が集積回路上の入力信号端子パターンと接続す
るように形成し、該当する終端抵抗の他端を択一的に外
部終端部に接続して最も近い最適な終端抵抗値を得る構
成が開示されている。Japanese Patent Application Laid-Open No. 1-158762 discloses that in an integrated circuit having a built-in terminating resistor, one end of a plurality of different terminating resistors is formed so as to be connected to an input signal terminal pattern on the integrated circuit. Is connected to an external terminal section to obtain the closest optimum terminal resistance value.
【０００４】また、特開昭６２ー１７６１５３号公報に
は、終端抵抗を内蔵した集積回路において、終端抵抗の
一端が集積回路上の入力信号端子パターンと接続する様
に形成し、終端抵抗の他端を外部終端部に接続して終端
抵抗値を得る構成が開示されている。Japanese Patent Application Laid-Open No. 62-176153 discloses an integrated circuit having a built-in terminating resistor, in which one end of the terminating resistor is formed so as to be connected to an input signal terminal pattern on the integrated circuit. A configuration is disclosed in which an end is connected to an external termination to obtain a termination resistance value.
【０００５】[0005]
【発明が解決しようとする課題】このように、従来、プ
リント基板に実装したＬＳＩパッケージに終端抵抗を付
ける場合には、リード端子の先端に終端抵抗を形成して
いた。しかしながら、かかる構造は、次のような問題を
有する。As described above, conventionally, when a terminating resistor is attached to an LSI package mounted on a printed board, the terminating resistor is formed at the tip of the lead terminal. However, such a structure has the following problems.
【０００６】例えば、特開昭６２ー１７６１５３号公報
に開示されている従来例の半導体パッケージを図５を参
照して説明すると、半導体パッケージ５上に形成された
外部信号端子リード６には、半導体チップ１に形成され
た終端抵抗４にワイヤボンダ３を介して接続されている
終端抵抗用パット９ａが接続され、終端抵抗４の他端９
ｂが外部信号リード端子６を介して外部電源に接続され
る。For example, a conventional semiconductor package disclosed in Japanese Unexamined Patent Publication No. 62-176153 will be described with reference to FIG. 5. The external signal terminal lead 6 formed on the semiconductor package 5 includes a semiconductor. A terminating resistor pad 9 a connected via a wire bonder 3 is connected to a terminating resistor 4 formed on the chip 1, and the other end 9 of the terminating resistor 4 is connected.
b is connected to an external power supply via the external signal lead terminal 6.
【０００７】かかる構成は、半導体パッケージの使用可
能な入出力信号リード端子は、入力信号端子の中で終端
抵抗が必要な本数だけ少なくなる。したがって、入力信
号端子パターンに対して、外部電源に接続する終端抵抗
用信号端子パターンが信号端子毎に必要なため、終端抵
抗を接続する入出力信号端子数分だけ入出力信号が使用
できないという問題がある。With such a configuration, the number of usable input / output signal lead terminals of the semiconductor package is reduced by the number of terminating resistors required among the input signal terminals. Therefore, a signal terminal pattern for a terminating resistor to be connected to an external power supply is required for each signal terminal with respect to the input signal terminal pattern. There is.
【０００８】[0008]
【課題を解決するための手段】前述の課題を解決するた
め、本発明による半導体パッケージは、半導体チップ上
に、複数の第１のパットと、終端用電源パターンが形成
され、半導体パッケージ上に、複数の外部信号リード端
子と、該外部信号リード端子に対応して形成され、両端
が第２のパットに接続された複数の終端抵抗と、前記終
端用電源パターンと接続された半導体パッケージ電源端
子とが形成され、所定の前記外部信号リード端子と前記
半導体チップ上の第１のパット間、前記第１と第２のパ
ット間、前記第２のパットと前記終端用電源パターン間
がワイヤボンダで接続されるとともに、前記複数の第１
のパット間が電気的に接続されて構成される。ここで、
前記複数の第１のパット間がアルミ配線またはワイヤボ
ンダで接続されている。In order to solve the above-mentioned problems, a semiconductor package according to the present invention has a plurality of first pads and a termination power supply pattern formed on a semiconductor chip. A plurality of external signal lead terminals, a plurality of terminal resistors formed corresponding to the external signal lead terminals, both ends of which are connected to the second pad, and a semiconductor package power terminal connected to the terminal power pattern. Are formed, and a predetermined bond between the external signal lead terminal and the first pad on the semiconductor chip, a connection between the first and second pads, and a connection between the second pad and the termination power supply pattern are connected by a wire bonder. And a plurality of the first
Are electrically connected to each other. here,
The plurality of first pads are connected by aluminum wiring or a wire bonder.
【０００９】本発明の他の態様による半導体パッケージ
は、片端が第１のパットに接続された終端抵抗と、外部
端子リードにボンデイングで接続された第２のパット間
の接続から成る外部端子リードグループの複数組と、該
複数組の外部端子リードのグループの複数の前記終端抵
抗の他端及び外部終端抵抗用電源端子とが接続された終
端抵抗用電源パターンを備えて構成される。According to another aspect of the present invention, there is provided a semiconductor package having an external terminal lead group including a terminating resistor having one end connected to a first pad and a connection between a second pad connected to external terminal leads by bonding. And a terminating resistor power supply pattern to which the other ends of the terminating resistors of the plurality of sets of external terminal leads and the external terminating resistor power supply terminals are connected.
【００１０】[0010]
【発明の実施の形態】次に本発明による半導体パッケー
ジの実施形態を図面を参照しながら説明する。図１は本
発明による半導体パッケージの一実施形態を示す図であ
る。図１において、半導体パッケージ５上に搭載された
半導体チップ１上には、アルミ配線８で互いに接続され
たパット２ａ、２ｂ及び終端用電源パターン７が形成さ
れ、半導体パッケージ５上には終端抵抗用パット９ａ、
９ｂ間に接続、形成された終端抵抗４、外部信号リード
端子６及び半導体パッケージ電源端子１０が形成されて
おり、所要により外部信号リード端子６とパット２ａ、
終端抵抗用パット９ａとパット２ｂ、終端抵抗用パット
９ｂと終端用電源パターン７、半導体パッケージ電源端
子１０と終端用電源パターン７とがワイヤボンダ３を介
して接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of a semiconductor package according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a semiconductor package according to the present invention. In FIG. 1, pads 2 a and 2 b and a termination power supply pattern 7 connected to each other by aluminum wiring 8 are formed on a semiconductor chip 1 mounted on a semiconductor package 5, and a termination resistor for termination resistance is formed on the semiconductor package 5. Pat 9a,
9b, a terminating resistor 4, an external signal lead terminal 6, and a semiconductor package power supply terminal 10 formed and connected between the external signal lead terminal 6 and the pad 2a, if necessary.
The termination resistor pads 9a and 2b, the termination resistor pad 9b and the termination power supply pattern 7, the semiconductor package power supply terminal 10 and the termination power supply pattern 7 are connected via the wire bonder 3.
【００１１】このように、半導体パッケージ５内におい
て、外部信号リード端子６に接続されるパット２ａの隣
りに、終端抵抗４にワイヤボンダ３でボンディングした
パット２ｂが構成され、図２の全体図に示すように、終
端抵抗４の接点をパットに接続、そのパットとチップが
ボンディングで接続され、反対側の接点をパットに接
続、そのパットと終端用電源をボンディングする。終端
用電源はリード端子に接続されており、外部から電源が
供給される。As described above, in the semiconductor package 5, the pad 2b bonded to the terminating resistor 4 by the wire bonder 3 is formed next to the pad 2a connected to the external signal lead terminal 6, as shown in the overall view of FIG. As described above, the contact of the terminating resistor 4 is connected to the pad, the pad and the chip are connected by bonding, the contact on the opposite side is connected to the pad, and the pad and the power supply for termination are bonded. The terminating power supply is connected to the lead terminals, and power is supplied from outside.
【００１２】終端抵抗が必要な外部信号リード端子６が
接続されているパット２ａと、隣の終端抵抗４が接続さ
れているパット２ｂはアルミ配線または外部回路で接続
される。A pad 2a to which an external signal lead terminal 6 requiring a terminating resistor is connected and a pad 2b to which an adjacent terminating resistor 4 is connected are connected by aluminum wiring or an external circuit.
【００１３】上述のように、本実施形態においては、半
導体パッケージ内に終端抵抗を内蔵し、終端抵抗用電源
パターンを半導体パッケージに供給している電源に接続
し、信号端子パターンと同数の終端抵抗を内蔵し、終端
抵抗が必要な入力信号パターンと接続しているので、プ
リント基板の実装部品が削減しパターン配線の自由度が
増す。As described above, in this embodiment, the terminating resistor is built in the semiconductor package, the power supply pattern for the terminating resistor is connected to the power supply supplied to the semiconductor package, and the same number of terminating resistors as the signal terminal patterns are provided. , Which is connected to an input signal pattern that requires a terminating resistor. This reduces the number of components mounted on the printed circuit board and increases the degree of freedom in pattern wiring.
【００１４】図２には、図１に示す実施形態の全体構成
図が示されている。半導体パッケージ５に搭載された半
導体チップ１上には、多数のパット２が形成されてい
る。半導体パッケージ５の周辺には多数の外部信号リー
ド端子６が形成されるとともに、半導体チップの外周部
には外部信号リード端子６と同数の終端抵抗４が形成さ
れ、外部信号リード端子６とパット２間はワイヤボンダ
３でボンデイングされている。FIG. 2 shows an overall block diagram of the embodiment shown in FIG. A large number of pads 2 are formed on the semiconductor chip 1 mounted on the semiconductor package 5. A large number of external signal lead terminals 6 are formed around the semiconductor package 5, and the same number of terminating resistors 4 as the external signal lead terminals 6 are formed on the outer peripheral portion of the semiconductor chip. The gap is bonded by a wire bonder 3.
【００１５】図３には、図２の点線部の拡大構成図が示
されている。図３に示すように、半導体チップ１のパッ
ト２間の接続はアルミ配線８により為され、終端抵抗４
は終端抵抗用パット９間に接続され、ワイヤボンダ３に
より外部信号リード端子６とパット２間が接続されてい
る。FIG. 3 shows an enlarged configuration diagram of a dotted line portion in FIG. As shown in FIG. 3, the connection between the pads 2 of the semiconductor chip 1 is made by the aluminum wiring 8, and the terminating resistor 4
Is connected between the terminating resistor pads 9, and the external signal lead terminal 6 and the pad 2 are connected by the wire bonder 3.
【００１６】図４は、本発明による半導体パッケージの
他の実施形態を示す図であり、図１に示す実施形態と基
本構成は同じであるが、半導体チップ１上に形成されて
いるパット２ａ、２ｂ間がアルミ配線８ではなく、ワイ
ヤボンダ３により接続されている。FIG. 4 is a view showing another embodiment of the semiconductor package according to the present invention. The basic configuration is the same as that of the embodiment shown in FIG. 2b is connected by the wire bonder 3 instead of the aluminum wiring 8.
【００１７】[0017]
【発明の効果】以上説明したように、本発明の半導体パ
ッケージによれば、終端抵抗用電源パターンを半導体パ
ッケージ電源と接続し、外部信号リード端子と共有し、
入力信号端子パターンと同数の内蔵終端抵抗と接続して
いるので、全て信号端子として使用できることになり、
入出力信号端子を有効に活用でき、回路の小型化、コス
ト低減面でも有益である。As described above, according to the semiconductor package of the present invention, the power supply pattern for the termination resistor is connected to the semiconductor package power supply and shared with the external signal lead terminal,
Since it is connected to the same number of built-in terminating resistors as the input signal terminal pattern, all can be used as signal terminals,
The input / output signal terminals can be used effectively, which is also beneficial in terms of circuit size reduction and cost reduction.
【図１】本発明による半導体パッケージの一実施形態を
示す半導体パッケージを示す図である。FIG. 1 is a diagram showing a semiconductor package showing an embodiment of a semiconductor package according to the present invention.
【図２】図１に示す実施形態の全体構成図である。2 is an overall configuration diagram of the embodiment shown in FIG. 1. FIG.
【図３】図３の点線部の拡大図である。FIG. 3 is an enlarged view of a dotted line portion in FIG.
【図４】本発明による半導体パッケージの他の実施形態
を示す半導体パッケージを示す図である。FIG. 4 is a view showing a semiconductor package showing another embodiment of the semiconductor package according to the present invention.
【図５】従来の半導体パッケージの半導体パッケージの
原理図である。FIG. 5 is a principle diagram of a semiconductor package of a conventional semiconductor package.
１ 半導体チップ ２、２ａ、２ｂ パット ３ ワイヤボンダ ４ 終端抵抗 ５ 半導体パッケージ ６ 外部信号リード端子 ７ 終端用電源パターン ８ アルミ配線 ９ 終端抵抗用パット １０ 半導体パッケージ電源端子 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2, 2a, 2b pad 3 Wire bonder 4 Termination resistor 5 Semiconductor package 6 External signal lead terminal 7 Termination power supply pattern 8 Aluminum wiring 9 Termination resistor pad 10 Semiconductor package power supply terminal
Claims (4)
と、終端用電源パターンが形成され、 半導体パッケージ上に、複数の外部信号リード端子と、
該外部信号リード端子に対応して形成され、両端が第２
のパットに接続された複数の終端抵抗と、前記終端用電
源パターンと接続された半導体パッケージ電源端子とが
形成され、 所定の前記外部信号リード端子と前記半導体チップ上の
第１のパット間、前記第１と第２のパット間、前記第２
のパットと前記終端用電源パターン間がワイヤボンダで
接続されるとともに、前記複数の第１のパット間が電気
的に接続されて成ることを特徴とする半導体パッケー
ジ。1. A plurality of first pads and a power supply pattern for termination are formed on a semiconductor chip, and a plurality of external signal lead terminals are formed on a semiconductor package.
It is formed corresponding to the external signal lead terminal.
A plurality of terminating resistors connected to the pad, and a semiconductor package power terminal connected to the terminating power supply pattern; a predetermined external signal lead terminal and a first pad on the semiconductor chip; Between the first and second pads, the second
And a plurality of first pads are electrically connected to each other by a wire bonder between the pads and the terminating power supply pattern.
接続されている請求項１に記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein the plurality of first pads are connected by aluminum wiring.
で接続されている請求項１に記載の半導体パッケージ。3. The semiconductor package according to claim 1, wherein the plurality of first pads are connected by a wire bonder.
と、外部端子リードにボンデイングで接続された第２の
パット間の接続から成る外部端子リードグループの複数
組と、該複数組の外部端子リードのグループの複数の前
記終端抵抗の他端及び外部終端抵抗用電源端子とが接続
された終端抵抗用電源パターンを備えて成ることを特徴
とする半導体パッケージ。4. A plurality of sets of external terminal lead groups each comprising a terminating resistor having one end connected to the first pad and a connection between second pads connected to the external terminal lead by bonding, and a plurality of sets of the plurality of external terminal lead groups. A semiconductor package comprising a termination resistance power supply pattern in which the other ends of the plurality of termination resistances of the group of external terminal leads and an external termination resistance power supply terminal are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9091608A JPH10270648A (en) | 1997-03-26 | 1997-03-26 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9091608A JPH10270648A (en) | 1997-03-26 | 1997-03-26 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10270648A true JPH10270648A (en) | 1998-10-09 |
Family
ID=14031296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9091608A Pending JPH10270648A (en) | 1997-03-26 | 1997-03-26 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10270648A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11437351B2 (en) | 2020-09-09 | 2022-09-06 | Kioxia Corporation | Semiconductor device |
-
1997
- 1997-03-26 JP JP9091608A patent/JPH10270648A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11437351B2 (en) | 2020-09-09 | 2022-09-06 | Kioxia Corporation | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5789816A (en) | Multiple-chip integrated circuit package including a dummy chip | |
| KR970030750A (en) | Semiconductor device and electronic device using same | |
| JPS616846A (en) | Plug-in package with capacitor | |
| JPH10270648A (en) | Semiconductor package | |
| US6509628B2 (en) | IC chip | |
| JP3597830B2 (en) | Electronic circuit device, electronic device package, and transmission line termination method | |
| JP2570584B2 (en) | Semiconductor device | |
| JPH01132150A (en) | Carrier substrate of semiconductor chip | |
| JPH06177322A (en) | Memory element | |
| JPH05343525A (en) | Semiconductor integrated circuit | |
| JPH0697666A (en) | Electronic device | |
| JP2677087B2 (en) | Semiconductor integrated circuit | |
| JPH1098137A (en) | Switching noise-reducing package | |
| JPH1012660A (en) | Integrated circuit for surface mounting | |
| JPH0964232A (en) | Ceramic package | |
| JP2502994Y2 (en) | Semiconductor integrated circuit device | |
| JPH1070158A (en) | Tab-mounting semiconductor device | |
| JPH04165601A (en) | Electronic device | |
| JPH0786446A (en) | Ic package | |
| JPH01114003A (en) | Resistor chip | |
| JPH07114217B2 (en) | Tape carrier type semiconductor device | |
| JPH08203712A (en) | Terminating device | |
| JPH0593046U (en) | Chip module with resistor array | |
| JPS62196854A (en) | Semiconductor device | |
| JPH0498859A (en) | Chip case of semiconductor integrated circuit |