JPH04144270A - Integrated circuit case - Google Patents

Integrated circuit case

Info

Publication number
JPH04144270A
JPH04144270A JP2269005A JP26900590A JPH04144270A JP H04144270 A JPH04144270 A JP H04144270A JP 2269005 A JP2269005 A JP 2269005A JP 26900590 A JP26900590 A JP 26900590A JP H04144270 A JPH04144270 A JP H04144270A
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
conductor
circuit case
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2269005A
Other languages
Japanese (ja)
Inventor
Omihiro Mano
眞野　臣弘
Masanobu Sano
佐野　昌宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP2269005A priority Critical patent/JPH04144270A/en
Publication of JPH04144270A publication Critical patent/JPH04144270A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To make possible a reduction in the size of printed boards and to contrive the improvement of a packaging efficiency by a method wherein a plurality of integrated circuits are built in an integrated circuit case via a heat conductor. CONSTITUTION:Wiring patterns 5, which are connected with external connecting terminals 3 and consist of a conductor, are attracted in combination to an insulating substrate 4 and one end of each pattern 5 is connected with each IC connecting terminal 6 provided on an IC chip 1 via each connection conductor 7. The title case has caps 8 for protecting the IC chip and the like. That is, the paths of electrical signals pass through the conductors 7 from the terminals 3 through the patterns 5 and are inputted in the chip 1 from the terminals 6 or are outputted from the chip 1. As the case is an integrated circuit case of a structure, in which these patterns 5 are integrally formed as one pair (two groups) via a conductor 2, function corresponding to two times that of a conventional integrated circuit case are built in within a same packaging are and the packaging efficiency also approximates to two times.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路ケースに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to integrated circuit cases.

〔従来の技術〕[Conventional technology]

従来の集積回路ケースは、論理回路等より成る１個のＩ
Ｃチップを内蔵しており、１枚のプリント配線基板に平
面的に複数個実装される。A conventional integrated circuit case consists of a single integrated circuit consisting of a logic circuit, etc.
It has a built-in C chip, and multiple pieces are mounted flat on a single printed wiring board.

しかしプリント配線基板の大きさに限度があるため、さ
らに多数の集積回路ケースを実装する場合、プリント配
線基板の両方の面にも実装していた。However, since there is a limit to the size of a printed wiring board, when mounting a larger number of integrated circuit cases, they must be mounted on both sides of the printed wiring board.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の集積回路ケースには、１個のＩＣチップ
が内蔵されており、実装するプリント配線基板の大きさ
によって実装する数量に限度がある。The conventional integrated circuit case described above has one IC chip built-in, and there is a limit to the number of IC chips that can be mounted depending on the size of the printed wiring board on which it is mounted.

このため平面的にプリント配線基板の両面に実装する方
法が最大限となる。Therefore, the method of mounting on both sides of the printed wiring board in a two-dimensional manner is the best method.

従って多機能な装置を製作する際より多くの集積回路ケ
ースを実装するが、たとえ１個でも集積回路ケースの数
がオーバーした場合、実装するプリント配線基板の数を
増やす必要がある。Therefore, when manufacturing a multifunctional device, more integrated circuit cases are mounted, but if the number of integrated circuit cases exceeds even one, it is necessary to increase the number of printed wiring boards to be mounted.

これにより製造コストが高価となるばかりか実装するス
ペースも増大し装置が大型化する欠点があった。This not only increases the manufacturing cost but also increases the mounting space, resulting in an increase in the size of the device.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の集積回路ケースは、導体を介して集積回路と絶
縁基板とこの絶縁基板に合着され一端を信号入出力用外
部端子と他端を集積回路の接続端子と接続する配線パタ
ーンと、前記集積回路を保護するキャップとを含んで構
成される。The integrated circuit case of the present invention includes an integrated circuit, an insulating substrate, a wiring pattern bonded to the insulating substrate via a conductor, and connecting one end to an external terminal for signal input/output and the other end to a connecting terminal of the integrated circuit; and a cap that protects the integrated circuit.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して詳細に説明
する。Next, embodiments of the present invention will be described in detail with reference to the drawings.

第１図は本発明の一実施例を示す断面図である。　第１
図に示す集積回路ケースは、論理回路等の集積回路より
成るＩＣチップ１が熱伝導の良い導体、２を介して複数
個（第１図では２個）止着されているため複数倍の機能
を有することに相当する。　一方、外部との信号の送受
を行うための外部接続端子３は、これらを固定保持する
絶縁基板４の周囲に必要数備え付いている。FIG. 1 is a sectional view showing one embodiment of the present invention. 1st
The integrated circuit case shown in the figure has multiple IC chips 1 (two in Figure 1), each consisting of an integrated circuit such as a logic circuit, attached via a conductor 2 with good thermal conductivity, so it has multiple functions. This corresponds to having . On the other hand, a necessary number of external connection terminals 3 for transmitting and receiving signals with the outside are provided around an insulating substrate 4 that fixes and holds these terminals.

この外部接続端子３と接続される伝導体よりなる配線パ
ターン５は絶縁基板４に合着されておりこの配線パター
ン５の一端は、前記ＩＣチップ１に備え付いているＩＣ
接続端子６と接続線７により接続されている。A wiring pattern 5 made of a conductor to be connected to the external connection terminal 3 is bonded to an insulating substrate 4, and one end of this wiring pattern 5 connects to an IC mounted on the IC chip 1.
It is connected by a connecting terminal 6 and a connecting wire 7.

また、ＩＣチップ等の保護のためキャップ８を有してい
る。It also has a cap 8 to protect the IC chip and the like.

すなわち、電気信号の経路は、外部接続端子３から配線
パターン５を通じて接続線７を通り、ＩＣ接続端子６か
らＩＣチップ１に入出力される。That is, the path of the electrical signal is from the external connection terminal 3 through the wiring pattern 5, through the connection line 7, and input/output from the IC connection terminal 6 to the IC chip 1.

第１図はこれらが導体２を介して一対（２組）として一
体化された集積回路ケースであるため、同一実装面積の
中に２倍に相当する機能を内蔵したことにより実装効率
も２倍近くなる。Figure 1 shows an integrated circuit case in which these are integrated as a pair (two sets) via the conductor 2, so the mounting efficiency is doubled because the functions equivalent to twice as many are built into the same mounting area. It gets closer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、熱伝導体を介して複数の
集積回路を集積回路ケースに内蔵しているため、実装す
るプリント基板の削減を可能とし、実装効率の改善が図
れるので、低価格、小型な装置を提供できる。As explained above, the present invention incorporates a plurality of integrated circuits into an integrated circuit case via thermal conductors, so it is possible to reduce the number of printed circuit boards to be mounted and improve mounting efficiency, resulting in a low cost. , a small device can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す断面図である。 １・・・ＩＣチップ、２・・・導体、３・・・外部接続
端子、４・・・絶縁基板、５・・・配線パターン、６・
・・ＩＣ接続端子、 ７・・・接続線、 ８・・・キャップ。FIG. 1 is a sectional view showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... IC chip, 2... Conductor, 3... External connection terminal, 4... Insulating board, 5... Wiring pattern, 6...
...IC connection terminal, 7...connection wire, 8...cap.

Claims (1)

【特許請求の範囲】[Claims] 　導体を介して集積回路と絶縁基板と該絶縁基板に合着
され一端を信号入出力用外部端子と他端を集積回路の接
続端子と接続する配線パターンと、前記集積回路を保護
するキャップとを含むことを特徴とする集積回路ケース
。An integrated circuit, an insulating substrate, a wiring pattern bonded to the insulating substrate through a conductor and connecting one end to an external terminal for signal input/output and the other end to a connecting terminal of the integrated circuit, and a cap for protecting the integrated circuit. An integrated circuit case comprising:
JP2269005A 1990-10-05 1990-10-05 Integrated circuit case Pending JPH04144270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2269005A JPH04144270A (en) 1990-10-05 1990-10-05 Integrated circuit case

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2269005A JPH04144270A (en) 1990-10-05 1990-10-05 Integrated circuit case

Publications (1)

Publication Number Publication Date
JPH04144270A true JPH04144270A (en) 1992-05-18

Family

ID=17466343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2269005A Pending JPH04144270A (en) 1990-10-05 1990-10-05 Integrated circuit case

Country Status (1)

Country Link
JP (1) JPH04144270A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100225236B1 (en) * 1996-12-06 1999-10-15 마이클 디. 오브라이언 Bga semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100225236B1 (en) * 1996-12-06 1999-10-15 마이클 디. 오브라이언 Bga semiconductor package

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