JP4543755B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an element arrangement structure of a semiconductor integrated circuit used in a memory system.

  As a semiconductor device, a system LSI in which a plurality of semiconductor elements are integrated on a circuit board to achieve high integration and high performance as a one-chip IC is a current mainstream product. Some of these single-chip semiconductor devices function as a memory system in which a processor for performing arithmetic processing and the like and a memory for data access by the processor are integrated, and a plurality of memories are mounted. Further, a wiring pattern (bus signal wiring) for electrically connecting each element arranged on the semiconductor device is formed on the semiconductor device.

  FIG. 16 shows a configuration example on a mounting substrate of a semiconductor integrated circuit (LSI) used as a conventional memory system. Reference numeral 102 denotes a processor that performs arithmetic processing of the memory system, and reference numerals 103 and 104 denote memories to which the processor 102 accesses data. Reference numeral 127 denotes a data signal line that connects the processor 102 and the memory 103, 128 denotes an address signal line that connects the processor 102 and the memory 103, and 129 denotes a control signal line that connects the processor 102 and the memory 103. The processor 102 transmits a control signal indicating that data writing to the memory 103 or data reading from the memory 103 is performed via the control signal line 129 to the memory 103, and in the memory 103 via the address signal line 128. The data corresponding to the designated address is acquired via the data signal line 127, or the data to be transmitted via the data signal line 127 is written to the designated address. The data signal line 127 is represented by a single signal line. For example, in the case of a 16-bit LSI memory system, 16 data signal lines are formed, and a 32-bit LSI memory system. Then, it is formed by 32 data signal lines. The connection between the processor 102 and the memory 104 is the same as the connection between the processor 102 and the memory 103 described above.

  In this memory system, it is important to realize high performance of a semiconductor integrated circuit (LSI). The efficiency of each element on a semiconductor substrate for high integration of the semiconductor integrated circuit (LSI) is important. Mounting arrangement and shortening the wiring length of the signal line connecting the plurality of mounted elements. Further, in a memory system equipped with a plurality of memories, equal-length wiring is used to make the wiring lengths of signal lines connecting a plurality of memory elements and a semiconductor element such as a processor accessing the plurality of memory elements equal to each other. Is desirable.

In a semiconductor mounting substrate used in a conventional memory system, a method for reducing the mounting area and wiring length has been devised by making the mounting substrate shape special and stacking memory devices. (For example, refer to Patent Document 1). In addition, some memory devices themselves are special (see, for example, Patent Document 2).
JP 2000-124389 A JP 2003-168852 A

  In the semiconductor device disclosed in Patent Document 1, it is necessary to adopt a configuration in which memory elements are overlapped on a semiconductor substrate, which causes a problem that it is difficult to implement from the viewpoint of manufacturing and cost. In addition, the fact that equal-length wiring is not used for all memory elements is a factor that hinders high performance as an LSI.

  The semiconductor device disclosed in Patent Document 2 has memory elements arranged on both sides of a semiconductor substrate, and since it has a special structure, it is somewhat difficult to implement in terms of manufacturing and cost, but access to the memory. It can be said that it is excellent in realizing equal-length wiring of connection signal lines between the element that performs the above and a plurality of memory elements. However, the semiconductor device disclosed here is based on the premise of a structure in which a plurality of memory elements are arranged on both sides of the semiconductor substrate, and on the premise of a basic structure in which each element is arranged on one side of the semiconductor substrate. Therefore, the invention disclosed in Patent Document 2 cannot be utilized.

  The present invention is based on the basic structure of a semiconductor device, which is a semiconductor integrated circuit having a memory access element such as a processor and a plurality of memory elements on the premise of each semiconductor element being arranged on one side of a semiconductor substrate. High integration, shortening of wiring of signal lines connecting them, and equal length wiring of signal lines connected to each of a plurality of memory elements from a memory access element are realized.

Specifically, the semiconductor device includes a first and second memory elements having a quadrangular structure on the same surface of a semiconductor substrate, and a semiconductor element having a quadrangular structure accessible to the first and second memory elements. The first memory element is arranged in parallel with the first side of the semiconductor element, and the second side is in parallel with the second side adjacent to the first side of the semiconductor element. And a part of the first memory element is sandwiched between parallel lines of the second side of the semiconductor element and the side of the second memory element facing the second side of the semiconductor element. And a part of the second memory element is sandwiched between parallel lines of the first side of the semiconductor element and the side of the first memory element facing the first side of the semiconductor element. It arranged in the region, the said semiconductor substrate The first, second, third, and fourth memories further include third and fourth memory elements that can be accessed by the semiconductor element on a surface different from a surface on which the conductor element is disposed. The elements have the same shape, and the first memory element and the third memory element are overlapped with each other across the semiconductor substrate, and the second memory element and the fourth memory element Means that the entirety overlaps with the semiconductor substrate in between .

  Furthermore, by applying the basic structure of the present invention described above, by using both sides of the semiconductor substrate, an element for accessing the memory and a plurality of memory elements are arranged, thereby realizing higher integration and higher performance. ing.

  The present invention makes it possible to obtain a degree of freedom in size of the semiconductor device itself, and is effective in developing a variety of semiconductor devices from the viewpoint of design reuse. In a device that performs memory access and a semiconductor mounting board on which multiple memory devices are mounted, the connection wiring length can be reduced without requiring a special mechanism, and the mounting area can be reduced, and memory access can be performed. It is possible to realize equal-length wiring from the element that performs the above to a plurality of memory elements. In addition, wiring pattern routing is greatly reduced, which eliminates signal reflection, transmission loss, crosstalk noise, etc., making it extremely advantageous for high-speed operation and reducing the number of board layers. Become.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a semiconductor integrated circuit according to a first embodiment of the present invention. Reference numeral 101 denotes a semiconductor substrate on which a plurality of elements are integrated. On the semiconductor substrate 101, a processor 102 that executes arithmetic processing and the like, a memory 103 that allows the processor 102 to access data and execute data storage or acquisition, and 104 is provided. These processor 102 and memories 103 and 104 have a three-dimensional shape based on a substantially square shape. Examples of these include a three-dimensional shape with a square or rectangle as the bottom, and the same applies to other memories in the following embodiments.

  The semiconductor integrated circuit shown in FIG. 1 is characterized in that one side of the memories 103 and 104 is arranged in parallel on one side of the processor 102 and the other side adjacent to the side. is there. As a result, the wiring lengths of the signal lines connected from the processor 102 to the memories 103 and 104 can be equalized, and equal length wiring to the memory can be realized. This is the same as the semiconductor integrated circuit of FIG. 16 shown in the prior art.

  In the semiconductor integrated circuit shown in FIG. 1, a feature different from the prior art is that a part of the memory 103 is arranged in a parallel region (region indicated by a broken line) between the processor 102 and the memory 104. That is, a part of 104 is arranged in a parallel area (area indicated by a broken line) sandwiched between the processor 102 and the memory 103. With this arrangement, it is possible to increase the integration degree of the elements arranged on the semiconductor substrate, while making the wiring lengths of the connection signal lines from the processor 102 to the memories 103 and 104 equal.

  In order to explain the effect of improving the degree of integration by the element arrangement of the present invention, the difference will be described with reference to FIGS. FIG. 2 shows an element arrangement state of a semiconductor integrated circuit to which the element arrangement according to the present invention is applied, and FIG. 17 shows an application example of the element arrangement of the semiconductor integrated circuit based on the prior art. 2 and 17 both show a semiconductor integrated circuit when a plurality of memories are arranged around the processor.

  In FIG. 17, the memory is arranged in parallel with each side of the processor, but each memory is arranged in a parallel region formed by a side adjacent to the side of the processor facing the memory and a memory facing the side. Since even a part of the memory is not arranged, depending on the size of the processor and the memory, only four memories can be arranged around the processor as shown in the figure. Specifically, the width of the side facing the processor of the memory is not less than ½ of the width of the side facing the memory of the processor. The width of the side facing the memory of the processor is M, When the width of the opposite side is N, the relationship 2N ≧ M holds.

  On the other hand, in a semiconductor integrated circuit to which the element arrangement according to the present invention as shown in FIG. Can be arranged in a parallel region sandwiched between the memories facing each other, so that the width of the side facing the processor of each memory is 1/2 or more of the width of the side facing the processor memory Even in this case, as shown in the figure, eight memories can be arranged around the processor.

Although signal lines connected from the processor 102 to the memory are not shown in FIG. 1, the wiring pattern of the signal lines is not particularly limited. FIG. 3 shows an example of the wiring pattern of the semiconductor integrated circuit in FIG. FIG. 3 is a view of the semiconductor integrated circuit shown in FIG. 1 as viewed from directly above. The same components as those in FIG. In FIG. 3, 111 is a dedicated terminal group to which a signal line connected to the memory 103 is connected, 112 is a dedicated terminal group to which a signal line connected to the memory 104 is connected, and 113 is connected to both the memories 103 and 104. This is a common terminal group to which signal lines to be connected are connected. Furthermore, 114 is a dedicated signal line group connected to the memory 103 from the dedicated terminal group of the processor 102, 115 is a dedicated signal line group connected to the memory 104 from the dedicated terminal group of the processor 102, and 116 is a common terminal group of the processor 102. Is a common signal line group connected to the memories 103 and 104. In FIG. 3, the common signal line group 116 is shown as a single signal line. However, the common signal line group 116 may actually be constituted by a single signal line or a plurality of signal lines. Although arranged at the corner, it may be a side near the corner. These signal lines are data signal lines and address signal lines as in the prior art. Control signal lines and the like are included. Such terminals and signal lines can also be used in the following embodiments.

As described above, according to the first embodiment of the present invention, in a semiconductor integrated circuit having a plurality of memory systems, high integration is achieved, and an element that performs memory access to a plurality of memories. The connection signal line can be an equal length wiring. In this embodiment, the semiconductor integrated circuit having two memories has been described. However, the present invention can be applied to any semiconductor integrated circuit having at least two memories. The same applies to the embodiments .

  FIG. 4 shows a semiconductor integrated circuit according to the present embodiment. 4 is different from FIG. 1 in that the memories 103 and 104 are arranged on the opposite surfaces of the processor 102 and the semiconductor substrate 101. In addition, a common point with FIG. 1 is that a part of the memory 103 is arranged in a parallel region sandwiched between the processor 102 and the memory 104, and a part of the memory 104 is sandwiched between the processor 102 and the memory 103. It is arranged in a parallel region. 4A is a diagram showing the semiconductor integrated circuit in three dimensions, and FIG. 4B is a diagram showing the semiconductor integrated circuit from the side.

In the semiconductor integrated circuit having the structure shown in FIG. 4 as described above, a plurality of memories are arranged on the surface of the semiconductor substrate opposite to the side where the element for performing memory access is arranged. Many other elements can be arranged on the same surface as the element to be performed. at the same time,
Although it is on the opposite side of the semiconductor substrate, as in the first embodiment, a large number of memories can be arranged around the processor, so that it is possible to integrate a plurality of memories with equal-length wiring. It is.

(Third embodiment)
Next, a third embodiment of the present invention will be described. The present embodiment is characterized in that in the memory system according to the first embodiment, a part of the plurality of memories is arranged on the opposite surface of the semiconductor substrate from the element that performs memory access. .

  FIG. 5 shows a semiconductor integrated circuit according to the present embodiment. 5 is different from FIG. 1 in that the memory 104 is disposed on the opposite surface of the processor 102 and the semiconductor substrate 101. In addition, a common point with FIG. 1 is that a part of the memory 103 is arranged in a parallel region sandwiched between the processor 102 and the memory 104, and a part of the memory 104 is sandwiched between the processor 102 and the memory 103. It is arranged in a parallel region. 5A is a diagram showing the semiconductor integrated circuit in three dimensions, and FIG. 5B is a diagram showing the semiconductor integrated circuit from the side.

  In the semiconductor integrated circuit having the structure shown in FIG. 5 as described above, a part of the plurality of memories is provided on the surface of the semiconductor substrate opposite to the side where the element that performs memory access is arranged. Therefore, many elements other than the memory or other memory elements can be arranged on the same surface as the element that performs memory access. At the same time, as in the first embodiment, a large number of memories can be arranged around the processor on both sides of the semiconductor substrate, so that it is possible to integrate a plurality of memories with equal-length wiring. It is.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. The present embodiment is characterized in that in the memory system according to the third embodiment, a plurality of memories arranged on different surfaces of the semiconductor substrate overlap with each other with the semiconductor substrate interposed therebetween. To do.

  FIG. 6 shows a semiconductor integrated circuit according to the present embodiment. 6 is different from FIG. 5 in that the memories 102 and 103 arranged near one corner of the processor 101 are arranged closer to each other, and a part thereof overlaps with the semiconductor substrate 101 interposed therebetween. .

  In the semiconductor integrated circuit having the structure shown in FIG. 6 as described above, a part of the plurality of memories is provided on the surface of the semiconductor substrate opposite to the side where the element that performs memory access is arranged. Therefore, many elements other than the memory or other memory elements can be arranged on the same surface as the element that performs memory access. At the same time, since the memories arranged on both sides of the semiconductor substrate partially overlap each other with the semiconductor substrate interposed therebetween, more memories can be accessed than the semiconductor integrated circuit shown in the third embodiment. It becomes possible to arrange the same length wiring around the element to be performed.

FIG. 7 is a diagram showing an application of the memory arrangement of the semiconductor integrated circuit according to the present embodiment. For example, assuming that the width of the side facing the processor of the memory arranged around the processor 102 is N , the width of one side of the processor 102 is M , and the distance between the processor and each memory is L, the processor 102 of two memories When the length obtained by adding the widths of the opposite sides is greater than the length obtained by adding the distance between one side of the processor, the processor 102, and the memory, that is, 2N ≧ M + 2L. In this case, in the third embodiment, only one memory can be arranged on one side of the periphery of the processor 102. However, in this embodiment, two memories can be arranged on one side of the periphery of the processor 102. become.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. In this embodiment, in the memory system according to the first embodiment, a plurality of memories are similarly arranged on the opposite surface of the semiconductor substrate with respect to the plurality of memories arranged around the element that performs memory access. It is characterized by that.

  FIG. 8 shows a semiconductor integrated circuit according to the present embodiment. 8 is different from FIG. 1 in that memories 105 and 106 are similarly arranged on the opposite surface of the semiconductor substrate 101 with respect to the memories 103 and 104. That is, the memories 103 and 105 are completely overlapped with the semiconductor substrate 101 interposed therebetween, and the memories 104 and 106 are completely overlapped with the semiconductor substrate 101 interposed therebetween. In addition, although the example which overlaps completely is given, what is necessary is just the state which overlaps substantially completely.

  As described above, according to the semiconductor integrated circuit shown in FIG. 8, a plurality of memories are arranged on both sides of the semiconductor substrate. Therefore, more memories can be accessed than the semiconductor integrated circuit shown in the first embodiment. It can be placed around the element to be performed. If the memory arrangement of the semiconductor integrated circuit of this embodiment is applied, for example, a plurality of memories corresponding to the memories 103 to 110 may be arranged on the opposite surface of the semiconductor substrate 101 in the semiconductor integrated circuit in FIG. Is possible.

(Sixth embodiment)
Next, in the semiconductor integrated circuits according to the first to fifth embodiments of the present invention, input / output terminals of the dedicated signal line and the common signal line connected to the memory of the element that performs the memory access described with the processor 102 as an example A configuration example of the terminal groups of the dedicated terminal groups 111 and 112 and the common terminal group 113 that are a set group of the above, and a configuration example of the dedicated signal line groups 114 and 115 and the common signal line group 116 that connect these to the memory This will be described as an embodiment. In the present embodiment, an element having a plurality of terminals on the outer side and the inner side with respect to the center direction of a semiconductor element such as a BGA is used, and a device having terminals on two opposite sides as a memory is used. Yes.

FIG. 9 shows, as a cross-sectional view of a semiconductor integrated circuit, the terminal configuration of a processor and the configuration of signal lines connected to a memory that can be used in the semiconductor integrated circuit according to the first, third, and fourth embodiments of the present invention. ing. The processor 102 and the memory 103 are arranged on the same surface of the semiconductor substrate 101, and an external terminal 117 provided outside is provided as a terminal for inputting and outputting signal lines to and from the memory 103 to the processor 102. The inner terminal 118 provided inside the outer terminal 117 is configured. The outer terminal 117 and the inner terminal 118 constitute a dedicated terminal group 111 and 112 and a common terminal group 113. The outer terminal 117 and the memory 103 are connected by a signal line 119. The signal line 119 is configured on the same side of the semiconductor substrate 101 as the side on which the processor 102 and the memory 103 are disposed. On the other hand, the inner terminal 118 and the memory 103 are connected by a signal line 120. The signal line 120 is configured on the side of the semiconductor substrate 101 opposite to the side where the processor 102 and the memory 103 are disposed.

  The terminal configuration and the wiring pattern shown in FIG. 9 are characterized in that the processor 102 not only configures the terminals in parallel with the respective sides but also configures the terminals in the depth direction. The signal line 120 connecting the inner terminal 118 and the memory 103 can be provided with a large number of terminals with respect to the width of the side, and for this purpose, the processor 102 is disposed through the semiconductor substrate 101 from the inner terminal 118. The other side is wired toward the opposite side, passes through the opposite side, passes through the semiconductor substrate 101 again, and is connected to the memory 103.

  FIG. 10, like the configuration shown in FIG. 9, shows the terminal configuration of the processor and the configuration of the signal line connected to the memory that can be used in the semiconductor integrated circuit in the first, third, and fourth embodiments of the present invention. 1 is a cross-sectional view of a semiconductor integrated circuit. 10 is different from FIG. 9 in that the signal line connecting the inner terminal 118 of the processor 102 and the memory 103 is not wired on the opposite side of the semiconductor substrate like the signal line 120, but is shown in the figure. As described above, the signal line 121 is wired through the inside of the semiconductor substrate.

  With this configuration, the processor 102 can have terminals in the depth direction like the outer terminal 117 and the inner terminal 118 without wiring signal lines on one side of the semiconductor substrate.

  FIG. 11 shows the configuration of the terminal of the processor and the configuration of the signal line connected to the memory that can be used in the semiconductor integrated circuit in the first, third, and fourth embodiments of the present invention, as in the configuration shown in FIG. 1 is a cross-sectional view of a semiconductor integrated circuit. 11 differs from FIG. 9 in that the signal line connecting the outer terminal 117 of the processor 102 and the memory 103 is not wired on the same surface side of the semiconductor substrate as the signal line 119, but is shown in the figure. As described above, the signal line 121 is wired through the inside of the semiconductor substrate.

  With this configuration, the wiring area on the semiconductor substrate can be reduced, so that a semiconductor integrated circuit with higher integration efficiency can be realized.

  FIG. 12 is a cross-sectional view of a semiconductor integrated circuit showing a terminal configuration of a processor and a signal line connected to a memory that can be used in the semiconductor integrated circuit according to the second, third, and fourth embodiments of the present invention. Yes. The processor 102 and the memory 104 are arranged on different surfaces of the semiconductor substrate 101, and an external terminal 117 provided outside is provided as a terminal for inputting and outputting signal lines to and from the memory 104 in the processor 102. And the inner side terminal 118 provided inside the outer side terminal 117 is comprised. The outer terminal 117 and the inner terminal 118 constitute a dedicated terminal group 111 and 112 and a common terminal group 113. The outer terminal 117 and the memory 104 are connected by a signal line 119. The signal line 119 is configured on the same side of the semiconductor substrate 101 as the side on which the processor 102 is disposed. On the other hand, the internal terminal 118 and the memory 104 are connected by a signal line 120. The signal line 120 is configured on the same side as the side on which the memory 104 of the semiconductor substrate 101 is disposed.

  The features of the terminal configuration and wiring pattern shown in FIG. 12 are the same as those shown in FIG. 9, in which the processor 102 not only configures the terminals in parallel with each side but also the terminals in the depth direction. Therefore, unlike FIG. 9, the processor 102 and the memory 104 are arranged on different surfaces of the semiconductor substrate. It corresponds to the case.

  FIG. 13 is a cross-sectional view of the semiconductor integrated circuit according to the first, third, and fourth embodiments of the present invention, similar to the configuration shown in FIG. 13 differs from FIG. 12 in that the signal line connecting the outer terminal 117 of the processor 102 and the memory 104 is not wired on the same side as the processor of the semiconductor substrate like the signal line 119. As shown in FIG. 4, the signal line 121 is wired through the inside of the semiconductor substrate.

  With this configuration, the area of the wiring region on the surface of the semiconductor substrate on which the processor is disposed can be reduced, so that a semiconductor integrated circuit with higher integration efficiency can be realized.

  FIG. 14 shows the terminal configuration of the processor and the configuration of the signal lines connected to the memory that can be used in the semiconductor integrated circuit in the second, third, and fourth embodiments of the present invention, as in the configuration shown in FIG. 1 is a cross-sectional view of a semiconductor integrated circuit. 14 is different from FIG. 12 in that a signal line connecting the inner terminal 118 of the processor 102 and the memory 104 is not wired on the same surface as the memory 104 of the semiconductor substrate like the signal line 120. As shown in FIG. 4, the signal line 121 is wired through the inside of the semiconductor substrate.

  With this configuration, the area of the wiring region on the surface of the semiconductor substrate opposite to the side on which the processor is disposed can be reduced, so that a semiconductor integrated circuit with higher integration efficiency can be realized.

  FIG. 15 is a cross-sectional view of a semiconductor integrated circuit showing the terminal configuration of a processor and the configuration of signal lines connected to a memory that can be used in the fourth and fifth embodiments of the present invention.

  On one surface of the semiconductor substrate, a processor 102 and a memory 103 connected to the processor 102 through signal lines are arranged, and on the other surface, a memory 104 connected to the processor 102 through signal lines is arranged. ing. The memories 103 and 104 are partially or entirely overlapped with the semiconductor substrate 101 interposed therebetween.

  The processor 102 has a first terminal 123 provided along the periphery of the processor 102 through which a signal line connected to the memory 103 is input and output, and a second terminal provided in the processor 102 from the first terminal 123. The first terminal 123 and the memory 103 are connected to the memory 103 via the signal line 119, and the second terminal 124 and the memory 103 are connected to the memory 103 via the signal line 121. ing. The signal line 119 is wired on the same surface as the processor 102 of the semiconductor substrate 101 and the signal line 121 is wired inside the semiconductor substrate 101. On the other hand, a signal line connected to the memory 104 is input / output to / from the processor 102, a third terminal 125 provided inside the second terminal 124 of the processor 102, and provided inside the third terminal 125. The third terminal 125 and the memory 104 are connected to the memory 104 via the signal line 122, and the fourth terminal 126 and the memory 104 are connected to the memory 104 via the signal line 120. Connected with. The signal line 122 is wired inside the semiconductor substrate 101, and the signal line 120 is wired on a surface different from the surface on which the processor 102 of the semiconductor substrate 101 is disposed.

  With this configuration, when the memories are arranged on both sides of the semiconductor substrate and these memories overlap with each other with the semiconductor substrate interposed therebetween, the area of the wiring region can be reduced and a semiconductor integrated circuit with a higher degree of integration can be realized. it can.

  In each embodiment of the present invention, 102 is a processor. However, the present invention is not limited to this, and any element that performs data access to the memories 103 and 104 may be used. In addition, the semiconductor integrated circuit according to each embodiment of the present invention includes those packaged in a state where a plurality of semiconductor elements are arranged on one chip, and those obtained by packaging each semiconductor element as a semiconductor. What is arrange | positioned to a board | substrate can also be included. The form of the package is not particularly limited.

  The semiconductor device and the semiconductor mounting substrate according to the present invention are useful in a memory system or the like. The present invention can also be applied to a case where a semiconductor device and a system composed of a plurality of the same semiconductor devices are configured.

  In addition, it is expected to be used in a wide range of embedded devices equipped with such a memory system.

Semiconductor integrated circuit diagram according to the first embodiment of the present invention Application diagram of the semiconductor integrated circuit according to the first embodiment of the present invention 1 is a wiring pattern diagram of a semiconductor integrated circuit according to a first embodiment of the present invention; Semiconductor integrated circuit diagram according to the second embodiment of the present invention Semiconductor integrated circuit diagram according to the third embodiment of the present invention Semiconductor integrated circuit diagram according to the fourth embodiment of the present invention Application diagram of semiconductor integrated circuit according to the fourth embodiment of the present invention Semiconductor integrated circuit diagram according to the fifth embodiment of the present invention Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (1) Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (2) Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (3) Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (4) Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (5) Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (6) Cross-sectional view of wiring of semiconductor integrated circuit of the present invention (7) Conventional semiconductor integrated circuit diagram Application diagram of conventional semiconductor integrated circuits

Explanation of symbols

101 Semiconductor substrate 102 Processor 103, 104, 105, 106, 107, 108, 109, 110 Memory 111, 112 Dedicated terminal group 113 Common terminal group 114, 115 Dedicated signal line group 116 Common terminal group 117 Outer terminal 118 Inner terminal 119, 120, 121, 122 Signal line 123 Data signal line 124 Address signal line 125 Control signal line

Claims (7)

A semiconductor device comprising first and second memory elements having a rectangular structure on the same surface of a semiconductor substrate, and a semiconductor element having a rectangular structure accessible to the first and second memory elements,
The first memory element is arranged so that one side of the first memory element is parallel to the first side of the semiconductor element, and the second side adjacent to the first side of the semiconductor element is The second memory element is arranged so that one side of the second memory element is parallel, and a part of the first memory element includes a second side of the semiconductor element and a second side of the semiconductor element. 2 is disposed in a region sandwiched by parallel lines of the sides of the second memory element facing the two sides, and a part of the second memory element includes the first side of the semiconductor element and the semiconductor element Disposed in a region sandwiched by parallel lines of the side of the first memory element facing the first side;
The semiconductor substrate further comprises third and fourth memory elements that are accessible to the semiconductor element on a surface different from the surface on which the semiconductor element is disposed.
The first, second, third, and fourth memory elements have the same shape, and the first memory element and the third memory element overlap with each other across the semiconductor substrate. The semiconductor device is characterized in that the second memory element and the fourth memory element are overlapped with each other across the semiconductor substrate.   The semiconductor element includes a common terminal to which a common signal line connected to the first and second memory elements is connected, and a first dedicated signal line connected to the first memory element. 2. The semiconductor device according to claim 1, further comprising a second dedicated terminal to which one dedicated terminal and a second dedicated signal line connected to the second memory element are connected.   The first dedicated terminal is provided along the first side, the second dedicated terminal is provided along the second side, and the common terminal is more than the first and second dedicated terminals. Provided along the first side and the second side close to the corner between the first side and the second side of the semiconductor element, or at the corner between the first side and the second side. The semiconductor device according to claim 2, wherein:   The common signal line, the first dedicated signal line, and the second dedicated signal line are each composed of a plurality of signal lines, and the common terminal, the first dedicated terminal, and the second dedicated terminal are each composed of a plurality of terminals. 4. The semiconductor device according to claim 3, wherein:   The common terminal includes an outer terminal provided along the periphery of the semiconductor element and an inner terminal provided on the inner side of the outer terminal with respect to the center direction of the semiconductor element. The semiconductor device according to claim 4.   The first dedicated terminal and the second dedicated terminal include an outer terminal provided along a periphery of the semiconductor element, and an inner terminal provided inside the outer terminal with respect to a central direction of the semiconductor element. The semiconductor device according to claim 4, comprising: The semiconductor element includes a plurality of dedicated terminals to which a plurality of dedicated signal lines connected to the first and third memory elements are connected, and the plurality of dedicated terminals are provided along the periphery of the semiconductor element. A first terminal, a second terminal provided on the inner side of the first terminal with respect to the central direction of the semiconductor element, and an inner side of the second terminal with respect to the central direction of the semiconductor element. A third terminal provided; and a fourth terminal provided on the inner side of the third terminal with respect to the central direction of the semiconductor element. The dedicated terminal connected to the first terminal. The signal line is wired on the same surface as the semiconductor element on the semiconductor substrate and connected to the first memory element, and the dedicated signal line connected to the second terminal is connected to the semiconductor substrate. Wired through the inside of the first memo A dedicated signal line connected to the element and connected to the third terminal is wired through the inside of the semiconductor substrate, connected to the third memory element, and connected to the fourth terminal. 2. The semiconductor device according to claim 1, wherein the signal line is wired on a surface different from a surface on which the semiconductor element is disposed of the semiconductor substrate and is connected to the third memory element.

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