JP7282523B2 - Printed Circuit Boards, Printed Wiring Boards, Electronics, and Cameras - Google Patents

Description

The present invention relates to a printed circuit board comprising a printed circuit board on which an element with multiple receiving terminals and an element with multiple transmitting terminals are provided.

A memory system, which is an example of a printed circuit board, includes a memory controller, which is an example of an element having a plurality of transmission terminals, a memory device, which is an example of an element having a plurality of reception terminals, and a printed wiring board on which these are mounted. , is equipped with

A transmission terminal of the memory controller and a reception terminal of the memory device are electrically connected by bus wiring on the printed wiring board. The memory controller controls the memory devices by sending address signals and command signals to the memory devices via bus lines.

Also, the memory controller and the memory device have data terminals for transmitting and receiving data signals, and the data terminals of the memory controller and the data terminals of the memory device are electrically connected by data signal lines of the printed wiring board.

High-performance electronic devices need to process large amounts of data. The electronic device described in Patent Literature 1 can process a large amount of data by including two memory devices. The two memory devices described in Patent Literature 1 are electrically connected to a memory controller by a bus wiring composed of T-branch wiring.

JP 2008-171950 A

However, in the conventional printed wiring board, each of the plurality of wirings constituting the bus wiring has the same configuration, and the plurality of wirings are arranged side by side in the width direction, so that the printed wiring board becomes large. As a result, the size of the printed circuit board has increased, and the size of electronic equipment on which the printed circuit board is mounted has also increased.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the size of a printed wiring board, that is, a printed circuit board.

A first aspect of the present disclosure provides a printed wiring board including first and second layers spaced apart from each other ; a first element provided on the printed wiring board ; a second element ; and a plurality of first wirings electrically connecting the first element, the second element , and the third element , the first element , and the third element. a plurality of second wirings that electrically connect the two elements and the third element and that are different from the first wirings , the plurality of first wirings being provided in the first layer and the second layer, respectively A first region in which the first element is positioned, a second region in which the second element is positioned, and the third element in a plan view from a direction perpendicular to the main surface of the printed wiring board. a first via conductor arranged between the second region and the third region outside the third region; and a first conductor pattern extending from toward the first region, wherein each of the plurality of second wirings is arranged across the first layer and the second layer, and in the plan view, the first , a second via conductor arranged between the second region and the third region outside the second and third regions; and a second conductor pattern extending from the via conductor toward the first region, and the fourth region in which the plurality of first conductor patterns are arranged in plan view includes a plurality of the second conductor patterns. The printed circuit board is characterized in that it is arranged so as to overlap with the arranged fifth region.
A second aspect of the present disclosure includes a first layer and a second layer that are spaced apart from each other, and in plan view from a direction perpendicular to the main surface, a first region where the first element is arranged, a first A printed wiring board having a second region where two elements are arranged and a third region where a third element is arranged, wherein the first element, the second element and the third element are electrically connected and a plurality of second wirings electrically connecting the first element, the second element, and the third element and different from the first wirings. , each of the plurality of first wirings is disposed across the first layer and the second layer, and is outside the first, second and third regions in plan view, the second region and the a first via conductor arranged between a third region and a first conductor pattern arranged in the first layer and extending from the first via conductor toward the first region in plan view; wherein each of the plurality of second wirings is arranged across the first layer and the second layer and outside the first, second, and third regions in plan view, the second region a second via conductor disposed between and the third region; and a second conductor pattern disposed on the second layer and extending from the second via conductor toward the first region in plan view. and wherein, in plan view, a fourth region in which the plurality of first conductor patterns are arranged is arranged so as to overlap a fifth region in which the plurality of second conductor patterns are arranged. A printed wiring board characterized by:

According to the present invention, a printed wiring board, that is, a printed circuit board can be miniaturized.

1A is a front view of a network camera as an example of an electronic device according to a first embodiment; FIG. 2B is a side view of a network camera as an example of electronic equipment according to the first embodiment; FIG. 1 is a block diagram of a network camera according to a first embodiment; FIG. 1 is a cross-sectional view of a printed circuit board according to a first embodiment; FIG. 1A is a schematic diagram of a memory controller and a memory device according to the first embodiment; FIG. 4B is a schematic diagram of first wiring and second wiring according to the first embodiment; FIG. (a) is a schematic diagram of the first wiring according to the first embodiment. (b) is a schematic diagram of a second wiring according to the first embodiment. (a) is a perspective view schematically showing a portion of the first wiring according to the first embodiment. (b) is a perspective view schematically showing a portion of the second wiring according to the first embodiment. (c) is a perspective view schematically showing a part of the first and second wirings according to the first embodiment. 2 is a plan view showing address/command signal lines of Example 1. FIG. 2 is a perspective view showing address/command signal lines of Example 1. FIG. (a) is a simulation waveform diagram of the signal of Example 2. FIG. (b) is a simulation waveform diagram of the signal of Example 2. FIG. (a) is a schematic diagram of a first wiring and a second wiring according to a second embodiment. (b) is a schematic diagram of the first wiring according to the second embodiment. (c) is a schematic diagram of a second wiring according to the second embodiment. (a) is a perspective view schematically showing a portion of a first wiring according to a second embodiment. (b) is a perspective view schematically showing a portion of the second wiring according to the second embodiment. FIG. 11 is a plan view showing address/command signal lines of Example 3; FIG. 11 is a perspective view showing address/command signal lines of Example 3; (a) is a simulation waveform diagram of a signal in Example 3. FIG. (b) is a simulation waveform diagram of the signal of Example 3. FIG. (a) is a schematic diagram of wiring of a comparative example. (b) is a schematic diagram of wiring of a comparative example. (c) is a schematic diagram of wiring of a comparative example. 8 is a plan view showing address/command signal lines of Comparative Example 1; FIG. 3 is a perspective view showing an address/command signal line of Comparative Example 1; FIG. (a) is a simulation waveform diagram of a signal in Comparative Example 2. FIG. (b) is a simulation waveform diagram of a signal in Comparative Example 2. FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
[First embodiment]
FIG. 1(a) is a front view of a network camera 500 as an example of the electronic device according to the first embodiment, and FIG. 1(b) is a side view of the network camera 500 as an example of the electronic device according to the first embodiment. It is a diagram. A network camera 500 includes a rotation base 501, a pair of support bases 502 provided on the rotation base 501, a lens frame 503 which is a housing supported by the pair of support bases 502, and a front portion of the lens frame 503. and a lens unit 504, which is a lens barrel provided. A power terminal 505 is arranged on the rear portion of the rotation base 501 . The attitude of the lens unit 504 is variable with respect to the rotation base 501 . The network camera 500 is remotely operated by a remote controller (not shown) directly or via a network, and can perform orientation of the lens unit 504, zooming, focusing, and the like.

FIG. 2 is a block diagram of the network camera 500 according to the first embodiment. The network camera 500 is a digital camera, and includes an imaging element 600 and a printed circuit board 100 electrically connected to the imaging element 600 by a cable 700 . The printed circuit board 100 has a printed wiring board 200 . The printed circuit board 100 has a memory controller 301 as an example of a first element, a memory device 311 as an example of a second element, and a memory device 312 as an example of a third element. The memory device 311 and the memory device 312 are memory devices with the same configuration. The memory devices 311 and 312 are, for example, DDR (Double Data Rate) 4 memories. The printed circuit board 100 has a connector 302 , a bridge chip 303 and a LAN (Local Area Network) chip 304 . The memory controller 301 , memory devices 311 and 312 , connector 302 , bridge chip 303 and LAN chip 304 are mounted on the printed wiring board 200 .

The imaging element 600 and the connector 302 are electrically connected by a cable 700 such as a flexible flat cable. Connector 302 and bridge chip 303 are electrically connected by wiring of printed wiring board 200 . The bridge chip 303 and the memory controller 301 are electrically connected by wiring of the printed wiring board 200 . The memory controller 301 and the LAN chip 304 are electrically connected by wiring of the printed wiring board 200 . The memory controller 301 and the two memory devices 311 and 312 are electrically connected by wiring of the printed wiring board 200 .

The imaging element 600 is arranged inside the lens frame 503 in close proximity to the lens unit 504 shown in FIGS. 1(a) and 1(b). The imaging device 600 is an image sensor and outputs an image data signal representing a captured image. The imaging device 600 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor.

A bridge chip 303 is a member provided when it is necessary to convert a signal output from the image sensor 600 into a signal that can be processed by the memory controller 301 . If the memory controller 301 can process the output signal of the imaging device 600 as it is, the bridge chip 303 can be omitted.

The memory controller 301 and the memory devices 311 and 312 are each configured in one semiconductor package. The memory controller 301 and the memory device 311 are electrically connected by data signal lines of the printed wiring board 200 so that image data signals can be transmitted and received. The memory controller 301 and the memory device 312 are electrically connected by data signal lines of the printed wiring board 200 so that image data signals can be transmitted and received.

Furthermore, the memory controller 301 and the memory devices 311 and 312 are electrically connected by an address/command signal line, which is a bus wiring composed of a plurality of wirings of the printed wiring board 200 . The memory controller 301 transmits an address signal and a command signal to the two memory devices 311 and 312 via the address/command signal line by parallel transmission. Address signals and command signals sent from the memory controller 301 are both received by the two memory devices 311 and 312 through address/command signal lines. Each of the memory devices 311 and 312 performs processing such as data storage and erasure according to the address signal and command signal.

The memory controller 301 transmits image data signals obtained from the memory devices 311 and 312 or the bridge chip 303 to the LAN chip 304 . The LAN chip 304 can be transmitted to the outside of the network camera 500 through a LAN cable (not shown) or the like.

FIG. 3 is a cross-sectional view of the printed circuit board 100 according to the first embodiment. FIG. 3 shows only the memory device 311 among the memory devices 311 and 312 shown in FIG. The printed wiring board 200 has an insulating base material (for example, epoxy resin) and a conductive conductor (for example, copper) that constitutes wiring. The wiring is provided on the substrate.

Printed wiring board 200 is a laminated board having six wiring layers 201 , 202 , 203 , 204 , 205 and 206 . The six wiring layers 201 to 206 are spaced apart from each other in the Z direction, which is the direction perpendicular to the main surface of the printed wiring board 200 and also the stacking direction. The wiring layers 201 to 206 are arranged in the order of the wiring layer 201, the wiring layer 202, the wiring layer 203, the wiring layer 204, the wiring layer 205, and the wiring layer 206 from one side to the other side in the Z direction. The wiring layers 201 and 206 are main surfaces, that is, surface layers that are mounting surfaces, and the wiring layers 202 to 205 between the wiring layer 201 and the wiring layer 206 are inner layers. A solder resist (not shown) may be arranged on the wiring layers 201 and 206 .

A conductor pattern 270 such as a copper foil constituting wiring is arranged on each wiring layer 201-206, and a via conductor 260 constituting wiring is arranged between the wiring layers 201-206. A via conductor 260 is a conductor placed in a via. In this embodiment, via conductor 260 is a build-up via. Note that FIG. 3 does not accurately illustrate data signal lines and address/command signal lines, but schematically illustrates a cross section of printed wiring board 200 for explaining wiring layers 201-206.

The memory controller 301, the memory device 311, and the memory device 312 shown in FIG. 2 are mounted together on the wiring layer 201 of the wiring layers 201 and 206, which are a pair of surface layers. Although both the two memory devices 311 and 312 are preferably mounted on the wiring layer 201 , one may be mounted on the wiring layer 201 and the other on the wiring layer 206 . Also, the memory controller 301 is preferably mounted on the same wiring layer 201 as the two memory devices 311 and 312 , but may be mounted on the wiring layer 206 .

Components such as capacitors and resistors are mounted on the wiring layer 206 . The wiring layers 202 and 205 are layers in which conductor patterns that mainly serve as grounds are arranged. The wiring layer 203 which is the first layer is a layer relatively close to the wiring layer 201 with respect to the wiring layer 204 which is the second layer. The wiring layers 203 and 204 are layers in which conductor patterns that mainly serve as signal lines such as data signal lines and address/command signal lines are arranged.

Each of the memory controller 301 and memory devices 311 and 312 has multiple signal terminals, multiple power supply terminals, and multiple ground terminals. Each terminal of the memory controller 301 and the memory devices 311 and 312 has a BGA (Ball Grid Array) structure. The memory controller 301 and memory devices 311 and 312 are joined to the printed wiring board 200 by soldering.

FIG. 4A is a schematic diagram of the memory controller 301 and memory devices 311 and 312 when the printed circuit board 100 according to the first embodiment is viewed in the Z direction. FIG. 4B is a schematic diagram of wiring of the printed wiring board 200 when the printed circuit board 100 according to the first embodiment is viewed in the Z direction.

As shown in FIG. 4A, the memory devices 311 and 312 are spaced apart in the X direction perpendicular to the Z direction. Also, the memory controller 301 is spaced apart from the memory devices 311 and 312 in the Y direction orthogonal to the X and Z directions.

The memory controller 301 has, as signal terminals, four transmission terminals 351 as a plurality of first transmission terminals and four transmission terminals 352 as a plurality of second transmission terminals. The memory device 311 has, as signal terminals, four receiving terminals 361 as a plurality of first receiving terminals and four receiving terminals 362 as a plurality of second receiving terminals. The memory device 312 has, as signal terminals, four reception terminals 363 that are a plurality of third reception terminals and four reception terminals 364 that are a plurality of fourth reception terminals. That is, the memory controller 301 has eight transmission terminals and can transmit 8-bit address signals and command signals. Each of the memory devices 311 and 312 has eight receiving terminals and can receive an 8-bit address signal and command signal. In addition, in FIG. 4A, illustration of terminals other than the transmission terminals 351 and 352 of the memory controller 301 is omitted. Terminals other than the receiving terminals 361, 362, 363, and 364 of the memory devices 311 and 312 are also omitted. The number of transmission terminals of the memory controller 301, the number of reception terminals of the memory device 311, and the number of reception terminals of the memory device 312 are not limited to eight.

FIG. 4B shows wiring layers 203 and 204 of the printed wiring board 200 . In FIG. 4B, the conductor patterns arranged on the wiring layer 203 are shown by solid lines, and the conductor patterns arranged on the wiring layer 204 are shown by broken lines. The printed wiring board 200 has four wirings 251, which are a plurality of first wirings, electrically connecting the transmitting terminal 351 and the receiving terminals 361 and 363 shown in FIG. 4(a). The printed wiring board 200 has four wirings 252, which are a plurality of second wirings, electrically connecting the transmitting terminal 352 and the receiving terminals 362, 364 shown in FIG. 4(a). These eight wirings 251 and 252 constitute an address/command signal line 250 which is a transmission line for address signals and command signals, that is, a bus wiring. Note that the number of wirings forming the address/command signal line 250 is not limited to eight. The number of wires forming the address/command signal line 250 should correspond to the number of transmission terminals of the memory controller 301 , the number of reception terminals of the memory device 311 , and the number of reception terminals of the memory device 312 .

In the printed wiring board 200, the first region when the memory controller 301 shown in FIG. 4A is projected in the Z direction is defined as region R1. The memory controller 301 is arranged at the position of the region R1 of the printed wiring board 200 when viewed in the Z direction (planar view). In the printed wiring board 200, a second region when the memory device 311 shown in FIG. 4A is projected in the Z direction is defined as a region R2. The memory device 311 is arranged at the position of the region R2 of the printed wiring board 200 when viewed in the Z direction. In the printed wiring board 200, the third area when the memory device 312 shown in FIG. 4A is projected in the Z direction is assumed to be an area R3. The memory device 312 is arranged at the position of the region R3 of the printed wiring board 200 when viewed in the Z direction.

FIG. 5A is a schematic diagram of the wiring 251 of the printed wiring board 200 when the printed circuit board 100 according to the first embodiment is viewed in the Z direction. FIG. 5B is a schematic diagram of the wiring 252 of the printed wiring board 200 when the printed circuit board 100 according to the first embodiment is viewed in the Z direction. Similar to FIG. 4B, FIGS. 5A and 5B show wiring layers 203 and 204 of the printed wiring board 200. FIG. As in FIG. 4B, in FIGS. 5A and 5B, the conductor patterns arranged on the wiring layer 203 are shown by solid lines, and the conductor patterns arranged on the wiring layer 204 are shown by broken lines. .

As shown in FIG. 5(a), each wiring 251 includes a main wiring 280 extending from the memory controller 301 shown in FIG. 4(a) and a memory branched from the main wiring 280 to form the memory shown in FIG. 4(a). and branch wirings 281 and 282 extending to the devices 311 and 312 . One end of the main wiring 280 is connected to the transmission terminal 351 of the memory controller 301 shown in FIG. 4(a). The other end of the main wiring 280 is connected to one end of the branch wiring 281 and one end of the branch wiring 282 . The other end of the branch wiring 281 is connected to the receiving terminal 361 of the memory device 311 shown in FIG. 4(a). The other end of the branch wiring 282 is connected to the receiving terminal 363 of the memory device 312 shown in FIG. 4(a). Thus, each wiring 251 has a so-called T-branch structure.

As shown in FIG. 5B, each wiring 252 includes a main wiring 285 extending from the memory controller 301 of FIG. 4A and a memory device shown in FIG. and branch wirings 286 and 287 extending to 311 and 312, respectively. One end of the main wiring 285 is connected to the transmission terminal 352 of the memory controller 301 shown in FIG. 4(a). The other end of the main wiring 285 is connected to one end of the branch wiring 286 and one end of the branch wiring 287 . The other end of the branch wiring 286 is connected to the receiving terminal 362 of the memory device 311 shown in FIG. 4(a). The other end of the branch wiring 287 is connected to the receiving terminal 364 of the memory device 312 shown in FIG. 4(a). Thus, each wiring 252 has a so-called T-branch structure.

Each wiring 251 and each wiring 252 will be specifically described below. As shown in FIG. 5A, each wiring 251 has via conductors 261, which are first via conductors, arranged outside the regions R1, R2, and R3 when viewed in the Z direction. Via conductor 261 is arranged across wiring layer 203 and wiring layer 204 shown in FIG. As shown in FIG. 5B, each wiring 252 has via conductors 262, which are second via conductors, arranged outside the regions R1, R2, and R3 when viewed in the Z direction. The via conductor 262 is arranged across the wiring layer 203 and the wiring layer 204 shown in FIG. In this embodiment, the via conductor 261 is included in the branch wiring 282 and the via conductor 262 is included in the branch wiring 286 .

A main wiring 280 of each wiring 251 shown in FIG. 5A has a conductor pattern 271, which is a first conductor pattern, extending from the via conductor 261 toward the region R1 when viewed in the Z direction. In this embodiment, the conductor pattern 271 extends from the via conductor 261 to the inside of the region R1 when viewed in the Z direction. The main wiring 285 of each wiring 252 shown in FIG. 5B has a conductor pattern 272, which is a second conductor pattern, extending from the via conductor 262 toward the region R1 when viewed in the Z direction. In this embodiment, the conductor pattern 272 extends from the via conductor 262 to the inside of the region R1 when viewed in the Z direction. A conductor pattern 271 shown in FIG. 5A is arranged on the wiring layer 203, and a conductor pattern 272 shown in FIG. Since the conductor pattern 271 and the conductor pattern 272 are arranged in different layers, the conductor pattern 271 and the conductor pattern 272 spread in the width direction of the main wirings 280 and 285, that is, in the X direction shown in FIG. You can prevent it from being placed. Thereby, the printed wiring board 200 can be miniaturized. Therefore, the printed circuit board 100 can be miniaturized, and the network camera 500 shown in FIGS. 1(a) and 1(b) can be miniaturized.

Since each wiring 251 has a conductor pattern 271 and each wiring 252 has a conductor pattern 272, in this embodiment, the plurality (four) of conductor patterns 271 shown in FIG. , there are a plurality (four) of conductor patterns 272 shown in FIG. Each conductor pattern 271 shown in FIG. 5(a) has a portion 271-1 extending linearly in the Y direction. Each conductor pattern 272 shown in FIG. 5(b) has a portion 272-1 extending linearly in the Y direction. In FIGS. 5(a) and 5(b), the portion 271-1 and the portion 272-1 are all linear, but they do not necessarily have to be linear.

A plurality of portions 271-1 extending in the Y direction shown in FIG. 5A are arranged at intervals in the X direction. A plurality of portions 272-1 extending in the Y direction shown in FIG. 5B are arranged at intervals in the X direction. A fourth region in which the plurality of portions 271-1 are arranged when viewed in the Z direction is defined as a region R4. A region R4 is a region between two of the plurality of portions 271-1 that are farthest apart in the X direction. A fifth region in which the plurality of portions 272-1 are arranged when viewed in the Z direction is defined as a region R5. A region R5 is a region between two of the plurality of portions 272-1 that are farthest apart in the X direction. In addition, in FIG. 4B, for convenience of explanation, the regions R4 and R5 are drawn slightly shifted in the X direction.

As shown in FIG. 4B, when viewed in the Z direction, the region R4 and the region R5 overlap partially or entirely, in this embodiment, entirely. When the region R4 and the region R5 partially overlap, it is preferable that half or more of them overlap. Since the conductor pattern 271 is arranged on the wiring layer 203 and the conductor pattern 272 is arranged on the wiring layer 204, the region R4 and the region R5 can be overlapped when viewed in the Z direction. Thereby, the printed wiring board 200 can be miniaturized.

Note that if one of the plurality of wirings 251 and one of the plurality of wirings 252 is focused, when viewed from the Z direction, the portion 271-1 and the portion 272-1 are part or All should be overlapped. When part of the portion 271-1 and the portion 272-1 overlap, it is preferable that half or more of them overlap. In FIG. 4B, for convenience of explanation, the portion 272-1 of the conductor pattern 272 is slightly shifted in the X direction with respect to the portion 271-1 of the conductor pattern 271. As shown in FIG.

As shown in FIG. 5A, the branch wiring 281 of each wiring 251 has a conductor pattern 273, which is a third conductor pattern, extending from the via conductor 261 toward the region R2 when viewed in the Z direction. In this embodiment, the conductor pattern 273 extends from the via conductor 261 to the inside of the region R2 when viewed in the Z direction. The branch wiring 282 of each wiring 251 has a conductor pattern 274, which is a fourth conductor pattern, extending from the via conductor 261 toward the region R3 when viewed in the Z direction. In this embodiment, the conductor pattern 274 extends from the via conductor 261 to the inside of the region R4 when viewed in the Z direction. The conductor pattern 273 is arranged on the wiring layer 203 and the conductor pattern 274 is arranged on the wiring layer 204 .

A branch wiring 281 of each wiring 251 has a via conductor 263 which is a third via conductor connected to the conductor pattern 273 . The via conductor 263 is arranged inside the region R2 when viewed in the Z direction. Via conductor 263 is arranged across wiring layer 201 and wiring layer 203 shown in FIG. A branch wiring 282 of each wiring 251 has a via conductor 264 which is a fourth via conductor connected to the conductor pattern 274 . The via conductor 264 is arranged inside the region R3 when viewed in the Z direction. Via conductor 264 is arranged across wiring layer 201 and wiring layer 204 shown in FIG.

As shown in FIG. 5B, the branch wiring 286 of each wiring 252 has a conductor pattern 275, which is the fifth conductor pattern, extending from the via conductor 262 toward the region R2 when viewed in the Z direction. In this embodiment, the conductor pattern 275 extends from the via conductor 262 to the inside of the region R2 when viewed in the Z direction. The branch wiring 287 of each wiring 252 has a conductor pattern 276, which is a sixth conductor pattern, extending from the via conductor 262 toward the region R3 when viewed in the Z direction. In this embodiment, the conductor pattern 276 extends from the via conductor 262 to the inside of the region R3 when viewed in the Z direction. The conductor pattern 275 is arranged on the wiring layer 203 and the conductor pattern 276 is arranged on the wiring layer 204 .

A branch wiring 286 of each wiring 252 has a via conductor 265 which is a fifth via conductor connected to the conductor pattern 275 . The via conductor 265 is arranged inside the region R2 when viewed in the Z direction. Via conductor 265 is arranged across wiring layer 201 and wiring layer 203 shown in FIG. A branch wiring 287 of each wiring 252 has a via conductor 266 which is a sixth via conductor connected to the conductor pattern 276 . The via conductor 266 is arranged inside the region R3 when viewed in the Z direction. Via conductor 266 is arranged across wiring layer 201 and wiring layer 204 shown in FIG.

As shown in FIG. 5A, the main wiring 280 of each wiring 251 has a via conductor 267 that is arranged inside the region R1 when viewed in the Z direction and connected to the conductor pattern 271 . Via conductor 267 is arranged across wiring layer 201 and wiring layer 203 shown in FIG. As shown in FIG. 5B, the main wiring 285 of each wiring 252 has a via conductor 268 that is arranged inside the region R1 when viewed in the Z direction and connected to the conductor pattern 272 . Via conductor 268 is arranged across wiring layer 201 and wiring layer 204 shown in FIG. Via conductors 261, 262, 263, 264, 265, 266, 267, and 268 shown in FIGS. 5(a) and 5(b) are built-up vias.

As described above, the main wiring 280 shown in FIG. 5A has the via conductors 267 and the conductor patterns 271 . The branch wiring 281 has conductor patterns 273 and via conductors 263 . The branch wiring 282 has via conductors 261 , conductor patterns 274 and via conductors 264 . 5A and the transmission terminal 351 of the memory controller 301 shown in FIG. 4A are arranged in the wiring layer 201 shown in FIG. are electrically connected by a conductor pattern of That is, the transmission terminal 351 of the memory controller 301 is soldered to a conductor pattern (not shown) arranged on the wiring layer 201 shown in FIG. The via conductor 263 and the receiving terminal 361 of the memory device 311 shown in FIG. 4A are electrically connected by a conductor pattern (not shown) arranged in the wiring layer 201 shown in FIG. there is That is, the receiving terminal 361 of the memory device 311 is soldered to a conductor pattern (not shown) arranged on the wiring layer 201 shown in FIG. The via conductor 264 and the receiving terminal 363 of the memory device 312 shown in FIG. 4A are electrically connected by a conductor pattern (not shown) arranged in the wiring layer 201 shown in FIG. there is That is, the receiving terminal 363 of the memory device 312 is soldered to a conductor pattern (not shown) arranged on the wiring layer 201 shown in FIG.

The main wiring 285 shown in FIG. 5B has via conductors 268 and conductor patterns 272 . The branch wiring 286 has via conductors 262 , conductor patterns 275 and via conductors 265 . The branch wiring 287 has conductor patterns 276 and via conductors 266 . 5B and the transmission terminal 352 of the memory controller 301 shown in FIG. 4A are arranged in the wiring layer 201 shown in FIG. are electrically connected by a conductor pattern of That is, the transmission terminal 352 of the memory controller 301 is soldered to a conductor pattern (not shown) arranged on the wiring layer 201 shown in FIG. The via conductor 265 and the receiving terminal 362 of the memory device 311 shown in FIG. 4A are electrically connected by a conductor pattern (not shown) arranged in the wiring layer 201 shown in FIG. there is That is, the receiving terminal 362 of the memory device 311 is soldered to a conductor pattern (not shown) arranged on the wiring layer 201 shown in FIG. The via conductor 266 and the receiving terminal 364 of the memory device 312 shown in FIG. 4A are electrically connected by a conductor pattern (not shown) arranged in the wiring layer 201 shown in FIG. there is That is, the receiving terminal 364 of the memory device 312 is soldered to a conductor pattern (not shown) arranged on the wiring layer 201 shown in FIG.

As shown in FIG. 4A, when viewed in the Z direction, the memory device 311 and the memory device 312 are arranged facing each other with a gap in the X direction. Therefore, as shown in FIG. 4B, the regions R2 and R3 face each other with a gap in the X direction. A plurality of via conductors 261 and a plurality of via conductors 262 are arranged between the region R2 and the region R3 in the X direction.

A plurality of via conductors 261 are arranged at intervals on a straight line L1, which is a virtual first straight line, when viewed in the Z direction. A plurality of via conductors 262 are arranged on a straight line L2, which is a virtual second straight line different from the straight line L1, while being spaced apart from each other when viewed in the Z direction. The straight line L1 and the straight line L2 are imaginary straight lines extending parallel to each other in the Y direction with an interval in the X direction. That is, a via conductor group made up of a plurality of via conductors 261 arranged side by side in the Y direction and a via conductor group made up of a plurality of via conductors 262 arranged side by side in the Y direction are spaced apart in the X direction. ing. The plurality of via conductors 261 and the plurality of via conductors 262 are arranged in a zigzag arrangement, offset from each other in the Y direction. By arranging via conductors 261 and 262 in this manner, printed wiring board 200 can be further miniaturized.

When viewed in the Z direction, the relative position of via conductor 262 to via conductor 261, the relative position of via conductor 265 to via conductor 263, and the relative position of via conductor 266 to via conductor 264 are the same. be. That is, the arrangement of via conductors 261 and 262, the arrangement of via conductors 263 and 265, and the arrangement of via conductors 264 and 266 are the same. Y of the via conductor group of the plurality of via conductors 261 and the plurality of via conductors 262, the via conductor group of the plurality of via conductors 263 and the plurality of via conductors 265, and the via conductor group of the plurality of via conductors 264 and the plurality of via conductors 266 The direction position is the same. Thereby, the wiring lengths of the conductor patterns 273, 274, 275, 276 can be shortened, and the printed wiring board 200 can be further miniaturized. In this embodiment, as shown in FIG. 5A, the conductor patterns 273 and 274 are formed linearly extending in the X direction. As shown in FIG. 5(b), the conductor patterns 275 and 276 are formed linearly extending in the X direction. Thereby, the printed wiring board 200 can be further miniaturized.

As shown in FIG. 5A, the portion of the conductor pattern 271 on the side of the via conductor 261 with respect to the portion 271-1 is bent in order to be connected to the via conductor 261. As shown in FIG. As shown in FIG. 5B, the portion of the conductor pattern 272 on the side of the via conductor 262 with respect to the portion 272-1 is bent in order to be connected to the via conductor 262. As shown in FIG. The bent portions of the conductor patterns 271 and 272 on the side of the via conductors 261 and 262 are arranged outside the via conductor group consisting of the plurality of via conductors 261 and the plurality of via conductors 262 . Since the conductor patterns 271 and 272 are arranged outside the via conductor group, the conductor patterns 273, 274, 275 and 276 drawn from the via conductor group are arranged so as not to short-circuit the conductor patterns 271 and 272. FIG. That is, since the conductor pattern 271 is arranged on the wiring layer 203 and the conductor pattern 272 is arranged on the wiring layer 204, the conductor patterns 273 and 275 are arranged on the wiring layer 203, and the conductor patterns 274 and 276 are arranged on the wiring layer 204. are placed.

Further, in this embodiment, the conductor pattern 275 and the conductor pattern 276 are formed to have the same wiring length. As a result, the length (electrical length) of the branch wiring 286 and the length (electrical length) of the branch wiring 287 are the same, and the occurrence of noise due to multiple reflection of electric signals can be suppressed.

FIG. 6A is a perspective view schematically showing part of the wiring 251 according to the first embodiment. FIG. 6B is a perspective view schematically showing part of the wiring 252 according to the first embodiment. FIG. 6C is a perspective view schematically showing a portion of the wirings 251 and 252 according to the first embodiment. As shown in FIG. 6A, the conductor pattern 271 of the wiring 251 is arranged in the wiring layer 203, the conductor pattern 273 of the wiring 251 is arranged in the wiring layer 203, and the conductor pattern 274 of the wiring 251 is arranged in the wiring layer. 204. As shown in FIG. 6B, the conductor pattern 272 of the wiring 252 is arranged on the wiring layer 204, the conductor pattern 275 of the wiring 252 is arranged on the wiring layer 203, and the conductor pattern 276 of the wiring 252 is arranged on the wiring layer. 204.

As shown in FIG. 6A, a virtual axis passing through the center of the via conductor 261 in the Z direction and extending in the Y direction is defined as an axis C1. When the wiring 251 is rotated by 180 degrees about the axis C1, the wiring 251 is placed in substantially the same arrangement as the wiring 252 shown in FIG. 6(b). As shown in FIG. 6(b), an imaginary axis line extending in the Y direction passing through the center of the via conductor 262 in the Z direction is defined as an axis line C2. When the wiring 252 is rotated by 180 degrees around the axis C2, the wiring 252 is placed in substantially the same arrangement as the wiring 251 shown in FIG. 6(a).

By arranging the wirings 251 and 252 shown in FIGS. 6A and 6B so that the via conductors 261 and 262 do not overlap each other, the wirings 251 and 252 are shifted in the X direction and the Y direction. can be prevented from shorting out. By arranging a plurality of the wirings 251 and 252 of such a combination at intervals in the Y direction, the regions R2 and R3 shown in FIG. 4B can be arranged close to each other. At that time, the conductor patterns 271 of the plurality of wirings 251 and the conductor patterns 272 of the plurality of wirings 252 are bent so as not to short-circuit each other. good.

(Comparative example)
FIG. 15A is a schematic diagram of wiring of a printed wiring board 200X when the printed circuit board of the comparative example is viewed in the Z direction. The printed wiring board 200X of the comparative example has six wiring layers, like the printed wiring board 200 shown in FIG. FIG. 15A shows a wiring layer 203X as the third layer and a wiring layer 204X as the fourth layer. In FIG. 15A, the conductor patterns arranged on the wiring layer 203X are indicated by solid lines, and the conductor patterns arranged on the wiring layer 204X are indicated by broken lines. FIG. 15B is a schematic diagram of wiring arranged in a wiring layer 203X of a printed wiring board 200X when the printed circuit board of the comparative example is viewed in the Z direction. FIG. 15C is a schematic diagram of wiring arranged in a wiring layer 204X of a printed wiring board 200X when the printed circuit board of the comparative example is viewed in the Z direction.

Each of the plurality of wirings 270X forming the address/command signal line 250X of the comparative example is a so-called T-branch wiring, but has substantially the same arrangement structure. A via conductor 264X is arranged in the region R1X corresponding to the memory controller, and via conductors 262X and 263X are arranged in regions R2X and R3X corresponding to the two memory devices, respectively. A via conductor 261X is arranged between the region R2X and the region R3X. The via conductors 264X and the via conductors 261X are connected by a conductor pattern 271X arranged on the wiring layer 204X. The via conductors 261X and 262X are connected by a conductor pattern 272X arranged on the wiring layer 203X. The via conductors 261X and 263X are connected by a conductor pattern 273X arranged on the wiring layer 203X.

The address/command signal line 250X of the comparative example is a bus wiring in which a plurality of wirings 270X having the same T-branch wiring structure are arranged. Therefore, the width of the bus wiring is widened in the X direction, the area of the printed wiring board 200X when viewed in the Z direction is wide, and the size of the printed wiring board 200X is increased. As a result, printed circuit boards and, in turn, electronic devices become larger. There is also a method of increasing the number of wiring layers to reduce the area of printed wiring board 200X when viewed in the Z direction, but this increases the manufacturing cost of printed wiring board 200X.

In the first embodiment, the conductor pattern 271 of the main wiring 280 and the conductor pattern 272 of the main wiring 285 are alternately arranged on the wiring layers 203 and 204, thereby reducing the number of wiring layers when viewed in the Z direction. The area of printed wiring board 200 can be reduced. That is, since the printed wiring board 200 can be miniaturized, the printed circuit board 100 can be miniaturized, and the network camera 500 can be miniaturized.

Further, by processing the image data signal generated by the image sensor 600 shown in FIG. can provide.

The area occupied by the address/command signal lines will be described below using numerical examples.
(Example 1)
FIG. 7 is a plan view showing the address/command signal lines 250 of the first embodiment. FIG. 8 is a perspective view showing the address/command signal line 250 of the first embodiment. In the first embodiment, the case where the address/command signal lines 250 made up of a total of eight wirings 251 and 252 with four wirings 251 and four wirings 252 has been described. In the first embodiment, six wirings 251 and six wirings 252 constitute an address/command signal line 250 with a total of 12 wirings 251 and 252. FIG. A terminating resistor (not shown) having a resistance value of 40 [Ω] is arranged at the branch point of the wirings 251 and 252 .

In Example 1, when viewed in the Z direction, the width of one main wire in the X direction is 0.075 [mm], and the distance between two main wires in the X direction is 0.225 [mm]. . When viewed in the Z direction, the X-direction width W1 occupied by the plurality of main wires 280 and 285 is 1.575 [mm], and the Y-direction length L1 is 15.116 [mm]. When the area occupied by the plurality of main wires 280 and 285 is regarded as a rectangle, its area S1 (W1×L1) is 23.808 [mm ² ].

When viewed in the Z direction, the width of one branch wiring is 0.075 [mm], and the distance between two branch wirings in the Y direction is 0.200 [mm]. When viewed in the Z direction, the Y-direction width W2 occupied by the branch wirings 281, 282, 286, and 287 is 3.100 [mm], and the X-direction length L2 is 15.920 [mm]. When the area occupied by the branch wirings 281, 282, 286, and 287 is regarded as a rectangle, its area S2 (W2×L2) is 49.352 [mm ² ]. Therefore, the area S (S1+S2) occupied by the address/command signal line 250 of Example 1 is 73.160 [mm ² ].

(Comparative example 1)
FIG. 16 is a plan view showing an address/command signal line 250X of Comparative Example 1. FIG. 17 is a perspective view showing an address/command signal line 250X of Comparative Example 1. FIG. In the above-described comparative example, the case where the address/command signal line 250X is composed of eight wirings 270X has been described. In Comparative Example 1, a case will be described in which an address/command signal line 250X is composed of 12 wirings 270X.

When viewed in the Z direction, the width of one main wiring in the X direction is 0.075 [mm], and the distance between two main wirings in the X direction is 0.225 [mm]. When viewed in the Z direction, the X-direction width W1X occupied by the plurality of main wires is 3.375 [mm], and the Y-direction length L1X is 14.762 [mm]. If the area occupied by a plurality of main wires is regarded as a rectangle, its area S1X (W1X×L1X) is 49.822 [mm ² ].

When viewed in the Z direction, the width of one branch wiring is 0.075 [mm], and the distance between two branch wirings in the Y direction is 0.200 [mm]. When viewed in the Z direction, the Y-direction width W2X occupied by the plurality of branch wirings is 3.100 [mm], and the X-direction length L2X is 17.710 [mm]. If the area occupied by a plurality of branch wirings is regarded as a rectangle, its area S2X (W2X×L2X) is 54.901 [mm ² ]. Therefore, the area SX (S1X+S2X) occupied by the address/command signal line 250X in Comparative Example 1 is 104.723 [mm ² ].

First, the main wiring of Example 1 and Comparative Example 1 will be compared and examined. The length L1 of Example 1 is slightly longer than the length L1X of Comparative Example 1 due to the wiring design, but the width W1 of Example 1 is less than half the width W1X of Comparative Example 1. Therefore, the area S1 of Example 1 can be made half or less of the area S1X of Comparative Example 1.

Example 1 and comparative example 1 will be compared and examined with respect to the branch wiring. The width W1 of the main wiring of Example 1 can be made narrower than the width W1X of the main wiring of Comparative Example 1. FIG. Accordingly, in the first embodiment, the two memory devices can be arranged with a small space therebetween, so that the length L2 of the first embodiment can be shortened with respect to the length L2X of the first comparative example. Therefore, the area S2 of Example 1 can be made smaller than the area S2X of Comparative Example 1. FIG.

While the area SX of Comparative Example 1 is 104.723 [mm ² ], the area S of Example 1 is 73.160 [mm ² ]. mm ² ] (30%). In FIG. 7, when viewed in the Z direction, the larger the overlapping portion between the region R4 of the main wiring 280 in the wiring layer 203 (FIG. 8) and the region R5 of the main wiring 285 in the wiring layer 204 (FIG. 8), the more the area can be reduced. Highly effective. By matching the region R4 and the region R5, the maximum area reduction effect can be obtained.

(Example 2)
As Example 2, in the configuration of the address/command signal line 250 of Example 1, a signal waveform was simulated using a simulator under the following dimensions. The simulator used was HyperLynx manufactured by Mentor Graphics. The transmission speed of the address signal was set to 1200 [Mbps] (600 [MHz] pseudorandom signal).

The layer structure of printed wiring board 200 in Example 2 will be described. The thickness of the copper foil forming the conductor patterns arranged on each of the wiring layers 201 to 206 shown in FIG. 3 was set to 0.012 [mm]. The thickness of the insulating layer between the copper foil of the wiring layer 201 and the copper foil of the wiring layer 202 was set to 0.060 [mm]. The thickness of the insulating layer between the copper foil of the wiring layer 202 and the copper foil of the wiring layer 203 was set to 0.060 [mm]. The thickness of the insulating layer between the copper foil of the wiring layer 203 and the copper foil of the wiring layer 204 was set to 0.200 [mm]. The thickness of the insulating layer between the copper foil of the wiring layer 204 and the copper foil of the wiring layer 205 was set to 0.060 [mm]. The thickness of the insulating layer between the copper foil of the wiring layer 205 and the copper foil of the wiring layer 206 was set to 0.060 [mm].

In Example 2, the lengths of the conductor pattern 275 of the branch wiring 286 and the conductor pattern 276 of the branch wiring 287 shown in FIG. 8 are made equal. The length of the conductor pattern 272 of the main wiring 285 was set to 17.54 [mm]. The length of the conductor pattern 275 of the branch wiring 286 was set to 5.30 [mm]. The length of the conductor pattern 276 of the branch wiring 287 was set to 5.30 [mm]. A conductor, which is not shown in the first embodiment, is arranged in the wiring layer 201 which is the surface layer, is electrically connected to the via conductor 265, and is connected to the receiving terminal 362 of the memory device 311 shown in FIG. The length of the pattern 293 was set to 2.51 [mm]. A conductor, which is not shown in the first embodiment, is arranged in the wiring layer 201 which is the surface layer, is electrically connected to the via conductor 266, and is joined to the receiving terminal 364 of the memory device 312 shown in FIG. The length of the pattern 294 was set to 2.51 [mm].

FIG. 9A is a simulation waveform diagram of a signal received by the receiving terminal 362 of the memory device 311 in the second embodiment. FIG. 9B is a simulation waveform diagram of the signal received at the receiving terminal 364 of the memory device 312 in the second embodiment. The opening of the eye pattern was measured in FIGS. 9(a) and 9(b). The height H of the eye pattern was 474 [mV]. The width T of the eye pattern was 820 [psec].

(Comparative example 2)
As Comparative Example 2, in the configuration of the address/command signal line 250X of Comparative Example 1, a waveform simulation was performed using the same simulator as in Example 1 under the following dimensions. The layer structure of the printed wiring board of Comparative Example 2 was the same as the layer structure of the printed wiring board of Example 2.

In the wiring 270X shown in FIG. 17, the conductor pattern 272X in one branch wiring and the conductor pattern 273X in the other branch wiring are often different in length. The length of the conductor pattern 271X of the main wiring was set to 17.54 [mm]. The length of the conductor pattern 272X of one branch wiring was set to 4.59 [mm]. The length of the conductor pattern 273X of the other branch wiring was set to 7.45 [mm]. The length of the conductor pattern 274X, which is arranged on the wiring layer 201X, which is the surface layer, is electrically connected to the via conductor 262X, and to which the signal terminal of the memory device 311 is joined, was set to 2.51 [mm]. The length of the conductor pattern 275X arranged on the wiring layer 201X, which is the surface layer, electrically connected to the via conductor 266X, and joined to the signal terminal of the memory device 312 was set to 2.51 [mm]. A terminating resistor (not shown) having a resistance value of 40 [Ω] is placed at the branch point P shown in FIG. 17 .

FIG. 18A is a simulation waveform diagram of a signal received by the receiving terminal of the memory device 311 in Comparative Example 2. FIG. FIG. 18(b) is a simulation waveform diagram of the signal received by the receiving terminal of the memory device 312 in Comparative Example 2. FIG. The opening of the eye pattern was measured in FIGS. 18(a) and 18(b). The height H of the eye pattern was 381 [mV]. The width T of the eye pattern at the termination voltage of 600 [mV] was 814 [psec].

From the above simulation results, in the configuration of Example 2, the height of the eye pattern was improved by 93 [mV] and the width of the eye pattern was improved by 6 [psec] as compared with the configuration of Comparative Example 2. It was confirmed that multiple reflection of signals can be suppressed and noise can be reduced by using branch lines of equal length.

[Second embodiment]
A printed circuit board according to the second embodiment will be described. The printed circuit board of the second embodiment differs from that of the first embodiment in the configuration of a part of the first wiring in the printed wiring board. The printed wiring board will be described below.

FIG. 10(a) is a schematic diagram showing the first wiring and the second wiring of the printed wiring board according to the second embodiment. FIG. 10(b) is a schematic diagram showing the first wiring of the printed wiring board according to the second embodiment. FIG. 10(c) is a schematic diagram showing the second wiring of the printed wiring board according to the second embodiment. A printed wiring board 200A of the second embodiment has a wiring 251A that is a first wiring and a wiring 252 that is a second wiring and has the same configuration as in the first embodiment.

The wiring 251A has via conductors 267, conductor patterns 271, via conductors 261, via conductors 263, conductor patterns 274, and via conductors 264, as in the first embodiment. Wiring 251A is arranged in wiring layer 203, which is the first layer, and has conductor pattern 273A, which is a third conductor pattern, electrically connecting via conductors 261 and 263. The configuration of this conductor pattern 273A is different from the conductor pattern 273 of the first embodiment. Other configurations are the same as those of the first embodiment.

The conductor pattern 273 of the first embodiment is a linear conductor pattern, but the conductor pattern 273A of the second embodiment is a meandering conductor pattern and has a longer wiring length (electrical length) than the conductor pattern 273. It's becoming

FIG. 11(a) is a perspective view schematically showing a portion of the wiring 251A according to the second embodiment. FIG. 11(b) is a perspective view schematically showing a portion of the wiring 252 according to the second embodiment. FIGS. 11A and 11B show a wiring layer 203 as a first layer and a wiring layer 204 as a second layer.

As shown in FIG. 11A, a branch point P1 where the main wiring 280 branches to the branch wirings 281A and 282 is a portion of the wiring layer 203 in the via conductor 261. As shown in FIG. On the other hand, as shown in FIG. 11B, a branch point P2 where the main wiring 285 branches to the branch wirings 286 and 287 is a portion of the wiring layer 204 in the via conductor 262 . In the branch wiring 286 of the wiring 252, the signal is transmitted from the wiring layer 204 to the wiring layer 203 via the via conductor 262 and the conductor pattern 275 to the memory device. In the branch wiring 287 of the wiring 252 , the signal is transmitted to the memory device via the conductor pattern 276 from the wiring layer 204 to the wiring layer 203 via the via conductor 266 . Therefore, by equalizing the wiring lengths of the conductor patterns 275 and 276, the electrical lengths of the branch wirings 286 and 287 can be equalized.

In the branch wiring 281A of the wiring 251A, the signal passes through the conductor pattern 273A without passing through the via conductor 261 and is transmitted to the memory device. In the branch wiring 282 of the wiring 251A, the signal is transmitted from the wiring layer 203 to the wiring layer 204 via the via conductor 261 to the conductor pattern 274, and further from the wiring layer 203 to the wiring layer 204 via the via conductor 264. and transmitted to the memory device. In the branch wiring 282, the signal travels back and forth between the wiring layer 203 and the wiring layer 204, which causes a corresponding delay time. In the second embodiment, the conductor pattern 273A of the branch wiring 281A is meander-shaped, and the timing of the signal reaching the memory device through the branch wiring 281A is adjusted to match the timing of the signal reaching the memory device through the branch wiring 282. ing.

That is, by forming the conductor pattern 273A in a meandering shape, the electrical lengths of the branch wiring 281A and the branch wiring 282 can be equalized while reducing the area occupied by the address/command signal line 250A on the printed wiring board 200A. can. As a result, multiple reflection noise caused by unequal length branching is suppressed, the quality of the signal waveform is improved, and faster signal transmission can be realized.

(Example 3)
FIG. 12 is a plan view showing the address/command signal lines 250A of the third embodiment. FIG. 13 is a perspective view showing the address/command signal line 250A of the third embodiment. In the second embodiment, the case where the address/command signal line 250A composed of the four wirings 251A and the four wirings 252 in total eight wirings 251A and 252 has been described. In the third embodiment, six wirings 251A and six wirings 252 constitute an address/command signal line 250A consisting of twelve wirings 251A and 252 in total.

The number of layers and the dimensions of the layers of the printed wiring board of Example 3 were the same as those of Example 2. In the configuration of the address/command signal line 250A shown in FIGS. 12 and 13, signal waveform simulation was performed using a simulator. The simulator used was HyperLynx manufactured by Mentor Graphics. The transmission speed of the address signal was set to 1200 [Mbps] (600 [MHz] pseudorandom signal).

The length of the conductor pattern 271 of the main wiring 280 was set to 17.26 [mm]. The length of the conductor pattern 273A of the branch wiring 281A was set to 6.45 [mm] (44.6 [psec]). The length of the conductor pattern 274 of the branch wiring 282 was set to 5.30 [mm] (36.6 [psec]). A conductor, which is not shown in the second embodiment, is arranged in the wiring layer 201 which is the surface layer, is electrically connected to the via conductor 263, and is connected to the receiving terminal 361 of the memory device 311 shown in FIG. The length of the pattern 291 was set to 2.51 [mm]. A conductor, which is not shown in the second embodiment, is arranged in the wiring layer 201 which is the surface layer, is electrically connected to the via conductor 264, and is joined to the receiving terminal 363 of the memory device 312 shown in FIG. The length of the pattern 292 was set to 2.51 [mm].

The measured delay time of the via conductor 261 was 4 [psec]. Therefore, a meander-shaped conductor pattern 273A, which is longer than the conductor pattern 274 by a length of 1.15 [mm] corresponding to the delay time of 8 [psec] for two via conductors 261, is used.

FIG. 14(a) is a simulation waveform diagram of a signal received by the receiving terminal 361 of the memory device 311 in the third embodiment. FIG. 14(b) is a simulation waveform diagram of a signal received at the receiving terminal 362 of the memory device 312 in the third embodiment. The opening of the eye pattern was measured in FIGS. 14(a) and 14(b). The height H of the eye pattern was 538 [mV]. The width T of the eye pattern was 825 [psec].

From the above simulation results, in the configuration of Example 3, the height of the eye pattern was improved by 157 [mV] and the width of the eye pattern was improved by 11 [psec] as compared with the configuration of Comparative Example 2. It was confirmed that multiple reflection of signals can be suppressed and noise can be reduced by using branch lines of equal length.

The present invention is not limited to the embodiments described above, and many modifications are possible within the technical concept of the present invention. Moreover, the effects described in the embodiments are merely enumerations of the most suitable effects produced by the present invention, and the effects of the present invention are not limited to those described in the embodiments.

In the above-described embodiments, the case where the electronic device is a network camera has been described, but the present invention is not limited to this. For example, it can be applied to various electronic devices such as portable digital cameras, smartphones, and the like, which require small external shapes and high-quality image data.

In the above-described embodiment, the case where the printed wiring board has a plurality of first wirings and a plurality of second wirings has been described, but the present invention is not limited to this. That is, the printed wiring board may have one first wiring and one second wiring. For example, an address/command signal line may have at least one first wiring and one second wiring. Moreover, not only the address/command signal line, but bus wiring other than the address/command signal line may have the first wiring and the second wiring.

In the above-described embodiment, the case where the via conductor 261 is preferably arranged on the first straight line L1 and the via conductor 262 is arranged on the second straight line L2 has been described. However, it is not limited to this. For example, the via conductors 261 may be arranged in a staggered manner, and the via conductors 262 may be arranged in a staggered manner.

In the above-described embodiments, elements such as a memory controller and a memory device are mounted on a printed wiring board to form a printed circuit board. However, before the printed circuit board is manufactured, these elements are not yet mounted on the printed wiring board. Even if the printed wiring board is not mounted with elements, the wiring structure is the same as that of the above-described embodiment, and the same effect as that of the above-described embodiment can be obtained.

DESCRIPTION OF SYMBOLS 100... Printed circuit board 200... Printed wiring board 201... Wiring layer (surface layer) 203... Wiring layer (first layer) 204... Wiring layer (second layer) 250... Address/command signal line 251... Wiring (first wiring) 252 Wiring (second wiring) 261 Via conductor (first via conductor) 262 Via conductor (second via conductor) 263 Via conductor (third via conductor) 264 ... via conductor (fourth via conductor), 265 ... via conductor (fifth via conductor), 266 ... via conductor (sixth via conductor), 271 ... conductor pattern (first conductor pattern), 272 ... conductor pattern (second conductor pattern), 273 ... conductor pattern (third conductor pattern), 274 ... conductor pattern (fourth conductor pattern), 275 ... conductor pattern (fifth conductor pattern), 276 ... conductor pattern (sixth conductor pattern), 301 ... Memory controller (first element) 311 Memory device (second element) 312 Memory device (third element) 351 Transmission terminal (first transmission terminal) 352 Transmission terminal (second transmission terminal) 361... Receiving terminal (first receiving terminal), 362... Receiving terminal (second receiving terminal), 363... Receiving terminal (third receiving terminal), 364... Receiving terminal (fourth receiving terminal), 500... Network camera (electronic device), R1... area (first area), R2... area (second area), R3... area (third area), R4... area (fourth area), R5... area (fifth area)

Claims (12)

a printed wiring board comprising first and second layers spaced apart from each other;
A first element , a second element , and a third element provided on the printed wiring board,
The printed wiring board is
a plurality of first wirings electrically connecting the first element , the second element and the third element ;
a plurality of second wirings electrically connecting the first element , the second element and the third element and different from the first wiring ,
Each of the plurality of first wirings,
Arranged across the first layer and the second layer, in plan view from a direction perpendicular to the main surface of the printed wiring board, a first region where the first element is located, a second region where the second element is located a first via conductor disposed between the second region and the third region outside the third region in which the second region and the third element are located;
a first conductor pattern disposed on the first layer and extending from the first via conductor toward the first region in plan view;
each of the plurality of second wirings,
arranged across the first layer and the second layer and arranged between the second region and the third region outside the first, second and third regions in plan view a second via conductor;
a second conductor pattern disposed on the second layer and extending from the second via conductor toward the first region in plan view;
The printed circuit, wherein, in the plan view, a fourth region in which the plurality of first conductor patterns are arranged is arranged so as to overlap a fifth region in which the plurality of second conductor patterns are arranged. board. 2. The printed circuit board according to claim 1, wherein at least one of the plurality of first conductor patterns and at least one of the plurality of second conductor patterns are arranged to overlap each other in plan view. . In the plan view, the plurality of first via conductors are arranged on a first straight line at intervals, and the plurality of second via conductors are arranged on a second straight line different from the first straight lines at intervals. 3. The printed circuit board according to claim 1, wherein the printed circuit board is arranged with a space therebetween. Each of the plurality of first wirings,
a third conductor pattern disposed on the first layer and extending from the first via conductor toward the second region in plan view;
a fourth conductor pattern disposed on the second layer and extending from the first via conductor toward the third region in plan view;
each of the plurality of second wirings,
a fifth conductor pattern disposed on the first layer and extending from the second via conductor toward the second region in plan view;
and a sixth conductor pattern disposed on the second layer and extending from the second via conductor toward the third region in plan view. A printed circuit board as described. The printed wiring board includes a surface layer closer to the first layer than the second layer,
Both the second element and the third element are provided on the surface layer,
Each of the plurality of first wirings,
a third via conductor arranged across the surface layer and the first layer, arranged inside the second region in plan view, and connected to the third conductor pattern;
a fourth via conductor arranged across the surface layer and the second layer, arranged inside the third region in plan view, and connected to the fourth conductor pattern;
each of the plurality of second wirings,
a fifth via conductor arranged across the surface layer and the first layer, arranged inside the second region in plan view, and connected to the fifth conductor pattern;
a sixth via conductor arranged across the surface layer and the second layer, arranged inside the third region in plan view, and connected to the sixth conductor pattern. 5. The printed circuit board of claim 4. 6. The printed circuit board according to claim 4, wherein said fifth conductor pattern and said sixth conductor pattern are formed to have the same wiring length. 7. The printed circuit board according to claim 4, wherein said third conductor pattern is formed in a meandering shape. the first device is a memory controller;
A printed circuit board as claimed in any preceding claim, wherein the second and third elements are memory devices. 9. The print according to claim 8, wherein said first element transmits an address signal and a command signal to said second element and said third element through said plurality of first wirings and said plurality of second wirings. circuit board. Including a first layer and a second layer spaced apart from each other, a first region where the first element is arranged and a second region where the second element is arranged in a plan view from a direction perpendicular to the main surface A printed wiring board having a region and a third region in which a third element is arranged,
a plurality of first wirings for electrically connecting the first element , the second element , and the third element ;
a plurality of second wirings electrically connecting the first element , the second element and the third element and different from the first wiring ,
Each of the plurality of first wirings,
arranged across the first layer and the second layer and arranged between the second region and the third region outside the first, second and third regions in plan view a first via conductor;
a first conductor pattern disposed on the first layer and extending from the first via conductor toward the first region in plan view;
each of the plurality of second wirings,
arranged across the first layer and the second layer and arranged between the second region and the third region outside the first, second and third regions in plan view a second via conductor;
a second conductor pattern disposed on the second layer and extending from the second via conductor toward the first region in plan view;
The printed wiring characterized in that, in the plan view, a fourth region in which the plurality of first conductor patterns are arranged is arranged so as to overlap a fifth region in which the plurality of second conductor patterns are arranged. board. a housing;
The printed circuit board according to any one of claims 1 to 9 arranged in the housing. a housing;
A printed circuit board according to any one of claims 1 to 9, arranged in the housing;
an imaging device disposed within the housing and electrically connected to the printed circuit board.

Images