JP4707446B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of semiconductor elements and a capacitance element (capacitor) necessary for them are accommodated in one package.

  In an electronic circuit board applied to an electronic device, a control semiconductor element including a logic element such as an MPU (Micro Processing Unit) is mounted, and the control semiconductor element cooperates with a memory element (memory). Often works. That is, in many cases, a circuit board (motherboard) on which a logic element is mounted has a plurality of storage elements mounted thereon, and a system for processing data in the storage element by the logic elements is often constructed.

  The plurality of storage elements are mounted on a single substrate and configured as a memory module such as a DIMM (Dual Inline Memory Module), and the memory module is inserted into a socket provided on the motherboard.

  The semiconductor device on which the logic element is mounted and the memory module exchange data via the mother board.

  When the memory module and the logic element are separately mounted on the mother board, it is necessary to separately provide a region for arranging the memory module and the logic element on the mother board. Further, it is necessary to form wiring for connecting the memory module and the logic element on the mother board. For this reason, the entire system including the mother board becomes large, wiring within the mother board becomes complicated, and the number of wiring layers on the mother board increases.

  Therefore, a multi-chip module (MCM) has been proposed as a semiconductor device that incorporates a system composed of a logic element and a plurality of memory elements into one module to achieve high integration, small size, and high processing speed. Yes. As the structure of the MCM, for example, a logic element is mounted almost at the center of a substrate, and a plurality of peripheral elements such as memory elements are mounted around the logic element. When connecting multiple peripheral elements arranged around the logic element to the logic element, the wiring length between each peripheral element and the logic element is made equal to match the impedance, and the input / output timing of the signal is adjusted. It needs to be adjusted.

  Therefore, a peripheral element is arranged in the vicinity of each side of a quadrilateral (rectangular) logic element, and the wiring length from the clock signal output terminal of the logic element to the clock terminal of each peripheral element is made equal. A configuration has been proposed (see, for example, Patent Document 1).

  On the other hand, a decoupling capacitor for reducing power supply noise is usually mounted on each of the logic element and the peripheral element in the MCM as described above. There is known a semiconductor device in which one semiconductor element (logic element) and a plurality of capacitance elements (peripheral elements) necessary for the semiconductor element are mounted on a substrate. In such a semiconductor device, a semiconductor element is mounted substantially at the center of the substrate, and a plurality of capacitive elements are arranged around the semiconductor element so as to surround the semiconductor element. Accordingly, the wiring on the substrate is often a so-called fan-out wiring that extends radially from the semiconductor element to the periphery.

  On the other hand, external connection terminals are disposed on the back surface of the substrate by solder balls or the like, and the semiconductor device is mounted on a substrate such as a mother board. The semiconductor device has a planar arrangement structure as shown in FIG. 1 and a cross-sectional structure shown in FIG. FIG. 2 shows a II-II cross section of FIG. In such a structure, the semiconductor element 1 is mounted almost at the center of the substrate 2, and the capacitive element 3 is mounted around the four sides of the semiconductor element 1. The capacitive element 3 is a decoupling capacitor connected between the power supply line and the ground line of the semiconductor element 1 for performing noise removal.

  As shown in FIG. 2, the semiconductor element 1 is flip-chip mounted on the substrate 2, and the capacitive element 3 is solder-connected to the electrode of the substrate 2. A heat spreader 4 is mounted on the back surface of the semiconductor element 1. (FIG. 1 shows a state in which the heat spreader 4 is removed.) In addition, a plurality of solder balls 5 constituting external connection terminals are provided on the back surface of the substrate 2. The semiconductor device is mounted on a mother board or the like via the solder ball 5.

  In such a semiconductor device, as indicated by a dotted line in FIG. 1, the surface of the substrate 2 is divided into regions extending radially from the four sides of the semiconductor element 1, and the capacitive element 3 is disposed in each region. At the same time, wirings connecting the semiconductor device 1 and the solder balls 5 are arranged radially via multilayer wirings in the region.

  In such a structure, since the capacitive element 3 is disposed around the semiconductor element 1, the area of the substrate 2 becomes large. Therefore, in the MCM in which peripheral elements such as memory elements are arranged around the logic element, a region for mounting a decoupling capacitor is provided between the logic element and the peripheral element, and the size of the MCM itself is also large. turn into.

Thus, a semiconductor device has been proposed in which a peripheral element mounting area on the substrate is reduced by embedding a peripheral element such as a capacitor element in the substrate directly below the semiconductor element on the substrate on which the semiconductor element is mounted (for example, , See Patent Document 2).
JP 2001-177046 A JP-A-2005-11837

  In the semiconductor device described in Patent Document 1 described above, four memory elements are arranged around the logic element 7 mounted on the wiring board 2, and the logic element 7 corresponding to each of the four memory elements. A configuration is disclosed in which the clock wiring length from is equal.

  In recent years, while the amount of data processing in electronic devices has increased, there has been a demand for further speeding up of the processing of the data. For this reason, the capacity of storage elements connected to one logic element has increased, and a plurality of There is a tendency to be realized.

  When the number of memory elements connected to one logic element is increased, for example, when eight memory elements are connected to one logic element, the wiring configuration described in Patent Document 1 is difficult. In the technique disclosed in Patent Document 1, the object of equal-length wiring is a clock signal wiring, and wiring to other signal terminals is not taken into consideration.

  On the other hand, in the semiconductor device disclosed in Patent Document 2, it is disclosed that a capacitive element is disposed immediately below one semiconductor element mounted on a substrate. The arrangement of the capacitor elements corresponding to each of the storage elements to be processed is not considered. In general, the MCM substrate is a multilayer substrate, and wiring is provided in multiple layers, so that it is difficult to embed a large number of peripheral elements in the substrate.

  The present invention has been made in view of the above-described problems. In a semiconductor device configured by arranging a plurality of storage elements around a semiconductor element such as a logic element mounted on one main surface of a substrate. The present invention provides a configuration in which semiconductor elements such as logic elements and memory elements can be effectively mounted on a smaller area substrate with a high degree of integration.

  In addition, the present invention provides a wiring configuration capable of transmitting and receiving signals between a logic element and a memory element mounted on the substrate at a higher speed.

  Furthermore, the present invention provides a capacitor element applied to the logic element and a capacitor element applied to the memory element, without restricting the arrangement and mounting of the logic element and the memory element, and each of the logic elements to be targeted. The present invention provides a structure that is mounted and arranged closer to the storage element. The present invention has a configuration in which a plurality of storage elements constituting a large-capacity storage element unit and a logic element are mounted and arranged on a small-area substrate with high mounting density, and the logic element and the storage element It is an object of the present invention to provide a semiconductor device that can exchange signals between them at high speed.

In order to achieve the above object, according to the present invention, a substrate, a first semiconductor element mounted on one main surface of the substrate, and a first semiconductor surface mounted on one main surface of the substrate, A plurality of memory elements mounted around the semiconductor element; and a wiring disposed on the substrate and electrically connecting the first semiconductor element and the memory element. Around the semiconductor element, each of the four virtual regions set in parallel to each side outside the four outer sides of the first semiconductor element has 2 n storage elements (n is 1 is a natural number of 1 or more), and a recess is provided in a region corresponding to the first semiconductor element on the other main surface of the substrate, and the central portion of the recess includes the first semiconductor. A plurality of first capacitive elements electrically connected to the element are disposed and around the first capacitive element Wherein a plurality of second capacitive element electrically connected to said memory elements arranged therein are provided.

  In the semiconductor device according to the present invention, it is preferable that an address terminal of a memory element disposed in each of the virtual regions and an address control terminal of the first semiconductor element are connected to each other by an equal length wiring. In addition, it is preferable that a command input terminal of a memory element disposed in each of the virtual regions and a command output terminal of the first semiconductor element are connected to each other by an equal length wiring. Further, the memory element may be provided with an address input terminal and a command input terminal placed at a position far from the first semiconductor element.

  As described above, according to the present invention, it is possible to efficiently arrange one semiconductor element and a plurality of memory elements and connect them with a star wiring without using a termination resistance element, and a functional unit including a processor. It is possible to provide a semiconductor device having a single memory system that is miniaturized as a simple memory module. As a result, wiring on a substrate such as a mother board on which a semiconductor device is mounted can be simplified and the number of layers of the substrate can be reduced, which simplifies the design of the substrate of the electronic device and contributes to cost reduction.

  In addition, since the connection between the semiconductor element as the processor and the memory element as the memory can be achieved only by the wiring in the substrate of the semiconductor device without going through the substrate wiring such as a mother board, the wiring length becomes very short, Access time for writing and reading from the semiconductor element to the memory element is shortened. Therefore, processing speed is improved by high-speed data transfer, and throughput is improved.

  Furthermore, by providing a concave element on the back surface of the substrate and mounting a capacitor element such as a capacitor element, the capacitor element can be disposed immediately below the semiconductor element mounted on the front side of the substrate. And in close proximity to the storage element. Providing the recess prevents the capacitive element from protruding from the external connection terminal, and the capacitive element does not get in the way when mounting the semiconductor device via the external connection terminal. Further, by providing the recess, the capacitor can be made closer to the semiconductor element and the memory element.

  Next, embodiments of the present invention will be described with reference to the drawings.

  A semiconductor device 10 according to the first embodiment of the present invention is shown in FIGS. FIG. 4 shows an XX cross section of FIG.

  The semiconductor device 10 includes a semiconductor element 12 mounted on one main surface of a substrate 11 and a plurality of storage elements (memory elements) 13 disposed on the one main surface and around the semiconductor element 12. And capacitive elements (capacitors) 15A and 15B disposed in the recesses 14 disposed in the region located on the other main surface of the substrate 11 and immediately below the semiconductor element 12, and further including the substrate 11 is provided with an external connection terminal 16 around the recess 14 on the other main surface.

  The substrate 11 is an insulating substrate made of glass epoxy or the like, and a multilayer wiring is formed inside. The semiconductor element 12 mounted on one main surface (front surface) of the substrate 11 is a logic element such as an MPU (Micro Processing Unit) or a so-called ASIC (Application Specific Integrated Circuit). 11 is flip-chip mounted in a substantially central region.

  The memory element 13 is a semiconductor memory element such as a DRAM (Dynamic Random Access Memory) or a flash memory, and is arranged in the vicinity of the periphery of the semiconductor element 12 and flips to the substrate 11 like the semiconductor element 12. Chip mounted. A terminal of the memory element 13 is electrically connected to a corresponding terminal of the semiconductor element 12 through a wiring layer disposed in the substrate 11. Input / output of signals between the storage element 13 and the semiconductor element 12 is performed via wiring inside the substrate 11.

  On the other hand, in the other main surface (back surface) of the substrate 11, a plurality of capacitive elements (capacitors) are disposed in the recesses 14 disposed in the corresponding regions (regions immediately below) corresponding to the semiconductor elements 12. 15A and 15B are mounted and fixed. The capacitive element 15 </ b> A is a capacitive element for the semiconductor element 12, and the capacitive element 15 </ b> B is a capacitive element for the storage element 13. The arrangement configuration of the capacitive elements 15A and 15B in the recess 14 will be described later.

  Further, on the other main surface of the substrate 11, solder balls 16 serving as external connection terminals are formed in an array in an area excluding the recess 14, and the semiconductor elements 12 and the memory elements 13 are arranged in an array. The terminals are electrically connected to corresponding solder balls 16 through wiring layers in the substrate 11.

  Therefore, when the semiconductor device 10 is mounted and connected to the mother board via the solder ball 16, signals to the semiconductor element 12 and the memory element 13 via the solder ball 16 (actually melted and solidified solder ball). I / O and / or power supply is performed. Note that a heat radiating plate (heat spreader) 17 is attached to the back surface of the semiconductor element 12 to release heat generated during operation of the semiconductor element 12 to the surroundings.

  In the semiconductor device 10 having such a configuration, the region around the semiconductor element 12 on the first main surface (front surface) of the substrate 11 has four regions 51 to 51 as shown in FIG. In each area, an even number (two in the present embodiment) of storage elements 13 are arranged and mounted. Regions where the storage element 13 is mounted and arranged are shown in (b) to (i).

  In the configuration shown in FIG. 3, the region 51 in contact with one side (first side 12-1) of the rectangular region a where the semiconductor element 12 is arranged is close to the first side 12-1. Of two sides (second side 12-2 and fourth side 12-4) sandwiching the first side 12-1 and extending the second side 12-2 Extends in the direction of the fourth side 12-4 beyond the fourth side 12-4.

  Similarly, a region 52 in contact with one side (second side 12-2) of the rectangular region a where the semiconductor element 12 is disposed extends in parallel with the second side 12-2). At the same time, of the two sides (the first side 12-1 and the third side 12-3) sandwiching the second side 12-2, the first side 12 extends from the extended portion of the third side 12-3. Extends in the direction of -1 beyond the first side 12-1.

  In the rectangular region a, the region 53 in contact with the side 12-3 and the region 54 in contact with the side 12-4 are arranged in the same manner. Note that the setting of these four areas is not a physical division but a virtual division performed for the purpose of arranging the storage elements 13, and the areas 51 to 54 are virtual areas.

  In the semiconductor device 10, two memory elements 13 are mounted in each of the areas 51 to 54 (for example, the memory elements 13 (b) and (c) are mounted in the area 51), and the semiconductor The number of storage elements 13 in the entire device 10 is 4 × 2 = 8. In the arrangement configuration of the memory elements 13 according to the present invention, the number of the memory elements 13 arranged in one region is 2 to the nth power, and the example shown in FIG. Yes. The reason why 2 n power elements, that is, an even number of memory elements 13 are mounted and arranged in each of the areas 51 to 54 is to increase the storage capacity by arranging two memory elements 13 in one area. It is in.

  Further, by connecting the two memory elements as a pair to the semiconductor element 12 by so-called star connection, each of the plurality of memory elements 13 and the semiconductor element 12 has a substantially equal length of wiring (etc. This is for connection by a long wiring.

  In the arrangement of the semiconductor element 12 and the memory element 13 shown in FIG. 3, the electrical connection configuration between the memory elements 13 and between the semiconductor elements 12 is schematically shown in FIG.

  In the figure, two memory elements 13 (b) and (c) in a region 51 are connected to each other by wiring 18-1 between the corresponding electrode terminals in the region 51.

  The two storage elements 13 (d) and (e) in the region 52 adjacent to the region 51 are connected to each other between the corresponding electrode terminals by the wiring 18-2 in the region 52. . Then, the midpoint C5 of the wiring 18-1 connecting the pair of storage elements 13 (b) and (c) in the region 51 and the wiring 18 connecting the pair of storage elements 13 (d) and (e) in the region 52. -2 is connected to the midpoint C6 by the wiring 18-3. The midpoint C7 of the wiring 18-3 is electrically connected to a predetermined terminal of the semiconductor element 12 through the wiring 18-4. Thus, each of the memory elements 13 (b) to (e) is connected to one corresponding terminal of the semiconductor element 12 by the wirings 18-1, 18-2, 18-3, and 18-4.

In this configuration, the wiring 18-1 connecting the pair of storage elements 13 (b) and (c) and the wiring 18-2 connecting the other pair of storage elements 13 (d) and (e) are as follows. The wiring length is substantially equal. Also, the connection point C5 between the wiring 18-1 and one end of the wiring 18-3 is the midpoint of the wiring 18-1, and therefore the connection of the storage element 13 (b) on one end side of the wiring 18-1 as viewed from C5. the distance _{l 1} to the point C1, the distance _{l 2} before the connection point C2 on the other end side of the storage element 13 of the wiring 18-1 (c) is set to equal length.

Similarly, the connection point C6 between the wiring 18-2 and the other end of the wiring 18-3 is the middle point of the wiring 18-2, and the storage element 13 (d) on the one end side of the wiring 18-2 as viewed from the connection point C6. the distance _{l 3} before the connection point C3 of), the distance _{l 4} to a connection point C4 at the other end of the memory element 13 of the wiring 18-2 (e) is set to equal length. Therefore, the wiring lengths l ₁ , l ₂ , l ₃ , and l ₄ are set to be substantially equal.

Furthermore, the connection point C7 between the wiring 18-3 and one end of the wiring 18-4 is the midpoint of the wiring 18-3, and the connection point with the wiring 18-1 at one end of the wiring 18-3 as viewed from the connection point C7. distance _{L 1} to C5 are set to a length equal to the distance _{L 2} to the connecting point C6 of the wiring 18-2 at the other end of the wire 18-3. The other end of the wiring 18-4 is electrically connected to a predetermined terminal of the semiconductor element 12 (a).

  Such a wiring / connection configuration is called a star connection, and the wiring length from a predetermined terminal of the semiconductor element 12 (a) to each of the plurality of storage elements 13 (b) to (e) connected thereto is as follows. equal. Accordingly, the impedance of the wiring for each of the storage elements 13 (b) to (e) is also equalized, and it is not necessary to install a termination resistance element for adjusting the impedance of the wiring to the semiconductor element 12 (a).

  The memory elements 13 (f) to (i) disposed in the other regions 53 and 54 are also connected to corresponding terminals of the semiconductor element 12 (a) with the same equal-length wiring configuration. Therefore, as shown in FIG. 5, all the memory elements 13 (b) to (i) can be made to have the same length with respect to the semiconductor element 12 (a). The semiconductor device 10 including the element 12 and the memory element 13 can be operated.

  In the connection configuration shown in FIG. 5, the functional block in the semiconductor element 12 and the unit composed of (b) to (e) of the memory element 13 operate as one unit, and other units in the semiconductor element 12 The functional block and the unit composed of (f) to (i) of the storage element 13 operate in one unit. The two units operate individually, but of course there are cases where both units cooperate.

  As described above, the region 52 in contact with the second side 12-2 of the semiconductor element 12 (a) extends in parallel with the second side 12-2 and extends in parallel with the second side 12-2. Among the two sides (first side 12-1 and third side 12-4) sandwiching 2, the first side in the direction from the extension of the third side 12-3 to the first side 11-1 It extends beyond the side 11-1. That is, the region 52 corresponds to a region obtained by rotating the region 51 by 90 degrees clockwise with respect to the semiconductor device 12. Similarly, the region 53 and the region 54 constitute 90 degree rotational symmetry. Of course, these regions 51 to 54 may be extended in the clockwise direction as shown in FIG.

  According to this embodiment, one semiconductor element 12 and a plurality (eight) storage elements 13 are efficiently arranged on one substrate. On the other hand, by connecting the semiconductor element 12 and the plurality of memory elements 13 via an equal length wiring formed with a star connection, there is no need to provide a termination resistor in the semiconductor element 12. . Therefore, the semiconductor device 10 as a more miniaturized memory system can be provided as a functional memory module including the semiconductor element 12 without increasing the size of the semiconductor element. As a result, wiring on a substrate such as a motherboard on which the semiconductor device 10 is mounted can be simplified, the number of layers of the substrate can be reduced, and the design of the substrate of the electronic device can be simplified to reduce cost. Contribute to.

  In addition, since the electrical connection between the semiconductor element 12 as the logic element and the memory element 13 is performed by wiring in the substrate 11, the wiring length between the two is very short. The access time required for writing or reading data to or from the memory is greatly reduced. Therefore, high-speed data transfer is possible, the processing speed is improved, and the throughput is greatly improved.

Next, an example in which the configuration of the semiconductor device according to the first embodiment is applied to a memory module will be described. In the memory module, an ASIC element is applied as the semiconductor element 12 and an SDRAM (Synchronous DRAM, Synchronous DRAM) is used as the memory element 13.
Eight Dynamic Random Access Memory) were applied. The planar outer dimension of the substrate 11 of this semiconductor device is a standard 47.5 mm × 47.5 mm, and the planar outer dimension of the ASIC element 12 is 13.72 mm × 13.72 mm.

  As described above, by connecting the ASIC element 12 and the plurality of storage elements 13 with equal length wiring, it is not necessary to provide a termination resistance element in the ASIC element 12. The size can be reduced, and a region where the memory element 13 is arranged can be set wider.

  Here, an outline of the terminal arrangement of the SDRAM 13 is shown in FIG. The SDRAM has a rectangular planar shape, and its outer dimension is 13.8 mm × 11.3 mm.

  As shown in the figure, the terminal arrangement of the SDRAM 13 is such that the address input terminals (A0 to A16) and the command input terminals (/ RAS, / CAS, / WE) are arranged on one short side of the rectangle. Differential clock input terminals (CK, / CK), data input / output terminals (DQ0 to DQ15), differential data strobe terminals (DQS, / DQS), write data mask terminals (UDM, LDM), etc. are on the opposite side It is arranged on the short side.

  In the present embodiment, the address output terminal and command of the ASIC element 12 are related to the address input terminals (A0 to A16) and the command input terminals (/ RAS, / CAS, ODT, CKE, / CS) of each memory element 13. The termination resistor element is omitted in the ASIC element 12 by connecting the output terminals with equal-length wiring. In the present embodiment, the SDRAM 13 includes the semiconductor element 12 on the side where the address input terminals (A0 to A16) and the command input terminals (/ RAS, / CAS, ODT, CKE, / CS) are provided. It arrange | positions on the board | substrate 11 so that it may become far from.

  Therefore, differential clock input terminals (CK, / CK), data input / output terminals (DQ0 to DQ15), differential data strobe terminals (LDQS, / LDQS), (UDQS, / UDQS), write data mask terminals (UDM, LDM), etc. are connected to the ASIC element 12 with respect to the address input terminals (A0 to A16) and the command input terminals (/ RAS, / CAS, ODT, CKE, / CS). Located on the near side.

  Thus, by arranging the terminals of the SDRAM 13 on the substrate 11, the wiring between the ASIC 12 and the corresponding terminals of the SDRAM 13 can be easily formed with a shorter wiring length. Moreover, according to such an arrangement configuration, one short side of the SDRAM 13 faces one side of the ASIC element 12. Therefore, the long side of the SDRAM 13 extends in a direction perpendicular to the one side of the ASIC element 12. For this reason, there is almost no possibility that the presence of the SDRAM 13 restricts the flow of airflow from the lateral direction with respect to the ASIC element 12, and does not hinder heat dissipation of the ASIC element 12.

  Hereinafter, a form of wiring for electrically connecting a predetermined terminal of the ASIC element 12 and a corresponding terminal of the SDRAM 13 will be described.

  FIG. 8 is a diagram showing wiring relating to address input terminals (A0 to A16) and command input terminals (/ RAS, / CAS, ODT, CKE, / CS).

  The wiring topology related to the address input terminals (A0 to A16) and the command input terminals (/ RAS, / CAS, ODT, CKE, / CS) is like the model shown in FIG. 9, and the wiring length (Manhattan length) of 30 mm to 35 mm. ), A star connection was made so that the wiring length (Manhattan length) to each terminal was equal. As a result, the arrangement of the termination resistance element in the ASIC element is omitted.

  As a result of performing an operation test by connecting one ASIC element and eight DRAMs with wirings in one multilayer substrate with such a wiring length, it was possible to operate eight SDRAMs satisfactorily.

  FIG. 10 shows wiring relating to data input / output terminals (DQ0 to DQ15), differential data strobe terminals (LDQS, / LDQS), (UDQS, / UDQS), and write data mask terminals (UDM, LDM).

  The wiring topology relating to the data input / output terminals (DQ0 to DQ15), differential data strobe terminals (LDQS, / LDQS), (UDQS, / UDQS) and write data mask terminals (UDM, LDM) is the model shown in FIG. The wiring impedance was adjusted by providing a termination resistance element on the DRAM side with a wiring length (Manhattan length) of 5 to 30 mm.

  Further, FIG. 12 shows wiring relating to the differential clock input terminals (CK, / CK). The wiring topology related to the differential clock input terminals (CK, / CK) is as shown in the model shown in FIG. 13 and has a wiring length (Manhattan length) of 15 mm to 25 mm on the ASIC element side with respect to one of the differential pairs. A terminal resistance element was provided to adjust the wiring impedance to be equal.

  On the other hand, it is necessary to connect a capacitive element called a decoupling capacitor to the power supply line and the ground line of each semiconductor element mounted on the semiconductor device in order to reduce noise. In this embodiment, as shown in FIG. 4, a chip-like shape is formed in the recess 14 provided on the other main surface (back surface) of the substrate 11 and positioned immediately below the semiconductor element 12. Capacitance elements 15A and 15B are provided.

  The capacitor element 15 is connected between a power wiring layer for a semiconductor element and a ground wiring layer (both not shown) led out to the surface of the substrate 11 in the recess 14. The capacitor element 15 needs to be electrically connected to the electrodes of the semiconductor element and the memory element to be connected with a distance as short as possible. Therefore, it is desirable that the capacitor element 15 be disposed closer to the semiconductor element.

  In the present embodiment, the planar dimension of the recess 14 is larger than the planar dimension of the semiconductor element 12. As described above, when the semiconductor element 12 is an ASIC element, the outer dimension of the ASIC element is 13.72 mm × 13.72 mm, whereas the opening size of the recess 14 is 20.5 mm × 20.5 mm.

  As shown in FIG. 14, the arrangement of the plurality of capacitive elements 15 mounted in the recess 14 is selected so as to be closer to the semiconductor element to be connected. In other words, the capacitive element 15A connected to the semiconductor element 12 is disposed directly below the semiconductor element 12, while the capacitive element 15B corresponding to the storage element 13 is around the capacitive element 15A, that is, the opening of the concave portion 14. It is arrange | positioned in the vicinity of a peripheral part. The number of capacitive elements 15A is determined according to the number of functional blocks included in the semiconductor element 12, while the capacitive element 15B is determined according to the number of storage elements 13 to be mounted.

  The capacitive element 15A is located in the recess 14 and immediately below the semiconductor element 12, thereby reducing the distance from the semiconductor element 12, while the capacitive element 15B is also in the recess 14. Moreover, the distance between the corresponding memory element 13 is made smaller by being arranged close to the opening peripheral edge of the recess 14.

  If the depth of the recess 14 is made deeper than the thickness of the substrate 11, the distance between the semiconductor element 12 or the memory element 13 and the capacitor element 15 can be reduced, but the height (thickness of the capacitor element) The depth of the concave portion 14 is determined in consideration of the mechanical strength of the substrate 11 and the capacitance between wirings. By making the depth of the concave portion 14 greater than the height (thickness) of the capacitive element 15 to be accommodated, the capacitive element 15 does not protrude from the other main surface (back surface) of the substrate 11. Accordingly, there is no restriction when selecting the height of the external connection terminal 16 disposed on the other main surface of the substrate 11, and when the external connection terminal 16 is composed of a solder ball, its dimensions (high Does not affect the selection of the pitch and the arrangement pitch.

  Next, a semiconductor device according to a second embodiment of the present invention will be described.

  The semiconductor device according to the second embodiment of the present invention connects the memory elements 13 by star connection as in the semiconductor device 10 of the first embodiment, but the memory element connection in the semiconductor element 12. There are four terminals, and four storage elements 13 are connected to each of the four terminals. That is, a total of 16 memory elements 13 are applied, and the memory element connection terminals are arranged in the vicinity of each of the four sides of the semiconductor element 12.

  Note that the cross-sectional structure of the semiconductor device according to the present embodiment is the same as the cross-sectional structure shown in FIG.

FIG. 15 shows a configuration of a region when 16 memory elements 13 are arranged. Similar to the first embodiment, the region on the substrate 11 is divided into four regions 51 to 54 around the semiconductor element 12, and four storage elements 13 are arranged in each region. . That is, in this embodiment, n = 2, 2 ² = 4 memory elements are arranged in each region, and the number of memory elements 13 in the entire semiconductor device is 4 × 2 ² = 16. ing.

  In the present embodiment, the four storage elements 13 in each region are made into a single module by connecting the four storage elements 13 in a star shape. The module is connected to a control terminal provided in the semiconductor element 12 to constitute one unit. The control terminal is provided corresponding to the functional block in the semiconductor element 12. Therefore, in this embodiment, four units each including a function block and a storage element corresponding to the function block are formed. Although these units operate independently, of course, a plurality of units may cooperate.

  FIG. 16 schematically shows a wiring connection configuration in the present embodiment. The four memory elements 13 (b) to (e) arranged in the region 51 are connected to one terminal of the semiconductor element 12 with a uniform wiring by a star connection. Similarly, in the other three regions 52 to 54, the four memory elements 13 are connected to corresponding terminals of the semiconductor element 12 through equal-length wiring.

  In the connection configuration shown in FIG. 16, the unit composed of (b) to (e) of the first functional block in the semiconductor element 12 and the memory element 13 operates as one unit. The second functional block and the unit composed of (f) to (i) of the storage element 13 operate as one unit. A unit composed of the third functional block in the semiconductor element 12 and the storage elements 13 (j) to (m) operates as one unit, and further, a fourth functional block in the semiconductor element 12 and the storage element 13. The units consisting of (n) to (q) of the above operate in one unit. Each of the four units operates individually, but of course, a plurality of units may cooperate. Each region 51 to 54 is not limited to the configuration extending in the clockwise direction around the semiconductor element 12 as shown in FIG. 15, but may be extended in the counterclockwise direction as shown in FIG. Good.

  In this way, one semiconductor element 12 and a plurality (16) of storage elements 13 are efficiently arranged on one substrate 11. On the other hand, by connecting the semiconductor element 12 and a plurality (16) of memory elements 13 via isometric wires formed with a star connection, a termination resistance element is provided in the semiconductor element 12. No need arises. Therefore, the semiconductor device 10 can be provided as a smaller memory system as a functional memory module including the semiconductor element 12 without increasing the size of the semiconductor element 12. Thereby, wiring on a substrate such as a mother board on which the semiconductor device 10 is mounted can be simplified, the number of layers of the substrate can be reduced, and the design of the substrate of the electronic device can be simplified to reduce cost. Can be achieved.

  In addition, since the electrical connection between the semiconductor element 12 as the logic element and the memory element 13 is performed by wiring in the substrate 11, the wiring length between the two is very short. The access time required for writing or reading data to or from the memory is greatly reduced. Therefore, high-speed data transfer is possible, the processing speed is improved, and the throughput is greatly improved.

  Also in this embodiment, the concave portion 14 is formed on the other peripheral surface (back side) of the substrate 11, and the capacitor elements 15 </ b> A and 15 </ b> B necessary for the semiconductor element 12 and the memory element 13 are disposed in the concave portion 14.

  In the example shown in FIGS. 15 and 17, four memory elements 13 are arranged side by side in one area, but two memory elements 13 that are paired with each other can be stacked.

  FIG. 18 shows a semiconductor device in which two memory elements 13 are stacked. 13A shows a stacked body of such semiconductor elements 13. 18, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted.

  Since the memory elements 13 that are paired with each other in each of the areas 51 to 54 are stacked, as shown in FIG. 19 or FIG. 20, for example, in one area 51, the stacked body 13A of the two memory elements 13 is formed. Two are arranged side by side. The two memory elements 13 that are stacked are provided with a common terminal that is connected with an equal length from the branch point.

  In the embodiment shown in FIGS. 15 to 17, 19, and 20, four storage elements are respectively provided in the four regions 51 to 54 on one main surface of the substrate 11. Are arranged and connected as one module to one of the functional blocks of the semiconductor element 12, but as shown in FIGS. 21 and 22, two modules, that is, eight capacitive elements are connected by equal-length wiring. Of course, this is connected to the functional block of the semiconductor element 12. According to this configuration, the number of storage elements that can be handled by one functional block, and hence the storage capacity, is doubled, the processing speed of the functional block is greatly improved, and the throughput can be greatly improved.

As described above, in the embodiment of the present invention, all the memory elements 13 can be made to have equal length wiring because each of the semiconductor elements 12 is arranged around the semiconductor element 12 mounted on one main surface of the substrate 11. This is because four regions extending in parallel to the sides are set, and an even number (or ²ⁿ ) of storage elements 13 are arranged in each region.

  Thus, a pair of the storage elements 13 is formed in each region, and wiring is formed between the pair of storage elements 13, so that the command terminal and the address terminal of the storage element 13 are connected to the semiconductor element 12 with equal length wiring. The semiconductor element 12 can be reduced in size by omitting the terminal resistance element.

  Further, since the capacitor elements 15A and 15B necessary for each of the semiconductor element 12 and the memory element 13 are accommodated and arranged in the recess 14 formed on the back side of the substrate 11, it is necessary to mount the capacitor element 13 on the surface side of the substrate 11. Thus, the entire area of the surface of the substrate 11 can be effectively used for mounting the semiconductor element 12 and the memory element 13. Therefore, the planar shape dimension of the substrate 11, that is, the outer dimension of the semiconductor device can be further reduced.

  Further, since the semiconductor element 12 is flip-chip mounted on the substrate 11, the heat generation in the semiconductor element 11 can be efficiently released by attaching the heat radiating plate 17 to the back surface of the semiconductor element 12.

  Further, there is no problem in applying so-called lead-free solder as a solder material when the semiconductor element 12 and the memory element 13 are flip-chip mounted on the substrate 11 and a solder material for the solder ball 16.

  As described above, the present specification discloses the following invention.

(Appendix 1)
A substrate,
A first semiconductor element mounted on one main surface of the substrate;
A plurality of memory elements mounted on the periphery of the first semiconductor element on one main surface of the substrate;
A wiring disposed on the substrate and electrically connecting the first semiconductor element and the memory element;
Around the first semiconductor element, in each of the virtual regions set in parallel to the outer periphery of the first semiconductor element, the number of storage elements is 2 n (n is a natural number of 1 or more). A semiconductor device characterized by being arranged in units.

(Appendix 2)
A semiconductor device according to appendix 1, wherein
2. A semiconductor device comprising: an address terminal of a memory element disposed in each of the virtual regions and an address control terminal of the first semiconductor element connected to each other by an equal length wiring.

(Appendix 3)
A semiconductor device according to appendix 1, wherein
A semiconductor device comprising: a command input terminal of a memory element disposed in each of the virtual regions; and a command output terminal of the first semiconductor element connected to each other by an equal length wiring.

(Appendix 4)
The semiconductor device according to appendices 1 to 3,
The semiconductor device is characterized in that an address input terminal and a command input terminal are disposed at a position far from the first semiconductor element.

(Appendix 5)
A semiconductor device according to appendix 1, wherein
2. A semiconductor device characterized in that 2 n power storage elements arranged in one virtual region are connected to each other by the same length wiring with the first semiconductor element.

(Appendix 6)
A semiconductor device according to appendix 1, wherein
Memory devices arranged in different virtual regions are connected to each other by the same length wiring between the first semiconductor elements.

(Appendix 7)
A semiconductor device according to appendix 1, wherein
Each of the corresponding address terminals between 2 n memory elements as a unit and the address control terminal of the first semiconductor element are connected to each other by an equal length wiring. A featured semiconductor device.

(Appendix 8)
A semiconductor device according to appendix 1, wherein
Each of the corresponding command input terminals between 2 n memory elements as a unit and the command output terminal of the first semiconductor element are connected to each other by equal length wiring. A semiconductor device characterized by the above.

(Appendix 9)
A semiconductor device according to appendix 1, wherein
Each of the corresponding address terminals between the memory elements arranged in different virtual areas and the address control terminal of the first semiconductor element are connected to each other by an equal length wiring. A semiconductor device.

(Appendix 10)
A semiconductor device according to appendix 1, wherein
Each of the corresponding command input terminals between the memory elements arranged in different virtual areas and the command output terminal of the first semiconductor element are connected to each other by an equal length wiring. A featured semiconductor device.

(Appendix 11)
A substrate,
A first semiconductor element mounted on one main surface of the substrate;
A plurality of memory elements mounted on the periphery of the first semiconductor element on one main surface of the substrate;
A wiring disposed on the substrate and electrically connecting the first semiconductor element and the memory element;
In the other main surface of the substrate, a recess is disposed in a region corresponding to the first semiconductor element,
A plurality of first capacitive elements that are electrically connected to the first semiconductor element are disposed in the central portion of the recess,
A semiconductor device comprising a plurality of second capacitor elements electrically connected to the memory element around the first capacitor element.

It is a top view which shows an example of the conventional semiconductor device. It is sectional drawing along the II-II line of FIG. It is a figure which shows the area | region which arrange | positions the semiconductor element and memory element on a board | substrate in the 1st Embodiment of this invention. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the connection structure of the semiconductor element and memory element in FIG. It is a figure which shows the area | region which arrange | positions the semiconductor element and memory element on a board | substrate. It is a figure which shows the terminal arrangement | sequence of DRAM. It is a figure which shows the wiring regarding an address input terminal and a command input terminal. It is a figure which shows the wiring topology regarding an address input terminal and a command input terminal. It is a figure which shows the wiring regarding a data input / output terminal, a differential data strobe terminal, and a write data mask terminal. It is a figure which shows the wiring topology regarding a data input / output terminal, a differential data strobe terminal, and a write data mask terminal. It is a figure which shows the wiring regarding a differential clock input terminal. It is a figure which shows the wiring topology regarding a differential clock input terminal. It is a top view which shows the back surface of the semiconductor device shown in FIG. It is a figure which shows the area | region for arrange | positioning 16 memory elements in the semiconductor device by the 2nd Embodiment of this invention. FIG. 16 is a schematic diagram illustrating a wiring configuration between the semiconductor element and the memory element illustrated in FIG. 15. It is a figure which shows the area | region for arrange | positioning 16 memory elements in the semiconductor device by the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device which has the memory | storage element laminated | stacked. FIG. 19 is a diagram showing a region where semiconductor elements and memory elements are arranged in the semiconductor device shown in FIG. 18. FIG. 19 is a diagram showing a region where semiconductor elements and memory elements are arranged in the semiconductor device shown in FIG. 18. In the semiconductor device by the 2nd Embodiment of this invention, it is a figure which shows the different connection structure of 16 memory elements with the arrangement | positioning. FIG. 22 is a schematic diagram showing a wiring configuration of a semiconductor element and a memory element in the semiconductor device shown in FIG. 21.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Area | region 3 Capacitance element 4 Heat spreader 5 Solder ball 10 Semiconductor device 11 Substrate 12 Semiconductor element 12-1 1st edge 12-2 2nd edge 12-3 3rd edge 12-4 4th edge 13 Memory element 13A Stack of memory element 13 14 Recess 15A, 15B Capacitor 16 Solder ball 17 Heat sink 18-1, 18-2, 18-3, 18-4 Wiring 51, 52, 53, 54 Area on substrate 11

Claims (4)

A substrate,
A first semiconductor element mounted on one main surface of the substrate;
A plurality of memory elements mounted on the periphery of the first semiconductor element on one main surface of the substrate;
A wiring disposed on the substrate and electrically connecting the first semiconductor element and the memory element;
Around the first semiconductor element, each of the four virtual regions set in parallel to each side outside the four outer sides of the first semiconductor element has the memory element having a power of 2 n. Each (n is a natural number of 1 or more) ,
In the other main surface of the substrate, a recess is disposed in a region corresponding to the first semiconductor element,
A plurality of first capacitive elements that are electrically connected to the first semiconductor element are disposed in the central portion of the recess,
A semiconductor device comprising a plurality of second capacitor elements electrically connected to the memory element around the first capacitor element . The semiconductor device according to claim 1,
2. A semiconductor device comprising: an address terminal of a memory element disposed in each of the virtual regions and an address control terminal of the first semiconductor element connected to each other by an equal length wiring. The semiconductor device according to claim 1,
A semiconductor device comprising: a command input terminal of a memory element disposed in each of the virtual regions; and a command output terminal of the first semiconductor element connected to each other by an equal length wiring. The semiconductor device according to claim 1, wherein
The semiconductor device is characterized in that an address input terminal and a command input terminal are disposed at a position far from the first semiconductor element.

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