WO2014097916A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2014097916A1
WO2014097916A1 PCT/JP2013/082966 JP2013082966W WO2014097916A1 WO 2014097916 A1 WO2014097916 A1 WO 2014097916A1 JP 2013082966 W JP2013082966 W JP 2013082966W WO 2014097916 A1 WO2014097916 A1 WO 2014097916A1
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WIPO (PCT)
Prior art keywords
semiconductor chip
electrode
semiconductor
pad
row
Prior art date
Application number
PCT/JP2013/082966
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French (fr)
Japanese (ja)
Inventor
聡 伊佐
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014097916A1 publication Critical patent/WO2014097916A1/en

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device.
  • a DDP (Dual Die Package) type semiconductor device in which two semiconductor chips are stacked on a wiring board is known.
  • Patent Document 1 describe a semiconductor device in which two semiconductor chips are stacked face up. Hereinafter, the semiconductor device shown in FIGS. 8 to 10 of Patent Document 1 will be described.
  • this semiconductor device includes a wiring board, a first semiconductor chip, and a second semiconductor chip.
  • the first semiconductor chip and the second semiconductor chip have the same configuration.
  • a plurality of I / O (Input / Output) lands for the first semiconductor chip are formed at one end of the electrode formation surface of the wiring board. (Referred to as “first I / O land”).
  • a plurality of I / O lands for the second semiconductor chip (hereinafter referred to as “second I / O lands”) are formed at the other end of the electrode formation surface.
  • a plurality of CA (command address) lands are formed near the center of the electrode formation surface. The CA land is connected to the first and second semiconductor chips.
  • first bond finger row for connection to the first semiconductor chip.
  • the first bond finger row is classified into a bond finger row connected to the first I / O land via the wiring and through via, and a bond finger row connected to the CA land via the wiring and through via. Is done.
  • a bond finger row (hereinafter referred to as “second bond finger row”) for connection to the second semiconductor chip. Is formed).
  • the second bond finger row is classified into a bond finger row connected to the second I / O land via wiring and through vias, and a bond finger row connected to the CA land.
  • CA land is connected to the bond fingers in the second bond finger row as well as the bond fingers in the first bond finger row.
  • the first semiconductor chip has a rectangular shape and includes an I / O pad row and a CA pad row.
  • the I / O pad row and the CA pad row are arranged along a center line parallel to a pair of long sides facing each other of the first semiconductor chip.
  • the I / O system pad array and the CA system pad array are arranged in series so as to be in a straight line.
  • the I / O system pad row is disposed on one end side of the first semiconductor chip.
  • the CA-based pad row is disposed on the other end side of the first semiconductor chip.
  • one end of the first semiconductor chip (the end where the I / O pad array is formed) is the end side where the first I / O land of the wiring board is formed. It is mounted face-up on the chip mounting surface of the wiring board via an adhesive member.
  • the second semiconductor chip having the same configuration as the first semiconductor chip has one end (I / O system) of the second semiconductor chip. Face-up on the first semiconductor chip via an adhesive member so that the end where the pad row is formed is located on the end where the second I / O land is formed on the wiring board. Mounted on.
  • the second semiconductor chip is stacked on the first semiconductor chip in a state where the second semiconductor chip is rotated 180 degrees with respect to the first semiconductor chip about a straight line in the thickness direction passing through the center of the chip.
  • each bond finger constituting the first bond finger row is individually connected with an I / O pad or a CA pad of the first semiconductor chip by a wire. Connected to.
  • each bond finger constituting the second bond finger row is a wire, an I / O pad or a CA pad of the second semiconductor chip. And connected individually.
  • the first I / O land of the wiring board is connected to the I / O pad of the first semiconductor chip via a bond finger or a wire.
  • the second I / O land of the wiring board is connected to the I / O system pad of the second semiconductor chip via a bond finger or a wire.
  • the CA land of the wiring board is connected to the CA pad of the first semiconductor chip and the CA pad of the second semiconductor chip via bond fingers and wires, respectively.
  • the lower semiconductor chip mounted on the wiring board is used as in the above-described conventional technology.
  • a method is conceivable in which the upper semiconductor chip is stacked on the lower semiconductor chip while being rotated 180 degrees around the straight line in the thickness direction passing through the center of the own chip.
  • the length of the wiring that connects the CA land and the CA electrode pad of the lower semiconductor chip and the length of the wiring that connects the CA land and the CA electrode pad of the upper semiconductor chip are the same. And the difference will be larger.
  • FIG. 1A is a diagram showing an example of the lower semiconductor chip 101.
  • FIG. 1B is a diagram illustrating an example of the upper semiconductor chip 102.
  • the upper semiconductor chip 102 has the same configuration as the lower semiconductor chip 101.
  • an I / O connection pad row 101c and a CA connection pad row 101d are formed in the lower semiconductor chip 101.
  • the I / O system connection pad row 101c and the CA system connection pad row 101d are respectively connected to the I / O system pad row 101a and the CA system pad row 101b via the rewiring layer 101e.
  • an I / O connection pad row 102c and a CA connection pad row 102d are formed on the upper semiconductor chip 102.
  • the I / O system pad row 102a, CA system pad row 102b, I / O system connection pad row 102c, and CA system connection pad row 102d of the upper semiconductor chip 102 are respectively connected to the I / O system of the lower semiconductor chip 101. This corresponds to the pad row 101a, the CA-type pad row 101b, the I / O-type connection pad row 101c, and the CA-type connection pad row 101d.
  • FIG. 2A is a diagram showing a connection relationship between the wiring board 103 and the lower semiconductor chip 101.
  • FIG. 2B is a diagram illustrating a connection relationship between the wiring substrate 103 and the upper semiconductor chip 102.
  • the chip mounting surface 103-1 of the wiring substrate 103 has an I / O pin bond finger row 103 a 1, a CA pin bond finger row 103 a 2, an I / O pin bond finger row 103 b 1, and a CA pin. Bond finger row 103b2 is formed.
  • the I / O pin bond finger row 103 a 1 is connected to the I / O connection pad row 101 c of the lower semiconductor chip 101 via the wire 104.
  • the CA pin bond finger row 103 a 2 is connected to the CA connection pad row 101 d of the lower semiconductor chip 101 through the wire 104.
  • the I / O pin bond finger row 103 b 1 is connected to the I / O connection pad row 102 c of the upper semiconductor chip 102 via the wire 104.
  • the CA pin bond finger row 103b2 is connected to the CA connection pad row 102d of the upper semiconductor chip 102 via the wire 104.
  • the bond finger 103a20 in the CA pin bond finger row 103a2 connected to the CA0 pad 101d0 of the lower semiconductor chip 101 and the CA0 pad 102d0 of the upper semiconductor chip 102 are connected.
  • the bond pin 103b20 in the CA pin bond finger row 103b2 is connected to a common CA0 land.
  • FIG. 3 is a diagram for explaining the connection between the bond finger 103a20 and the CA0 land 105c0 and the connection between the bond finger 103b20 and the CA0 land 105c0.
  • an electrode forming surface 103-2 which is the back surface of the chip mounting surface 103-1, is provided with an I / O land 105a for the lower semiconductor chip 101 and an I / O for the upper semiconductor chip 102.
  • An O land 105b and a CA land 105c are formed.
  • the CA0 lands 105c0 are connected to the bond fingers 103a20 and 103b20.
  • the length of the wiring from the CA0 land 105c0 to the bond finger 103a20 is significantly different from the length of the wiring from the CA0 land 105c0 to the bond finger 103b20.
  • the difference in the length of the wiring becomes larger as the CA0 land 105c0 is closer to one of the bond fingers 103a20 and 103b20.
  • This difference in wiring length makes it difficult to adjust the deviation of the operation timing of the upper and lower semiconductor chips, and becomes a factor that hinders the high-speed operation of the semiconductor device.
  • the semiconductor device of the present invention is A substrate, a first semiconductor chip mounted on the substrate, and a second semiconductor chip stacked on the first semiconductor chip,
  • the first and second semiconductor chips are: A surface defined by first and second sides facing each other; A group of electrodes including first and second electrodes of a command address system arranged in a central region of the one surface in parallel with the first side; A third electrode disposed on the one surface along the first side; Each having a fourth electrode disposed on the one surface along the second side,
  • the first electrode of the first semiconductor chip is the third electrode of the first semiconductor chip
  • the second electrode of the first semiconductor chip is the first electrode.
  • the first electrode of the second semiconductor chip is the fourth electrode of the second semiconductor chip
  • the second electrode of the second semiconductor chip is the first electrode.
  • Each of the second semiconductor chips is electrically connected to the third electrode, and the first side of the second semiconductor chip is on the second side of the first semiconductor chip,
  • the second semiconductor chip is stacked on the first semiconductor chip so that the second side of the second semiconductor chip is positioned on the first side of the first semiconductor chip.
  • the first semiconductor chip is configured such that the first electrode is electrically connected to the third electrode and the second electrode is electrically connected to the fourth electrode.
  • the second semiconductor chip is configured such that the first electrode is electrically connected to the fourth electrode, and the second electrode is electrically connected to the third electrode.
  • the first side of the second semiconductor chip is on the second side of the first semiconductor chip, and the second side of the second semiconductor chip is the first semiconductor chip. They are stacked on the first semiconductor chip so as to be positioned on the first side.
  • the third electrode connected to the first electrode of the first semiconductor chip and the fourth electrode connected to the first electrode of the second semiconductor chip are connected to the first electrode of the first semiconductor chip. 1 can be arranged on one side.
  • the fourth electrode connected to the second electrode of the first semiconductor chip and the third electrode connected to the second electrode of the second semiconductor chip are connected to the first electrode of the first semiconductor chip. It can be arranged on the two sides. For this reason, it becomes possible to reduce the difference in the wiring length of the corresponding command address system in the upper and lower semiconductor chips on the substrate.
  • the present invention it is possible to reduce the difference in the wiring length of the corresponding command address system in the upper and lower semiconductor chips on the wiring board. For this reason, it becomes easy to adjust the shift of the operation timing due to the difference in the wiring length, and the speed of the semiconductor device can be increased.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device 1 according to a first embodiment of the present invention.
  • 3 is a plan view showing an electrode forming surface side of the semiconductor device 1;
  • FIG. 2 is a plan view showing a chip mounting surface side of the semiconductor device 1;
  • FIG. 3 is a cross-sectional view schematically showing a semiconductor device 1 according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing a chip mounting surface side of the semiconductor device 1;
  • FIG. 1 is a plan view showing a semiconductor chip 20.
  • 2 is a plan view showing a semiconductor chip 30.
  • FIG. 3 It is a figure for demonstrating the connection of the bond finger for CA0, and the land for CA0.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • It is a figure showing semiconductor chip 20X used for semiconductor device 1A of a 2nd embodiment of the present invention. It is the figure which showed the semiconductor chip 30X used for the semiconductor device 1A of 2nd Embodiment of this invention.
  • 1 is a plan view schematically showing a semiconductor device 1A.
  • 1 is a plan view schematically showing a semiconductor device 1A. It is the figure which showed semiconductor chip 20Y used for the semiconductor device 1B of 3rd Embodiment of this invention.
  • FIG. 6 is a diagram showing a switching circuit 60.
  • FIG. 4 is a cross-sectional view schematically showing the semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 4 shows a cross section in a direction perpendicular to the substrate.
  • the semiconductor device 1 is a DDP type semiconductor package in which two semiconductor chips 20 and 30 are stacked.
  • the semiconductor chip 20 is an example of a first semiconductor chip.
  • the semiconductor chip 30 is an example of a second semiconductor chip.
  • FIG. 5 is a plan view schematically showing the semiconductor device 1 shown in FIG. FIG. 5 shows the electrode forming surface 10b side on which a plurality of lands 13 are formed.
  • FIG. 6A and 6B are plan views schematically showing the semiconductor device 1 shown in FIG. 6A and 6B show the chip mounting surface 10a side on which a plurality of bond fingers 15 are formed.
  • FIG. 6A also shows the connection relationship between the lower semiconductor chip 20 and the bond finger rows 15a and 15b.
  • FIG. 6B also shows a connection relationship between the upper semiconductor chip 30 and the bond finger rows 15c and 15d.
  • FIG. 7A is a plan view showing the lower semiconductor chip 20.
  • FIG. 7B is a plan view showing the upper semiconductor chip 30.
  • the insulating layer on the rewiring layer 28 is omitted.
  • the semiconductor device 1 has a wiring substrate 10 made of, for example, a 0.2 mm thick glass epoxy base material (insulating substrate).
  • the wiring board 10 is formed in a substantially rectangular shape.
  • the wiring substrate 10 has a chip mounting surface 10a on which the two semiconductor chips 20 and 30 are stacked, and an electrode forming surface 10b that is the back surface of the chip mounting surface 10a.
  • the wiring 18 made of a conductive material such as Cu is formed on the chip mounting surface 10a.
  • the wiring 18 is partially covered with an insulating film, for example, a solder resist 14.
  • Bond fingers 15 are formed in the wiring regions exposed from the solder resist 14 on the chip mounting surface 10a.
  • a plurality of lands (external electrodes) 13 on which solder balls 17 are mounted are formed on the electrode forming surface 10b.
  • the lands 13 are electrically connected to the bond fingers 15 on the chip mounting surface 10 a through through vias 19 and wirings 18 formed in the wiring substrate 10.
  • the lands 13a-13c formed on the electrode forming surface 10b are arranged in a grid at predetermined intervals.
  • Each land 13 includes a bond finger belonging to one of the bond finger rows 15a to 15d, a wire 42, an I / O connection pad row 23a, 23b, 33a, 33b, or a CA connection pad row 24a, 24b, 34a,
  • the connection pads belonging to any one of 34 b and the rewiring layer 28 are electrically connected to the pads belonging to any of the I / O pad rows 21 and 31 or the CA pad rows 22 and 32. ing.
  • the land 13 is classified into two types according to the input / output system of the pad rows 21, 22, 31, and 32 of the semiconductor chips 20 and 30.
  • I / O lands 13a and 13c connected to data (DQ) system signals and DQ system power supply / GND, that is, input / output system electrode pad (I / O system pad) rows 21 and 31. .
  • the other is the CA land 13b connected to the command address system electrode pad (CA system pad) rows 22 and 32.
  • the I / O lands 13a and 13c are arranged separately at both ends of the electrode forming surface 10b.
  • the I / O lands 13a and 13c arranged at each end are assigned to the semiconductor chips 20 and 30, respectively.
  • an I / O land 13a corresponding to the semiconductor chip 20 is disposed at an upper end portion (first end portion) 11 as viewed in FIG.
  • an I / O land 13c corresponding to the semiconductor chip 30 is disposed at the lower end (second end) 12 as viewed in FIG.
  • a CA land 13b is disposed between the I / O lands 13a and 13c.
  • the semiconductor chip 20 is mounted on the chip mounting surface 10a via an adhesive member 41a such as DAF (Die Attached Film) or elastomer.
  • an adhesive member 41a such as DAF (Die Attached Film) or elastomer.
  • the semiconductor chip 20 is formed in a substantially rectangular plate shape as shown in FIGS. 6A and 7A.
  • a memory circuit and a plurality of electrode pads are formed on a pad forming surface 20 a that is one surface.
  • the pad forming surface 20a is a surface partitioned by long sides 25a and 25b facing each other.
  • the long side 25a is an example of a first side.
  • the long side 25b is an example of the second side.
  • the pad forming surface 20a includes an I / O system pad row 21, a CA system pad row 22, I / O system connection pad rows 23a and 23b, and a CA system connection pad row 24a.
  • 24b, a rewiring layer 28, and insulating layers 29a and 29b are formed.
  • the pads (electrodes) included in the I / O system pad row 21 are electrode pads connected to the pads included in the I / O system connection pad row 23a via the rewiring layer 28, and I / O system connection pad rows. 23b and an electrode pad connected via the redistribution layer 28.
  • an insulating layer 29 a is formed under the rewiring layer 28.
  • an insulating layer 29b is formed except for the pad portion.
  • the pads (electrodes) included in the CA system pad row 22 are the electrode pads (for example, the pad 22a) connected to the pads included in the CA system connection pad row 24a via the rewiring layer 28, and the CA system connection pad row. 24b and an electrode pad (for example, pad 22b) connected via the redistribution layer 28.
  • the pad 22a is an example of the first electrode.
  • the pad 22b is an example of a second electrode.
  • the I / O system pad row 21 and the CA system pad row 22 are aligned along a center line parallel to a pair of opposing long sides 25a and 25b of the rectangular semiconductor chip 20. Are arranged in series.
  • the I / O system pad row 21 is arranged close to the first end portion 26 side of the semiconductor chip 20.
  • the CA pad row 22 is arranged close to the second end 27 side.
  • the I / O pad row 21 and the CA pad row 22 are included in the electrode group.
  • the I / O system connection pad row 23a and the CA system connection pad row 24a are arranged in series on the pad forming surface 20a so as to be in a straight line along the long side 25a.
  • the I / O system connection pad row 23 a is disposed on the first end portion 26 side of the semiconductor chip 20.
  • the CA connection pad row 24a is arranged on the second end portion 27 side.
  • the electrode pad (for example, pad 24aa) included in the CA-based connection pad row 24a is an example of a third electrode.
  • the I / O connection pad row 23b and the CA connection pad row 24b are arranged in series on the pad forming surface 20a so as to be in a straight line along the long side 25b.
  • the I / O system connection pad row 23b is disposed on the first end portion 26 side.
  • the CA connection pad row 24b is disposed on the second end 27 side.
  • the electrode pad (for example, pad 24bb) included in the CA-based connection pad row 24b is an example of a fourth electrode.
  • a passivation film (not shown) for protecting the pad formation surface 20a is formed on the pad formation surface 20a excluding the I / O connection pad rows 23a and 23b and the CA connection pads 24a and 24b.
  • the semiconductor chip 20 is arranged on the wiring substrate 10 face up so that the first end portion 26 of the semiconductor chip 20 is located on the first end portion 11 side of the wiring substrate 10. ing. That is, in the semiconductor chip 20, the I / O system connection pad rows 23 a and 23 b arranged at the first end portion 26 of the semiconductor chip 20 are arranged at the first end portion 11 of the wiring substrate 10. The I / O land 13a and the bond finger row 15a are adjacent to each other.
  • Each pad included in the I / O system connection pad rows 23a and 23b of the semiconductor chip 20 is individually connected to a bond finger included in the bond finger row 15a by a conductive wire 42 made of, for example, Au or Cu. So that they are electrically connected.
  • the bond finger row 15a of the chip mounting surface 10a is in the vicinity of this long side along two long sides of the wiring substrate 10 parallel to the direction in which the I / O pad row 21 of the stacked semiconductor chips 20 extends. Each is arranged. Further, the bond finger row 15 a is arranged close to the first end portion 11 side of the wiring substrate 10.
  • Each pad included in the CA connection pad rows 24a and 24b of the semiconductor chip 20 is electrically connected to the bond finger included in the bond finger row 15b by being individually connected by the wire 42.
  • the bond finger row 15b of the chip mounting surface 10a is in the vicinity of the long side along two long sides of the wiring substrate 10 parallel to the direction in which the I / O pad row 21 of the stacked semiconductor chips 20 extends. Each is arranged. Further, the bond finger row 15 b is arranged close to the second end portion 12 side of the wiring substrate 10.
  • the semiconductor chip 30 has the same configuration as the semiconductor chip 20 except for the connection relationship between the pads included in the CA system pad row and the pads included in the CA system connection pad row by the redistribution layer (see FIGS. 7A and 7B). .
  • the semiconductor chip 30 is formed in a substantially rectangular plate shape as shown in FIGS. 6B and 7B.
  • a memory circuit and a plurality of electrode pads are formed on a pad forming surface 30 a that is one surface of the semiconductor chip 30.
  • the pad forming surface 30a is a surface partitioned by long sides 35a and 35b facing each other.
  • the long side 35a is an example of a first side.
  • the long side 35b is an example of a second side.
  • the pad forming surface 30a includes an I / O pad row 31, a CA pad row 32, I / O connection pad rows 33a and 33b, CA connection pad rows 34a and 34b, and a rewiring layer 28. Insulating layers 29a and 29b are formed.
  • the I / O pad row 31, the CA pad row 32, the I / O connection pad rows 33a and 33b, and the CA connection pad rows 34a and 34b in the semiconductor chip 30 are respectively This corresponds to the I / O pad row 21, the CA pad row 22, the I / O connection pad rows 23a and 23b, and the CA connection pad rows 24a and 24b in the semiconductor chip 20.
  • the pads in the CA pad row 22 (pads 22a corresponding to CA1) connected to the pads in the CA connection pad row 24a of the semiconductor chip 20 (for example, the pads 24aa corresponding to CA1).
  • the corresponding pad in the CA system pad row 32 (pad 32a corresponding to CA1) is connected to the pad in the CA system connection pad row 34b (pad 34bb corresponding to CA1).
  • the pad 32a corresponding to CA1 in the semiconductor chip 30 is an example of the first electrode.
  • the pad 35bb connected to the pad 32a is an example of a fourth electrode.
  • the pad 32b corresponding to CA0 in the semiconductor chip 30 is an example of a second electrode.
  • the pad 34aa connected to the pad 32b is an example of a third electrode.
  • the direction drawn by the rewiring layer 28 is opposite in each pad in the CA-based pad row.
  • the semiconductor chip 30 is disposed on the semiconductor chip 20 face up so that the first end 36 of the semiconductor chip 30 is located on the second end 12 side of the wiring substrate 10. As shown in FIG. ing. That is, the semiconductor chip 30 has the I / O connection pad rows 33a and 33b arranged on the first end portion 36 side for the semiconductor chip 30 arranged on the second end portion 12 side of the wiring board 10. It is arranged so as to be adjacent to the I / O land 13c.
  • an FOW 41b that is an adhesive member is disposed between the semiconductor chip 20 and the semiconductor chip 30.
  • a part of the wire 42 that electrically connects the semiconductor chip 20 and the wiring substrate 10 is embedded in the FOW 41b.
  • Each pad included in the I / O system connection pad row 33a, 33b of the semiconductor chip 30 is electrically connected to the bond finger included in the bond finger row 15c by being individually connected by the wire 42. .
  • the bond finger row 15c is formed on the chip mounting surface 10a so as to be juxtaposed with the bond finger row 15b.
  • Each pad included in the CA connection pad row 34a, 34b of the semiconductor chip 30 is electrically connected to the bond finger included in the bond finger row 15d by being individually connected by the wire 42.
  • the bond finger row 15d is formed on the chip mounting surface 10a so as to be juxtaposed with the bond finger rows 15a and 15b.
  • FIG. 8 shows the connection between the CA0 bond finger 15b0 and the CA0 land 13b0 in the bond finger row 15b for the semiconductor chip 20, and the connection between the CA0 bond finger 15d0 and the CA0 land 13b0 in the bond finger row 15d. It is a figure for demonstrating.
  • a sealing body 43 made of a thermosetting resin such as an epoxy resin is formed on the chip mounting surface 10 a of the wiring substrate 10.
  • the semiconductor chips 20 and 30 and the wire 42 are covered with a sealing body 43 and protected from the outside.
  • the semiconductor device 1 includes the substrate 10, the first semiconductor chip 20 mounted on the substrate 10, and the second semiconductor chip 30 stacked on the first semiconductor chip 20. Have.
  • the first and second semiconductor chips 20 and 30 have first surfaces 20a and 30a defined by first and second sides 25a, 25b, 35a and 35b facing each other, and a first region in the central region of the first surfaces 20a and 30a.
  • the first electrode 22a of the first semiconductor chip 20 is the third electrode 24aa of the first semiconductor chip 20, and the second electrode 22b of the first semiconductor chip 20 is the first.
  • the semiconductor chip 20 is configured to be electrically connected to the fourth electrode 24bb.
  • the first electrode 32a of the second semiconductor chip 30 is the fourth electrode 34bb of the second semiconductor chip 30, and the second electrode 32b of the second semiconductor chip 30 is the second.
  • the first side 35a of the second semiconductor chip 30 is on the second side 25b side of the first semiconductor chip 20, and is electrically connected to the third electrode 34aa of the semiconductor chip 30.
  • the second semiconductor chip 30 is stacked on the first semiconductor chip 20 so that the second side 35b is positioned on the first side 25a side of the first semiconductor chip 20, respectively.
  • the third electrode 24aa connected to the first electrode 22a of the semiconductor chip 20 and the fourth electrode 35bb connected to the first electrode 32a of the semiconductor chip 30 are replaced with the first electrode of the semiconductor chip 20.
  • the fourth electrode 24bb connected to the second electrode 22b of the semiconductor chip 20 and the third electrode 34aa connected to the second electrode 32b of the semiconductor chip 30 are connected to the second electrode 22b of the semiconductor chip 20. It can be arranged on the side 25b side.
  • the first semiconductor chip 20 is mounted on the substrate 10 so that the surface on the back side of the one surface 20a of the first semiconductor chip 20 faces the substrate 10.
  • the semiconductor chip 30 is mounted on the first semiconductor chip 20 so that the back surface of the one surface 30 a of the second semiconductor chip 30 faces the first semiconductor chip 20.
  • the first semiconductor chip 20 and the second semiconductor chip 30 can be stacked face up.
  • 9A to 9F are cross-sectional views schematically showing each step of the method for manufacturing the semiconductor device 1 of the present embodiment.
  • a wiring mother board 50 is prepared.
  • the wiring mother board 50 used in this embodiment is processed by a MAP (Mold Array Process) method.
  • a plurality of product forming portions 51 are arranged in a matrix on the wiring mother board 50.
  • the product forming part 51 is an area to be the wiring board 10 after being cut and separated.
  • a dicing line 52 is provided between the product forming portions 51.
  • a frame part (not shown) is provided around the product forming part 51 arranged in a matrix. Positioning holes (not shown) for carrying and positioning the wiring mother board 50 are provided in the frame portion at predetermined intervals.
  • the semiconductor chip 20 is placed on each product forming portion 51 of the wiring mother board 50, and a DAF, for example, a tape member having an adhesive layer on both surfaces of an insulating substrate, or an adhesive member 41a such as an elastomer. Adhering and fixing through.
  • a DAF for example, a tape member having an adhesive layer on both surfaces of an insulating substrate, or an adhesive member 41a such as an elastomer. Adhering and fixing through.
  • the semiconductor chip 20 is arranged on the product forming portion 51 so that the back surface of the pad forming surface 20a of the semiconductor chip 20 faces the product forming portion (wiring substrate) 51.
  • the pads in the I / O system connection pad rows 23 a and 23 b of the semiconductor chip 20 and the bond fingers in the bond finger row 15 a of the wiring substrate 10 are connected by wires 42. Further, the pads in the CA-based connection pad rows 24 a and 24 b of the semiconductor chip 20 and the bond fingers in the bond finger row 15 b of the wiring substrate 10 are connected by wires 42.
  • the wire bonding of the semiconductor chip 20 is performed before the semiconductor chip 30 is mounted on the pad forming surface 20a of the semiconductor chip 20.
  • the semiconductor chip 30 is mounted on the pad forming surface 20a of the semiconductor chip 20 via an adhesive member 41b such as FOW, and the semiconductor chip 20 and the semiconductor chip 30 are laminated.
  • the electrode pads of the semiconductor chip 30 and the bond fingers 15 formed near the boundary of the product forming portion 51 are connected by the wire 42 in the same manner as the semiconductor chip 20.
  • the connection between the electrode pad and the bond finger 15 by the wire 42 can also be performed by reverse bonding in order to lower the wire loop.
  • a sealing body 43 made of an insulating resin that collectively covers the chip mounting surface 50a of the wiring motherboard 50 is formed.
  • the wiring mother board 50 is closed with a molding die including an upper mold and a lower mold (not shown), for example.
  • a sealing body 43 is formed by press-fitting a thermosetting epoxy resin into a cavity formed by an upper mold and a lower mold from a gate (not shown), filling the cavity with resin, and then thermosetting the resin.
  • conductive solder balls 17 made of solder or the like are mounted on the plurality of lands 13 arranged in a grid pattern on the electrode formation surface 50b of the wiring mother board 50.
  • a ball mounting tool (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 13 on the wiring motherboard 50 is used.
  • the solder balls 17 are held in the suction holes, and the flux is transferred and formed on the held solder balls 17 and then mounted on the lands 13 of the wiring mother board 50 in a lump.
  • the solder balls 17 are fixed to the wiring mother board 50 by reflowing at a predetermined temperature.
  • the wiring mother board 50 in which the mounting of the solder balls 17 on all the lands 13 is completed is sent to the board dicing process.
  • the wiring mother board 50 is cut along the dicing lines 52 and separated into the product forming portions 51.
  • the wiring mother substrate 50 is supported by the dicing tape by bonding the sealing body 43 of the wiring mother substrate 50 to a dicing tape (not shown).
  • the wiring mother board 50 is cut vertically and horizontally along the dicing line 52 by a dicing blade (not shown), and the wiring mother board 50 is separated into pieces.
  • a DDP type semiconductor device as shown in FIG. 4 can be obtained by picking up from the dicing tape.
  • FIGS. 7A and 7B are diagrams showing semiconductor chips 20X and 30X used in the semiconductor device 1A according to the second embodiment of the present invention.
  • 10A and 10B the same components as those shown in FIGS. 7A and 7B are denoted by the same reference numerals.
  • 11A and 11B are plan views schematically showing the semiconductor device 1A.
  • 11A and 11B show the chip mounting surface 10a side on which a plurality of bond fingers 15 are formed.
  • FIG. 11A also shows the connection relationship between the lower semiconductor chip 20X and the bond finger rows 15a and 15b.
  • FIG. 11B also shows the connection relationship between the upper semiconductor chip 30X and the bond finger rows 15c and 15d.
  • 11A and 11B the same components as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.
  • the insulating layer on the rewiring layer 28 is omitted.
  • the lead direction of the rewiring layer of the corresponding pad (for example, the pad corresponding to CA0) in the CA-based pad row of the semiconductor chips 20 and 30 is set to the semiconductor chip 20 and the semiconductor chip 30. And in the opposite direction.
  • the semiconductor device 1A of the second embodiment in addition to the drawing direction of the rewiring layer of the corresponding pad in the CA pad row, the correspondence in the I / O pad row
  • the drawing direction of the rewiring layer of the pads to be performed (for example, pads corresponding to DQS) is also opposite in the semiconductor chip 20X and the semiconductor chip 30X.
  • the semiconductor device 1A of the second embodiment will be described focusing on differences from the semiconductor device 1 of the first embodiment.
  • the semiconductor chip 20X has the same configuration as the semiconductor chip 20 shown in FIG. 7A.
  • an I / O system connected to a pad for example, a pad corresponding to DQS; a seventh electrode
  • the pad (pad corresponding to DQS; fifth electrode) in the I / O-based pad row 31 corresponding to the pad (pad corresponding to DQS; fifth electrode) in the pad row 21 is formed on the semiconductor chip 30X. It is connected to a pad (pad corresponding to DQS; eighth electrode) in the I / O system connection pad row 33b.
  • the pad (pad corresponding to DQSB; sixth electrode) in the I / O system pad row 31 corresponding to the pad (pad corresponding to DQSB; sixth electrode) is connected to the I / O system of the semiconductor chip 30X. It is connected to a pad (pad corresponding to DQSB; seventh electrode) in the pad row 33a.
  • the fifth electrode and the sixth electrode are pads corresponding to, for example, DQS, DQSB, DM (TDQS), and TDQSB.
  • the electrode group further includes the fifth electrode and the sixth electrode in the I / O-based pad rows 21 and 31.
  • the first and second semiconductor chips 20X and 30X are further provided with pads (first pads) in the I / O connection pad rows 23a and 33a arranged on the pad forming surfaces 20a and 30a along the first sides 25a and 35a. 7) and pads (eighth electrodes) in the I / O connection pad rows 23b and 33b arranged on the pad forming surfaces 20a and 30a along the second sides 25b and 35b, respectively. .
  • the fifth electrode of the first semiconductor chip 20X is the seventh electrode of the first semiconductor chip 20X
  • the sixth electrode of the first semiconductor chip 20X is the first semiconductor chip.
  • Each of the 20X eighth electrodes is electrically connected.
  • the fifth electrode of the second semiconductor chip 30X is the eighth electrode of the second semiconductor chip 30X
  • the sixth electrode of the second semiconductor chip 30X is the second semiconductor chip. It is configured to be electrically connected to each of the 30X seventh electrodes.
  • chip pads such as DQS, DQSB, DM (TDQS), and TDQSB that cannot be handled by changing the allocation of I / O chip pads, can be arranged on the same side of the wiring board 10. Therefore, it is possible to further increase the speed of the semiconductor device.
  • FIGS. 7A and 7B are diagrams showing semiconductor chips 20Y and 30Y used in the semiconductor device 1B according to the third embodiment of the present invention. 12A and 12B, the same components as those shown in FIGS. 7A and 7B are denoted by the same reference numerals.
  • FIGS. 6A and 6B are plan views schematically showing the semiconductor device 1B.
  • 13A and 13B show the chip mounting surface side on which a plurality of bond fingers 15 are formed.
  • FIG. 13A also shows the connection relationship between the lower semiconductor chip 20Y and the bond finger rows 15a and 15b.
  • FIG. 13B also shows the connection relationship between the upper semiconductor chip 30Y and the bond finger rows 15c and 15d.
  • 13A and 13B the same components as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.
  • the insulating layer on the rewiring layer 28 is omitted.
  • the semiconductor chips 20Y and 30Y have the same configuration.
  • a switching circuit 60 as shown in FIG. 14 is formed.
  • the switching circuit 60 is an example of a setting circuit.
  • Switching circuit 60 includes receiving units 61 and 62 and selectors 63 and 64.
  • the number of switching circuits 60 is half that of the pads in the CA pad row 22.
  • the switching circuit 60 includes one pad (first electrode) in the CA system pad row 22 connected to the pad (third electrode) in the CA system connection pad row 24a, and a pad in the CA system connection pad row 24b.
  • One is provided for the combination of one pad (second electrode) in the CA-based pad row 22 connected to (fourth electrode).
  • the pads in the CA-based pad row 22 are divided into two pad units arranged in the pad arrangement direction, and one switching circuit 60 is provided for one set of the two pads. .
  • the accepting unit 61 accepts a signal from one pad (first electrode) in the CA system pad row 22 connected to the pad (third electrode) in the CA system connection pad row 24a.
  • the receiving unit 62 receives a signal from one pad (second electrode) in the CA pad array 22 connected to the pad (fourth electrode) in the CA connection pad array 24b.
  • the reception unit 61 When the reception unit 61 receives the signal, the reception unit 61 outputs the signal to the selectors 63 and 64. In addition, when receiving the signal, receiving unit 62 outputs the signal to selectors 63 and 64.
  • the output of the selector 63 is connected to an input unit 81 for inputting a signal into the semiconductor chip 20Y.
  • the output of the selector 64 is connected to an input unit 82 for inputting a signal into the semiconductor chip 20Y.
  • the selectors 63 and 64 also accept an MF signal whose signal level switches between “0” and “1” depending on, for example, whether or not a fuse in a fuse circuit (not shown) is cut.
  • the selector 63 When the MF signal is “0”, the selector 63 outputs a signal from the receiving unit 61 to the input unit 81, and the selector 64 outputs a signal from the receiving unit 62 to the input unit 82.
  • the selector 63 outputs a signal from the receiving unit 62 to the input unit 81, and the selector 64 outputs a signal from the receiving unit 61 to the input unit 82.
  • the number of switching circuits 60 is half that of the pads in the CA pad row 22.
  • the switching circuit 60 includes one pad (first electrode) in the CA system pad row 32 connected to the pad (third electrode) in the CA system connection pad row 34a, and a pad in the CA system connection pad row 34b.
  • One is provided for a combination of one pad (second electrode) in the CA-based pad row 32 connected to (fourth electrode).
  • the pads in the CA-based pad row 32 are divided into two pad units arranged in the pad arrangement direction, and one switching circuit 60 is provided for one set of the two pads. .
  • the accepting unit 61 accepts a signal from the pad (first electrode) in the CA system pad row 32 connected to the pad (third electrode) in the CA system connection pad row 34a.
  • the receiving unit 62 receives a signal from the pad (second electrode) in the CA system pad row 32 connected to the pad (fourth electrode) in the CA system connection pad row 34b.
  • the output of the selector 63 is connected to an input unit for inputting a signal into the semiconductor chip 30Y.
  • the output of the selector 64 is connected to an input unit for inputting a signal into the semiconductor chip 30Y.
  • the semiconductor device 1B includes the substrate 10, the first semiconductor chip 20Y mounted on the substrate 10, and the second semiconductor chip 30Y stacked on the first semiconductor chip 20Y. Have.
  • the first and second semiconductor chips 20Y and 30Y have first surfaces 20a and 30a defined by first and second sides 25a, 25b, 35a and 35b facing each other, and a first region in the central region of the first surfaces 20a and 30a.
  • a first connection state in which the first and second input sections 81 and 82 are connected to the first input section 81 and the second electrode is connected to the second input section 82;
  • the electrodes of the second input section 82 It has a second connection state of connecting the second electrode to the first input portion 81 as well as connection and switching circuit 60 to
  • the first electrode 22a of the first semiconductor chip 20Y is the third electrode 24aa of the first semiconductor chip 20Y, and the second electrode 22b of the first semiconductor chip 20Y is the first.
  • the semiconductor chip 20Y is configured to be electrically connected to the fourth electrode 24bb.
  • the first electrode 32a of the second semiconductor chip 30Y is the third electrode 34aa of the second semiconductor chip 30Y
  • the second electrode 32b of the second semiconductor chip 30Y is the second.
  • the first side 35a of the second semiconductor chip 30Y is on the second side 25b side of the first semiconductor chip 20Y, and is electrically connected to the fourth electrode 35bb of the semiconductor chip 30Y.
  • the second semiconductor chip 30Y is stacked on the first semiconductor chip 20Y so that the second side 35b is positioned on the first side 25a side of the first semiconductor chip 20Y.
  • the switching circuit 60 appropriately sets the first connection state and the second connection state, so that the substrate is mounted on the substrate as in the first embodiment.
  • the switching circuit 60 it is possible to reduce the difference in wiring length of the corresponding command address system in the upper and lower semiconductor chips.
  • the redistribution layers formed on the upper and lower semiconductor chips 20 and 30 have the same configuration. Therefore, only one type of semiconductor chip is prepared as the upper and lower semiconductor chips, and the cost can be reduced.
  • the rewiring of the pad is performed by providing the rewiring layer on the semiconductor chip.
  • the subwiring board is mounted on the semiconductor chip so that the rewiring of the pad is performed. May be.
  • the electrical connection between the first electrode of the semiconductor chips 20 and 20X and the third electrode of the semiconductor chips 20 and 20X, the second electrode of the semiconductor chips 20 and 20X, and Electrical connection between the fourth electrodes of the semiconductor chips 20 and 20X, electrical connection between the first electrodes of the semiconductor chips 30 and 30X and the fourth electrodes of the semiconductor chips 30 and 30X, and the semiconductor chip 30 , 30X, and the third electrode of the semiconductor chip 30, 30X, at least one connection may be made via a redistribution layer or a wiring substrate.
  • the electrical connection between the first electrode of the semiconductor chip 20Y and the third electrode of the semiconductor chip 20Y, the second electrode of the semiconductor chip 20Y, and the fourth electrode of the semiconductor chip 20Y Electrical connection between the first electrode of the semiconductor chip 30Y and the fourth electrode of the semiconductor chip 30Y, and the second electrode of the semiconductor chip 30Y and the third electrode of the semiconductor chip 30Y.
  • at least one of the connections may be made via a rewiring layer or a wiring board.
  • the semiconductor chip is applied to a semiconductor chip in which a plurality of electrode pads are arranged in a row in a central region of one surface.
  • a plurality of electrode pads in two or three or more rows in a central region of one surface.
  • a semiconductor chip in which is arranged may be applied.
  • a plurality of electrode rows arranged in parallel to the first side may be formed by electrodes included in the electrode group.

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Abstract

A semiconductor device includes a substrate and first and second semiconductor chips. Each of the first and second semiconductor chips includes: a surface that is divided according to first and second edges that are on opposite sides; an electrode group provided in a center area of the surface in parallel with the first edge, the electrode group including first and second electrodes of a command address type; third electrodes provided on the surface along the first edge; and fourth electrodes provided on the surface along the second edge. In the first semiconductor chip, the first electrodes are electrically connected with the third electrodes, and the second electrodes are electrically connected to the fourth electrodes. In the second semiconductor chip, the first electrodes are electrically connected with the fourth electrodes, and the second electrodes are electrically connected with the third electrodes. The second semiconductor chip is stacked on the first semiconductor chip in such a manner that the first edge of the second semiconductor chip is positioned on the second edge side of the first semiconductor chip and the second edge of the second semiconductor chip is positioned on the first edge side of the first semiconductor chip.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　配線基板上に２枚の半導体チップが積層されたDDP（Dual Die Package）型の半導体装置が知られている。 A DDP (Dual Die Package) type semiconductor device in which two semiconductor chips are stacked on a wiring board is known.
　特許文献１の図８～図１０には、２つの半導体チップがフェイスアップで積層された半導体装置が記載されている。以下、特許文献１の図８～図１０に示された半導体装置について説明する。 8 to 10 of Patent Document 1 describe a semiconductor device in which two semiconductor chips are stacked face up. Hereinafter, the semiconductor device shown in FIGS. 8 to 10 of Patent Document 1 will be described.
　特許文献１の図８に示されたように、この半導体装置は、配線基板と、第１の半導体チップと、第２の半導体チップと、を含む。第１の半導体チップと第２の半導体チップとは同一構成である。 As shown in FIG. 8 of Patent Document 1, this semiconductor device includes a wiring board, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip and the second semiconductor chip have the same configuration.
　また、特許文献１の図１０に示されたように、配線基板の電極形成面の一方の端部には、第１の半導体チップ用の複数のI/O（Input/Output）用ランド（以下「第１I/O用ランド」と称する）が形成されている。電極形成面の他方の端部には、第２の半導体チップ用の複数のI/O用ランド（以下「第２I/O用ランド」と称する）が形成されている。また、電極形成面の中央付近には、複数のCA（コマンド・アドレス）用ランドが形成されている。CA用ランドは、第１および第２の半導体チップと接続される。 As shown in FIG. 10 of Patent Document 1, a plurality of I / O (Input / Output) lands (hereinafter referred to as “I / O” lands) for the first semiconductor chip are formed at one end of the electrode formation surface of the wiring board. (Referred to as “first I / O land”). A plurality of I / O lands for the second semiconductor chip (hereinafter referred to as “second I / O lands”) are formed at the other end of the electrode formation surface. A plurality of CA (command address) lands are formed near the center of the electrode formation surface. The CA land is connected to the first and second semiconductor chips.
　特許文献１の図９（ｂ）に示されたように、配線基板のチップ搭載面には、第１の半導体チップと接続するためのボンドフィンガー列（以下「第１ボンドフィンガー列」と称する）が形成されている。 As shown in FIG. 9B of Patent Document 1, on the chip mounting surface of the wiring substrate, a bond finger row (hereinafter referred to as “first bond finger row”) for connection to the first semiconductor chip. Is formed.
　第１ボンドフィンガー列は、配線および貫通ビアを介して第１I/O用ランドと接続されたボンドフィンガー列と、配線および貫通ビアを介してCA用ランドと接続されたボンドフィンガー列と、に分類される。 The first bond finger row is classified into a bond finger row connected to the first I / O land via the wiring and through via, and a bond finger row connected to the CA land via the wiring and through via. Is done.
　また、特許文献１の図９（ａ）に示されたように、配線基板のチップ搭載面には、第２の半導体チップと接続するためのボンドフィンガー列（以下「第２ボンドフィンガー列」と称する）が形成されている。 Further, as shown in FIG. 9A of Patent Document 1, on the chip mounting surface of the wiring substrate, a bond finger row (hereinafter referred to as “second bond finger row”) for connection to the second semiconductor chip. Is formed).
　第２ボンドフィンガー列は、配線および貫通ビアを介して第２I/O用ランドと接続されたボンドフィンガー列と、CA用ランドと接続されたボンドフィンガー列と、に分類される。 The second bond finger row is classified into a bond finger row connected to the second I / O land via wiring and through vias, and a bond finger row connected to the CA land.
　このように、CA用ランドは、第１ボンドフィンガー列内のボンドフィンガーと共に、第２ボンドフィンガー列内のボンドフィンガーとも接続される。 Thus, the CA land is connected to the bond fingers in the second bond finger row as well as the bond fingers in the first bond finger row.
　特許文献１の図９（ｂ）に示されたように、第１の半導体チップは、矩形状であり、I/O系パッド列とCA系パッド列とを含む。 As shown in FIG. 9B of Patent Document 1, the first semiconductor chip has a rectangular shape and includes an I / O pad row and a CA pad row.
　I/O系パッド列とCA系パッド列は、第１の半導体チップの対向する一対の長辺と平行な中心線に沿って配置されている。I/O系パッド列とCA系パッド列は、一直線になるように直列に配置されている。I/O系パッド列は、第１の半導体チップの一方の端部側に配置されている。CA系パッド列は、第１の半導体チップの他方の端部側に配置されている。 The I / O pad row and the CA pad row are arranged along a center line parallel to a pair of long sides facing each other of the first semiconductor chip. The I / O system pad array and the CA system pad array are arranged in series so as to be in a straight line. The I / O system pad row is disposed on one end side of the first semiconductor chip. The CA-based pad row is disposed on the other end side of the first semiconductor chip.
　第１の半導体チップは、第１の半導体チップの一方の端部（I/O系パッド列が形成されている端部）が、配線基板の第１I/O用ランドが形成された端部側に位置するように、フェイスアップで、接着部材を介して、配線基板のチップ搭載面上に搭載される。 In the first semiconductor chip, one end of the first semiconductor chip (the end where the I / O pad array is formed) is the end side where the first I / O land of the wiring board is formed. It is mounted face-up on the chip mounting surface of the wiring board via an adhesive member.
　また、特許文献１の図９（ａ）に示されたように、第１の半導体チップと同一構成である第２の半導体チップは、第２の半導体チップの一方の端部（I/O系パッド列が形成されている端部）が、配線基板の第２I/O用ランドが形成された端部側に位置するように、フェイスアップで、接着部材を介して、第１の半導体チップ上に搭載される。 Further, as shown in FIG. 9A of Patent Document 1, the second semiconductor chip having the same configuration as the first semiconductor chip has one end (I / O system) of the second semiconductor chip. Face-up on the first semiconductor chip via an adhesive member so that the end where the pad row is formed is located on the end where the second I / O land is formed on the wiring board. Mounted on.
　つまり、第２の半導体チップは、自チップの中心を通る厚さ方向の直線を軸にして、第１半導体チップに対して１８０度回転させた状態で、第１半導体チップ上に積層される。 That is, the second semiconductor chip is stacked on the first semiconductor chip in a state where the second semiconductor chip is rotated 180 degrees with respect to the first semiconductor chip about a straight line in the thickness direction passing through the center of the chip.
　特許文献１の図９（ｂ）に示されたように、第１ボンドフィンガー列を構成する各ボンドフィンガーは、ワイヤにて、第１の半導体チップのI/O系パッドまたはCA系パッドと個別に接続される。 As shown in FIG. 9B of Patent Document 1, each bond finger constituting the first bond finger row is individually connected with an I / O pad or a CA pad of the first semiconductor chip by a wire. Connected to.
　また、特許文献１の図９（ａ）に示されたように、第２ボンドフィンガー列を構成する各ボンドフィンガーは、ワイヤにて、第２の半導体チップのI/O系パッドまたはCA系パッドと個別に接続される。 Further, as shown in FIG. 9A of Patent Document 1, each bond finger constituting the second bond finger row is a wire, an I / O pad or a CA pad of the second semiconductor chip. And connected individually.
　このため、配線基板の第１I/O用ランドは、ボンドフィンガーやワイヤを介して、第１の半導体チップのI/O系パッドと接続する。配線基板の第２I/O用ランドは、ボンドフィンガーやワイヤを介して、第２の半導体チップのI/O系パッドと接続する。 Therefore, the first I / O land of the wiring board is connected to the I / O pad of the first semiconductor chip via a bond finger or a wire. The second I / O land of the wiring board is connected to the I / O system pad of the second semiconductor chip via a bond finger or a wire.
　また、配線基板のCA用ランドは、ボンドフィンガーやワイヤを介して、第１の半導体チップのCA系パッドおよび第２の半導体チップのCA系パッドとそれぞれ接続される。 Also, the CA land of the wiring board is connected to the CA pad of the first semiconductor chip and the CA pad of the second semiconductor chip via bond fingers and wires, respectively.
特開２０１１－２４９５８２号公報JP 2011-249582 A
　複数の半導体チップが積層された半導体装置において、半導体チップの中央領域に電極パッド列が配置される場合、半導体チップの電極パッドと配線基板のボンドフィンガーとを接続するワイヤが長くなる。このため、FOW（Film Over Wire）でのチップ積層が難しくなる。よって、RDL（Redistribution Layer）技術を用いて、電極パッド列を半導体チップのエッジ近傍位置に再配線することが検討されている。 In a semiconductor device in which a plurality of semiconductor chips are stacked, when the electrode pad row is arranged in the central region of the semiconductor chip, the wire connecting the electrode pad of the semiconductor chip and the bond finger of the wiring board becomes long. This makes chip stacking difficult with FOW (Film Over Wire). Therefore, it has been studied to redistribute the electrode pad row near the edge of the semiconductor chip using RDL (Redistribution Layer) technology.
　そのため、例えば、電極パッドを半導体チップのエッジ近傍位置に再配線した同一構造の２つの半導体チップを用いて、上述した従来技術のように、配線基板上に搭載された下側の半導体チップに対して、自チップの中心を通る厚さ方向の直線を軸にして１８０度回転させた状態で、上側の半導体チップを下側の半導体チップ上に積層する手法が考えられる。 Therefore, for example, by using two semiconductor chips having the same structure in which the electrode pads are rewired near the edge of the semiconductor chip, the lower semiconductor chip mounted on the wiring board is used as in the above-described conventional technology. Thus, a method is conceivable in which the upper semiconductor chip is stacked on the lower semiconductor chip while being rotated 180 degrees around the straight line in the thickness direction passing through the center of the own chip.
　しかしながら、この手法では、CA用ランドと下側の半導体チップのCA用電極パッドとを接続する配線の長さと、そのCA用ランドと上側の半導体チップのCA用電極パッドとを接続する配線の長さと、の差が大きくなってしまう。 However, in this method, the length of the wiring that connects the CA land and the CA electrode pad of the lower semiconductor chip and the length of the wiring that connects the CA land and the CA electrode pad of the upper semiconductor chip are the same. And the difference will be larger.
　この差は、上下の半導体チップの動作タイミングのずれの調整を困難にし、また、DDP型の半導体装置の高速動作を阻害する要因になる恐れがあるということを、本願発明者は明らかにした。以下、この問題について、図１Ａ、１Ｂ、２Ａ、２Ｂ、３を参照して説明する。 The inventor of the present application has clarified that this difference makes it difficult to adjust the operation timing shift between the upper and lower semiconductor chips and may hinder the high-speed operation of the DDP type semiconductor device. This problem will be described below with reference to FIGS. 1A, 1B, 2A, 2B, and 3.
　図１Ａは、下側の半導体チップ１０１の一例を示した図である。図１Ｂは、上側の半導体チップ１０２の一例を示した図である。 FIG. 1A is a diagram showing an example of the lower semiconductor chip 101. FIG. 1B is a diagram illustrating an example of the upper semiconductor chip 102.
　上側の半導体チップ１０２は、下側の半導体チップ１０１と同一構成である。 The upper semiconductor chip 102 has the same configuration as the lower semiconductor chip 101.
　下側の半導体チップ１０１には、I/O系パッド列１０１ａとCA系パッド列１０１ｂの他に、I/O系接続パッド列１０１ｃとCA系接続パッド列１０１ｄが形成されている。I/O系接続パッド列１０１ｃとCA系接続パッド列１０１ｄは、それぞれ、再配線層１０１ｅを介して、I/O系パッド列１０１ａ、CA系パッド列１０１ｂと接続されている。 In the lower semiconductor chip 101, in addition to the I / O pad row 101a and the CA pad row 101b, an I / O connection pad row 101c and a CA connection pad row 101d are formed. The I / O system connection pad row 101c and the CA system connection pad row 101d are respectively connected to the I / O system pad row 101a and the CA system pad row 101b via the rewiring layer 101e.
　上側の半導体チップ１０２には、I/O系パッド列１０２ａとCA系パッド列１０２ｂの他に、I/O系接続パッド列１０２ｃとCA系接続パッド列１０２ｄが形成されている。 On the upper semiconductor chip 102, in addition to the I / O pad row 102a and the CA pad row 102b, an I / O connection pad row 102c and a CA connection pad row 102d are formed.
　上側の半導体チップ１０２のI/O系パッド列１０２ａとCA系パッド列１０２ｂとI/O系接続パッド列１０２ｃとCA系接続パッド列１０２ｄは、それぞれ、下側の半導体チップ１０１のI/O系パッド列１０１ａ、CA系パッド列１０１ｂ、I/O系接続パッド列１０１ｃ、CA系接続パッド列１０１ｄと対応している。 The I / O system pad row 102a, CA system pad row 102b, I / O system connection pad row 102c, and CA system connection pad row 102d of the upper semiconductor chip 102 are respectively connected to the I / O system of the lower semiconductor chip 101. This corresponds to the pad row 101a, the CA-type pad row 101b, the I / O-type connection pad row 101c, and the CA-type connection pad row 101d.
　図２Ａは、配線基板１０３と下側の半導体チップ１０１との接続関係を示した図である。図２Ｂは、配線基板１０３と上側の半導体チップ１０２との接続関係を示した図である。 FIG. 2A is a diagram showing a connection relationship between the wiring board 103 and the lower semiconductor chip 101. FIG. 2B is a diagram illustrating a connection relationship between the wiring substrate 103 and the upper semiconductor chip 102.
　配線基板１０３のチップ搭載面１０３－１には、I/O系ピン用ボンドフィンガー列１０３ａ１と、CA系ピン用ボンドフィンガー列１０３ａ２と、I/O系ピン用ボンドフィンガー列１０３ｂ１と、CA系ピン用ボンドフィンガー列１０３ｂ２とが形成されている。 The chip mounting surface 103-1 of the wiring substrate 103 has an I / O pin bond finger row 103 a 1, a CA pin bond finger row 103 a 2, an I / O pin bond finger row 103 b 1, and a CA pin. Bond finger row 103b2 is formed.
　図２Ａに示したように、I/O系ピン用ボンドフィンガー列１０３ａ１は、下側の半導体チップ１０１のI/O系接続パッド列１０１ｃとワイヤ１０４を介して接続される。CA系ピン用ボンドフィンガー列１０３ａ２は、下側の半導体チップ１０１のCA系接続パッド列１０１ｄとワイヤ１０４を介して接続される。 As shown in FIG. 2A, the I / O pin bond finger row 103 a 1 is connected to the I / O connection pad row 101 c of the lower semiconductor chip 101 via the wire 104. The CA pin bond finger row 103 a 2 is connected to the CA connection pad row 101 d of the lower semiconductor chip 101 through the wire 104.
　また、図２Ｂに示したように、I/O系ピン用ボンドフィンガー列１０３ｂ１は、上側の半導体チップ１０２のI/O系接続パッド列１０２ｃとワイヤ１０４を介して接続される。CA系ピン用ボンドフィンガー列１０３ｂ２は、上側の半導体チップ１０２のCA系接続パッド列１０２ｄとワイヤ１０４を介して接続される。 Further, as shown in FIG. 2B, the I / O pin bond finger row 103 b 1 is connected to the I / O connection pad row 102 c of the upper semiconductor chip 102 via the wire 104. The CA pin bond finger row 103b2 is connected to the CA connection pad row 102d of the upper semiconductor chip 102 via the wire 104.
　ここで、下側の半導体チップ１０１のCA0用パッド１０１ｄ０と接続する、CA系ピン用ボンドフィンガー列１０３ａ２内のボンドフィンガー１０３ａ２０（図２Ａ参照）と、上側の半導体チップ１０２のCA0用パッド１０２ｄ０と接続する、CA系ピン用ボンドフィンガー列１０３ｂ２内のボンドフィンガー１０３ｂ２０（図２Ｂ参照）とは、共通のCA0用ランドと接続されることになる。 Here, the bond finger 103a20 (see FIG. 2A) in the CA pin bond finger row 103a2 connected to the CA0 pad 101d0 of the lower semiconductor chip 101 and the CA0 pad 102d0 of the upper semiconductor chip 102 are connected. The bond pin 103b20 (see FIG. 2B) in the CA pin bond finger row 103b2 is connected to a common CA0 land.
　図３は、ボンドフィンガー１０３ａ２０とCA0用ランド１０５ｃ０との接続と、ボンドフィンガー１０３ｂ２０とCA0用ランド１０５ｃ０との接続と、を説明するための図である。 FIG. 3 is a diagram for explaining the connection between the bond finger 103a20 and the CA0 land 105c0 and the connection between the bond finger 103b20 and the CA0 land 105c0.
　図３において、チップ搭載面１０３－１の裏側の面である電極形成面１０３－２には、下側の半導体チップ１０１用のI/O用ランド１０５ａと、上側の半導体チップ１０２用のI/O用ランド１０５ｂと、CA用ランド１０５ｃとが形成されている。 In FIG. 3, an electrode forming surface 103-2, which is the back surface of the chip mounting surface 103-1, is provided with an I / O land 105a for the lower semiconductor chip 101 and an I / O for the upper semiconductor chip 102. An O land 105b and a CA land 105c are formed.
　CA用ランド１０５ｃのうち、CA0用ランド１０５ｃ０は、ボンドフィンガー１０３ａ２０とボンドフィンガー１０３ｂ２０に接続される。 Among the CA lands 105c, the CA0 lands 105c0 are connected to the bond fingers 103a20 and 103b20.
　図３に示したように、CA0用ランド１０５ｃ０からボンドフィンガー１０３ａ２０までの配線の長さと、CA0用ランド１０５ｃ０からボンドフィンガー１０３ｂ２０までの配線の長さとは、著しく異なる。この配線の長さの差は、CA0用ランド１０５ｃ０がボンドフィンガー１０３ａ２０と１０３ｂ２０のいずれか一方と近い場合ほど大きくなる。 As shown in FIG. 3, the length of the wiring from the CA0 land 105c0 to the bond finger 103a20 is significantly different from the length of the wiring from the CA0 land 105c0 to the bond finger 103b20. The difference in the length of the wiring becomes larger as the CA0 land 105c0 is closer to one of the bond fingers 103a20 and 103b20.
　この配線の長さの差が、上下の半導体チップの動作タイミングのずれの調整を困難にし、また、半導体装置の高速動作を阻害する要因になってしまう。 This difference in wiring length makes it difficult to adjust the deviation of the operation timing of the upper and lower semiconductor chips, and becomes a factor that hinders the high-speed operation of the semiconductor device.
　本発明の半導体装置は、
　基板と、前記基板上に搭載された第１の半導体チップと、前記第１の半導体チップ上に積層された第２の半導体チップと、を有し、
　前記第１と第２の半導体チップは、
　互いに対向する第１と第２の辺によって区画された一面と、
　前記一面の中央領域に前記第１の辺に平行に配置されたコマンドアドレス系の第１と第２の電極を含む電極群と、
　前記第１の辺に沿って前記一面に配置された第３の電極と、
　前記第２の辺に沿って前記一面に配置された第４の電極と、をそれぞれ有し、
　前記第１の半導体チップは、前記第１の半導体チップの前記第１の電極が前記第１の半導体チップの前記第３の電極に、前記第１の半導体チップの前記第２の電極が前記第１の半導体チップの前記第４の電極にそれぞれ電気的に接続するように構成され、
　前記第２の半導体チップは、前記第２の半導体チップの前記第１の電極が前記第２の半導体チップの前記第４の電極に、前記第２の半導体チップの前記第２の電極が前記第２の半導体チップの前記第３の電極にそれぞれ電気的に接続するように構成され、前記第２の半導体チップの前記第１の辺が前記第１の半導体チップの前記第２の辺側に、前記第２の半導体チップの前記第２の辺が前記第１の半導体チップの前記第１の辺側にそれぞれ位置するように、前記第１の半導体チップ上に積層されている。 The semiconductor device of the present invention is
A substrate, a first semiconductor chip mounted on the substrate, and a second semiconductor chip stacked on the first semiconductor chip,
The first and second semiconductor chips are:
A surface defined by first and second sides facing each other;
A group of electrodes including first and second electrodes of a command address system arranged in a central region of the one surface in parallel with the first side;
A third electrode disposed on the one surface along the first side;
Each having a fourth electrode disposed on the one surface along the second side,
In the first semiconductor chip, the first electrode of the first semiconductor chip is the third electrode of the first semiconductor chip, and the second electrode of the first semiconductor chip is the first electrode. Each electrically connected to the fourth electrode of one semiconductor chip,
In the second semiconductor chip, the first electrode of the second semiconductor chip is the fourth electrode of the second semiconductor chip, and the second electrode of the second semiconductor chip is the first electrode. Each of the second semiconductor chips is electrically connected to the third electrode, and the first side of the second semiconductor chip is on the second side of the first semiconductor chip, The second semiconductor chip is stacked on the first semiconductor chip so that the second side of the second semiconductor chip is positioned on the first side of the first semiconductor chip.
　このため、第１の半導体チップでは、第１の電極が第３の電極に、第２の電極が第４の電極にそれぞれ電気的に接続するように構成されている。第２の半導体チップでは、第１の電極が第４の電極に、第２の電極が第３の電極にそれぞれ電気的に接続するように構成されている。そして、第２の半導体チップは、第２の半導体チップの第１の辺が第１の半導体チップの第２の辺側に、第２の半導体チップの第２の辺が第１の半導体チップの第１の辺側にそれぞれ位置するように、第１の半導体チップ上に積層されている。 Therefore, the first semiconductor chip is configured such that the first electrode is electrically connected to the third electrode and the second electrode is electrically connected to the fourth electrode. The second semiconductor chip is configured such that the first electrode is electrically connected to the fourth electrode, and the second electrode is electrically connected to the third electrode. In the second semiconductor chip, the first side of the second semiconductor chip is on the second side of the first semiconductor chip, and the second side of the second semiconductor chip is the first semiconductor chip. They are stacked on the first semiconductor chip so as to be positioned on the first side.
　したがって、第１の半導体チップの第１の電極に接続された第３の電極と、第２の半導体チップの第１の電極に接続された第４の電極とを、第１の半導体チップの第１の辺側に配置できる。また、第１の半導体チップの第２の電極に接続された第４の電極と、第２の半導体チップの第２の電極に接続された第３の電極とを、第１の半導体チップの第２の辺側に配置できる。このため、基板上での上下の半導体チップにおける対応するコマンドアドレス系の配線長の差を低減することが可能になる。 Therefore, the third electrode connected to the first electrode of the first semiconductor chip and the fourth electrode connected to the first electrode of the second semiconductor chip are connected to the first electrode of the first semiconductor chip. 1 can be arranged on one side. In addition, the fourth electrode connected to the second electrode of the first semiconductor chip and the third electrode connected to the second electrode of the second semiconductor chip are connected to the first electrode of the first semiconductor chip. It can be arranged on the two sides. For this reason, it becomes possible to reduce the difference in the wiring length of the corresponding command address system in the upper and lower semiconductor chips on the substrate.
　本発明によれば、配線基板上での上下の半導体チップにおける対応するコマンドアドレス系の配線長の差を低減することが可能になる。このため、この配線長の差に伴う動作タイミングのずれの調整が容易になり、半導体装置の高速化を図ることが可能になる。 According to the present invention, it is possible to reduce the difference in the wiring length of the corresponding command address system in the upper and lower semiconductor chips on the wiring board. For this reason, it becomes easy to adjust the shift of the operation timing due to the difference in the wiring length, and the speed of the semiconductor device can be increased.
DDR型半導体装置で用いられる半導体チップの例を示した図である。It is the figure which showed the example of the semiconductor chip used with a DDR type semiconductor device. DDR型半導体装置で用いられる半導体チップの例を示した図である。It is the figure which showed the example of the semiconductor chip used with a DDR type semiconductor device. 半導体チップが搭載されたDDR型半導体装置の一例を示した図である。It is the figure which showed an example of the DDR type semiconductor device with which the semiconductor chip was mounted. 半導体チップが搭載されたDDR型半導体装置の一例を示した図である。It is the figure which showed an example of the DDR type semiconductor device with which the semiconductor chip was mounted. DDR型半導体装置の電極形成面側を示した図である。It is the figure which showed the electrode formation surface side of the DDR type semiconductor device. 本発明の第１実施形態の半導体装置１を概略的に示す断面図である。1 is a cross-sectional view schematically showing a semiconductor device 1 according to a first embodiment of the present invention. 半導体装置１の電極形成面側を示した平面図である。3 is a plan view showing an electrode forming surface side of the semiconductor device 1; FIG. 半導体装置１のチップ搭載面側を示した平面図である。2 is a plan view showing a chip mounting surface side of the semiconductor device 1; FIG. 半導体装置１のチップ搭載面側を示した平面図である。2 is a plan view showing a chip mounting surface side of the semiconductor device 1; FIG. 半導体チップ２０を示した平面図である。1 is a plan view showing a semiconductor chip 20. 半導体チップ３０を示した平面図である。2 is a plan view showing a semiconductor chip 30. FIG. CA0用ボンドフィンガーとCA0用ランドとの接続を説明するための図である。It is a figure for demonstrating the connection of the bond finger for CA0, and the land for CA0. 半導体装置１の製造方法の各工程を概略的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1. 半導体装置１の製造方法の各工程を概略的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1. 半導体装置１の製造方法の各工程を概略的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1. 半導体装置１の製造方法の各工程を概略的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1. 半導体装置１の製造方法の各工程を概略的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1. 半導体装置１の製造方法の各工程を概略的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1. 本発明の第２実施形態の半導体装置１Ａに用いられる半導体チップ２０Ｘを示した図である。It is a figure showing semiconductor chip 20X used for semiconductor device 1A of a 2nd embodiment of the present invention. 本発明の第２実施形態の半導体装置１Ａに用いられる半導体チップ３０Ｘを示した図である。It is the figure which showed the semiconductor chip 30X used for the semiconductor device 1A of 2nd Embodiment of this invention. 半導体装置１Ａを概略的に示す平面図である。1 is a plan view schematically showing a semiconductor device 1A. 半導体装置１Ａを概略的に示す平面図である。1 is a plan view schematically showing a semiconductor device 1A. 本発明の第３実施形態の半導体装置１Ｂに用いられる半導体チップ２０Ｙを示した図である。It is the figure which showed semiconductor chip 20Y used for the semiconductor device 1B of 3rd Embodiment of this invention. 本発明の第３実施形態の半導体装置１Ｂに用いられる半導体チップ３０Ｙを示した図である。It is the figure which showed semiconductor chip 30Y used for the semiconductor device 1B of 3rd Embodiment of this invention. 半導体装置１Ｂを概略的に示す平面図である。It is a top view which shows roughly the semiconductor device 1B. 半導体装置１Ｂを概略的に示す平面図である。It is a top view which shows roughly the semiconductor device 1B. 切替回路６０を示した図である。FIG. 6 is a diagram showing a switching circuit 60.
　以下、本発明の実施形態について図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第１実施形態）
　図４は、本発明の第１実施形態の半導体装置１を概略的に示す断面図である。図４は、基板に垂直な方向の断面を示している。半導体装置１は、２つの半導体チップ２０、３０が積層されたDDP型の半導体パッケージである。半導体チップ２０は、第１の半導体チップの一例である。半導体チップ３０は、第２の半導体チップの一例である。 (First embodiment)
FIG. 4 is a cross-sectional view schematically showing the semiconductor device 1 according to the first embodiment of the present invention. FIG. 4 shows a cross section in a direction perpendicular to the substrate. The semiconductor device 1 is a DDP type semiconductor package in which two semiconductor chips 20 and 30 are stacked. The semiconductor chip 20 is an example of a first semiconductor chip. The semiconductor chip 30 is an example of a second semiconductor chip.
　図５は、図４に示す半導体装置１を概略的に示す平面図である。図５は、複数のランド１３が形成された電極形成面１０ｂ側を示している。 FIG. 5 is a plan view schematically showing the semiconductor device 1 shown in FIG. FIG. 5 shows the electrode forming surface 10b side on which a plurality of lands 13 are formed.
　図６Ａ、６Ｂは、図４に示す半導体装置１を概略的に示す平面図である。図６Ａ、６Ｂは、複数のボンドフィンガー１５が形成されたチップ搭載面１０ａ側を示している。図６Ａは、下側の半導体チップ２０とボンドフィンガー列１５ａ、１５ｂとの接続関係も示す。図６Ｂは、上側の半導体チップ３０とボンドフィンガー列１５ｃ、１５ｄとの接続関係も示す。 6A and 6B are plan views schematically showing the semiconductor device 1 shown in FIG. 6A and 6B show the chip mounting surface 10a side on which a plurality of bond fingers 15 are formed. FIG. 6A also shows the connection relationship between the lower semiconductor chip 20 and the bond finger rows 15a and 15b. FIG. 6B also shows a connection relationship between the upper semiconductor chip 30 and the bond finger rows 15c and 15d.
　図７Ａは、下側の半導体チップ２０を示した平面図である。図７Ｂは、上側の半導体チップ３０を示した平面図である。 FIG. 7A is a plan view showing the lower semiconductor chip 20. FIG. 7B is a plan view showing the upper semiconductor chip 30.
　なお、図６Ａ、６Ｂ、７Ａ、７Ｂでは、再配線層２８上の絶縁層を省略している。 6A, 6B, 7A, and 7B, the insulating layer on the rewiring layer 28 is omitted.
　半導体装置１は、例えば０．２mm厚のガラスエポキシ基材（絶縁基板）からなる配線基板１０を有している。配線基板１０は、ほぼ矩形状に形成されている。 The semiconductor device 1 has a wiring substrate 10 made of, for example, a 0.2 mm thick glass epoxy base material (insulating substrate). The wiring board 10 is formed in a substantially rectangular shape.
　配線基板１０は、２つの半導体チップ２０、３０が積層されるチップ搭載面１０ａと、チップ搭載面１０ａの裏側の面である電極形成面１０ｂとを有している。 The wiring substrate 10 has a chip mounting surface 10a on which the two semiconductor chips 20 and 30 are stacked, and an electrode forming surface 10b that is the back surface of the chip mounting surface 10a.
　チップ搭載面１０ａには、Cu等の導電材料からなる配線１８が形成されている。配線１８は、部分的に、絶縁膜、例えばソルダーレジスト１４で覆われている。 The wiring 18 made of a conductive material such as Cu is formed on the chip mounting surface 10a. The wiring 18 is partially covered with an insulating film, for example, a solder resist 14.
　チップ搭載面１０ａにおいて、ソルダーレジスト１４から露出された配線領域には、それぞれボンドフィンガー１５が形成されている。 Bond fingers 15 are formed in the wiring regions exposed from the solder resist 14 on the chip mounting surface 10a.
　電極形成面１０ｂには、それぞれ半田ボール１７が搭載された複数のランド（外部電極）１３が形成されている。ランド１３は、配線基板１０に形成された貫通ビア１９と配線１８とを介して、チップ搭載面１０ａのボンドフィンガー１５と電気的に接続されている。 A plurality of lands (external electrodes) 13 on which solder balls 17 are mounted are formed on the electrode forming surface 10b. The lands 13 are electrically connected to the bond fingers 15 on the chip mounting surface 10 a through through vias 19 and wirings 18 formed in the wiring substrate 10.
　図５に示すように、電極形成面１０ｂに形成されたランド１３ａ－１３ｃは、それぞれ所定の間隔で格子状に配置されている。 As shown in FIG. 5, the lands 13a-13c formed on the electrode forming surface 10b are arranged in a grid at predetermined intervals.
　各ランド１３は、ボンドフィンガー列１５ａ－１５ｄのいずれかに属するボンドフィンガーと、ワイヤ４２と、I/O系接続パッド列２３ａ、２３ｂ、３３ａ、３３ｂまたはCA系接続パッド列２４ａ、２４ｂ、３４ａ、３４ｂ内のいずれかに属する接続パッドと、再配線層２８とを介して、I/O系パッド列２１、３１またはCA系パッド列２２、３２のいずれかの属するパッドと、電気的に接続されている。 Each land 13 includes a bond finger belonging to one of the bond finger rows 15a to 15d, a wire 42, an I / O connection pad row 23a, 23b, 33a, 33b, or a CA connection pad row 24a, 24b, 34a, The connection pads belonging to any one of 34 b and the rewiring layer 28 are electrically connected to the pads belonging to any of the I / O pad rows 21 and 31 or the CA pad rows 22 and 32. ing.
　ランド１３は、半導体チップ２０、３０のパッド列２１、２２、３１、３２の入出力系統に応じて、２種類の系統に分類される。 The land 13 is classified into two types according to the input / output system of the pad rows 21, 22, 31, and 32 of the semiconductor chips 20 and 30.
　１つは、データ（DQ）系信号およびDQ系電源/GND、すなわちInput/Output系の電極パッド（I/O系パッド）列２１、３１に接続されるI/O用ランド１３ａ、１３ｃである。 One is I / O lands 13a and 13c connected to data (DQ) system signals and DQ system power supply / GND, that is, input / output system electrode pad (I / O system pad) rows 21 and 31. .
　もう１つは、コマンドアドレス系の電極パッド（CA系パッド）列２２、３２に接続されるCA用ランド１３ｂである。 The other is the CA land 13b connected to the command address system electrode pad (CA system pad) rows 22 and 32.
　I/O用ランド１３ａ、１３ｃは、図５に示すように、電極形成面１０ｂの両端部に分かれて配置されている。 As shown in FIG. 5, the I / O lands 13a and 13c are arranged separately at both ends of the electrode forming surface 10b.
　各端部に配置されたI/O用ランド１３ａ、１３ｃは、半導体チップ２０、３０用にそれぞれ割り当てられている。本実施形態では、図５で見て上側の端部（第１の端部）１１には、半導体チップ２０に対応するI/O用ランド１３ａが配置されている。また、図５で見て下側の端部（第２の端部）１２には、半導体チップ３０に対応するI/O用ランド１３ｃが配置されている。また、I/O用ランド１３ａ、１３ｃの間に、CA用ランド１３ｂが配置されている。 The I / O lands 13a and 13c arranged at each end are assigned to the semiconductor chips 20 and 30, respectively. In the present embodiment, an I / O land 13a corresponding to the semiconductor chip 20 is disposed at an upper end portion (first end portion) 11 as viewed in FIG. In addition, an I / O land 13c corresponding to the semiconductor chip 30 is disposed at the lower end (second end) 12 as viewed in FIG. A CA land 13b is disposed between the I / O lands 13a and 13c.
　図４に示すように、チップ搭載面１０ａ上には、DAF（Die Attached Film）、あるいはエラストマ等の接着部材４１ａを介して、半導体チップ２０が搭載されている。 As shown in FIG. 4, the semiconductor chip 20 is mounted on the chip mounting surface 10a via an adhesive member 41a such as DAF (Die Attached Film) or elastomer.
　半導体チップ２０は、図６Ａ、７Ａに示すように、ほぼ矩形の板状に形成されている。半導体チップ２０では、一方の面であるパッド形成面２０ａに、例えばメモリ回路と複数の電極パッドとが形成されている。 The semiconductor chip 20 is formed in a substantially rectangular plate shape as shown in FIGS. 6A and 7A. In the semiconductor chip 20, for example, a memory circuit and a plurality of electrode pads are formed on a pad forming surface 20 a that is one surface.
　図７Ａを参照すると、パッド形成面２０ａは、互いに対向する長辺２５ａ、２５ｂにて区画された一面である。長辺２５ａは第１の辺の一例である。長辺２５ｂは第２の辺の一例である。 Referring to FIG. 7A, the pad forming surface 20a is a surface partitioned by long sides 25a and 25b facing each other. The long side 25a is an example of a first side. The long side 25b is an example of the second side.
　図７Ａおよび図４を参照すると、パッド形成面２０ａには、I/O系パッド列２１と、CA系パッド列２２と、I/O系接続パッド列２３ａおよび２３ｂと、CA系接続パッド列２４ａおよび２４ｂと、再配線層２８と、絶縁層２９ａおよび２９ｂが形成されている。 Referring to FIGS. 7A and 4, the pad forming surface 20a includes an I / O system pad row 21, a CA system pad row 22, I / O system connection pad rows 23a and 23b, and a CA system connection pad row 24a. 24b, a rewiring layer 28, and insulating layers 29a and 29b are formed.
　I/O系パッド列２１に含まれるパッド（電極）は、I/O系接続パッド列２３ａに含まれるパッドと再配線層２８を介して接続される電極パッドと、I/O系接続パッド列２３ｂに含まれるパッドと再配線層２８を介して接続される電極パッドと、を含む。 The pads (electrodes) included in the I / O system pad row 21 are electrode pads connected to the pads included in the I / O system connection pad row 23a via the rewiring layer 28, and I / O system connection pad rows. 23b and an electrode pad connected via the redistribution layer 28.
　なお、再配線層２８の下には絶縁層２９ａが形成されている。再配線層２８の上には、パッド部分を除いて絶縁層２９ｂが形成されている。 Note that an insulating layer 29 a is formed under the rewiring layer 28. On the rewiring layer 28, an insulating layer 29b is formed except for the pad portion.
　CA系パッド列２２に含まれるパッド（電極）は、CA系接続パッド列２４ａに含まれるパッドと再配線層２８を介して接続される電極パッド（例えば、パッド２２ａ）と、CA系接続パッド列２４ｂに含まれるパッドと再配線層２８を介して接続される電極パッド（例えば、パッド２２ｂ）と、を含む。なお、パッド２２ａは第１の電極の一例である。パッド２２ｂは、第２の電極の一例である。 The pads (electrodes) included in the CA system pad row 22 are the electrode pads (for example, the pad 22a) connected to the pads included in the CA system connection pad row 24a via the rewiring layer 28, and the CA system connection pad row. 24b and an electrode pad (for example, pad 22b) connected via the redistribution layer 28. The pad 22a is an example of the first electrode. The pad 22b is an example of a second electrode.
　I/O系パッド列２１とCA系パッド列２２とは、図７Ａに示すように、矩形状の半導体チップ２０の対向する一対の長辺２５ａ、２５ｂと平行な中心線に沿って、一直線になるように直列に配置されている。I/O系パッド列２１は、半導体チップ２０の第１の端部２６側に寄せて配置されている。CA系パッド列２２は、第２の端部２７側に寄せて配置されている。なお、I/O系パッド列２１とCA系パッド列２２は、電極群に含まれる。 As shown in FIG. 7A, the I / O system pad row 21 and the CA system pad row 22 are aligned along a center line parallel to a pair of opposing long sides 25a and 25b of the rectangular semiconductor chip 20. Are arranged in series. The I / O system pad row 21 is arranged close to the first end portion 26 side of the semiconductor chip 20. The CA pad row 22 is arranged close to the second end 27 side. The I / O pad row 21 and the CA pad row 22 are included in the electrode group.
　I/O系接続パッド列２３ａとCA系接続パッド列２４ａは、長辺２５ａに沿って、一直線になるように直列にパッド形成面２０ａに配置されている。I/O系接続パッド列２３ａは、半導体チップ２０の第１の端部２６側に配置されている。CA系接続パッド列２４ａは、第２の端部２７側に配置されている。なお、CA系接続パッド列２４ａに含まれる電極パッド（例えば、パッド２４ａａ）は、第３の電極の一例である。 The I / O system connection pad row 23a and the CA system connection pad row 24a are arranged in series on the pad forming surface 20a so as to be in a straight line along the long side 25a. The I / O system connection pad row 23 a is disposed on the first end portion 26 side of the semiconductor chip 20. The CA connection pad row 24a is arranged on the second end portion 27 side. The electrode pad (for example, pad 24aa) included in the CA-based connection pad row 24a is an example of a third electrode.
　I/O系接続パッド列２３ｂとCA系接続パッド列２４ｂは、長辺２５ｂに沿って、一直線になるように直列にパッド形成面２０ａに配置されている。I/O系接続パッド列２３ｂは、第１の端部２６側に配置されている。CA系接続パッド列２４ｂは、第２の端部２７側に配置されている。なお、CA系接続パッド列２４ｂに含まれる電極パッド（例えば、パッド２４ｂｂ）は、第４の電極の一例である。 The I / O connection pad row 23b and the CA connection pad row 24b are arranged in series on the pad forming surface 20a so as to be in a straight line along the long side 25b. The I / O system connection pad row 23b is disposed on the first end portion 26 side. The CA connection pad row 24b is disposed on the second end 27 side. The electrode pad (for example, pad 24bb) included in the CA-based connection pad row 24b is an example of a fourth electrode.
　I/O系接続パッド列２３ａ、２３ｂおよびCA系接続パッド２４ａ、２４ｂを除くパッド形成面２０ａには、パッド形成面２０ａを保護するための図示しないパッシベーション膜が形成されている。 A passivation film (not shown) for protecting the pad formation surface 20a is formed on the pad formation surface 20a excluding the I / O connection pad rows 23a and 23b and the CA connection pads 24a and 24b.
　半導体チップ２０は、図６Ａに示すように、半導体チップ２０の第１の端部２６が配線基板１０の第１の端部１１側に位置するように、フェイスアップで配線基板１０上に配置されている。すなわち、半導体チップ２０は、半導体チップ２０の第１の端部２６に配置されたI/O系接続パッド列２３ａおよび２３ｂが、配線基板１０の第１の端部１１に配置された半導体チップ２０用のI/O用ランド１３ａおよびボンドフィンガー列１５ａと隣接するように、配置されている。 As shown in FIG. 6A, the semiconductor chip 20 is arranged on the wiring substrate 10 face up so that the first end portion 26 of the semiconductor chip 20 is located on the first end portion 11 side of the wiring substrate 10. ing. That is, in the semiconductor chip 20, the I / O system connection pad rows 23 a and 23 b arranged at the first end portion 26 of the semiconductor chip 20 are arranged at the first end portion 11 of the wiring substrate 10. The I / O land 13a and the bond finger row 15a are adjacent to each other.
　半導体チップ２０のI/O系接続パッド列２３ａおよび２３ｂに含まれる各パッドは、ボンドフィンガー列１５ａに含まれるボンドフィンガーと、例えばAuやCu等からなる導電性のワイヤ４２により個別に結線されることで、電気的に接続されている。 Each pad included in the I / O system connection pad rows 23a and 23b of the semiconductor chip 20 is individually connected to a bond finger included in the bond finger row 15a by a conductive wire 42 made of, for example, Au or Cu. So that they are electrically connected.
　なお、チップ搭載面１０ａのボンドフィンガー列１５ａは、積層された半導体チップ２０のI/O系パッド列２１が延びる方向に平行な配線基板１０の２つの長辺に沿って、この長辺付近にそれぞれ配置されている。また、ボンドフィンガー列１５ａは、配線基板１０の第１の端部１１側に寄せて配置されている。 Note that the bond finger row 15a of the chip mounting surface 10a is in the vicinity of this long side along two long sides of the wiring substrate 10 parallel to the direction in which the I / O pad row 21 of the stacked semiconductor chips 20 extends. Each is arranged. Further, the bond finger row 15 a is arranged close to the first end portion 11 side of the wiring substrate 10.
　半導体チップ２０のCA系接続パッド列２４ａおよび２４ｂに含まれる各パッドは、ボンドフィンガー列１５ｂに含まれるボンドフィンガーと、ワイヤ４２により個別に結線されることで、電気的に接続されている。 Each pad included in the CA connection pad rows 24a and 24b of the semiconductor chip 20 is electrically connected to the bond finger included in the bond finger row 15b by being individually connected by the wire 42.
　なお、チップ搭載面１０ａのボンドフィンガー列１５ｂは、積層された半導体チップ２０のI/O系パッド列２１が延びる方向に平行な配線基板１０の２つの長辺に沿って、この長辺付近にそれぞれ配置されている。また、ボンドフィンガー列１５ｂは、配線基板１０の第２の端部１２側に寄せて配置されている。 The bond finger row 15b of the chip mounting surface 10a is in the vicinity of the long side along two long sides of the wiring substrate 10 parallel to the direction in which the I / O pad row 21 of the stacked semiconductor chips 20 extends. Each is arranged. Further, the bond finger row 15 b is arranged close to the second end portion 12 side of the wiring substrate 10.
　半導体チップ３０は、CA系パッド列に含まれるパッドとCA系接続パッド列に含まれるパッドとの再配線層による接続関係以外は、半導体チップ２０と同一構成となる（図７Ａ、図７Ｂ参照）。 The semiconductor chip 30 has the same configuration as the semiconductor chip 20 except for the connection relationship between the pads included in the CA system pad row and the pads included in the CA system connection pad row by the redistribution layer (see FIGS. 7A and 7B). .
　半導体チップ３０は、図６Ｂ、図７Ｂに示すように、ほぼ矩形の板状に形成されている。半導体チップ３０の一方の面であるパッド形成面３０ａに、例えばメモリ回路と複数の電極パッドとが形成されている。 The semiconductor chip 30 is formed in a substantially rectangular plate shape as shown in FIGS. 6B and 7B. For example, a memory circuit and a plurality of electrode pads are formed on a pad forming surface 30 a that is one surface of the semiconductor chip 30.
　パッド形成面３０ａは、互いに対向する長辺３５ａ、３５ｂにて区画された一面である。長辺３５ａは第１の辺の一例である。長辺３５ｂは第２の辺の一例である。 The pad forming surface 30a is a surface partitioned by long sides 35a and 35b facing each other. The long side 35a is an example of a first side. The long side 35b is an example of a second side.
　パッド形成面３０ａには、I/O系パッド列３１と、CA系パッド列３２と、I/O系接続パッド列３３ａおよび３３ｂと、CA系接続パッド列３４ａおよび３４ｂと、再配線層２８と、絶縁層２９ａおよび２９ｂが形成されている。 The pad forming surface 30a includes an I / O pad row 31, a CA pad row 32, I / O connection pad rows 33a and 33b, CA connection pad rows 34a and 34b, and a rewiring layer 28. Insulating layers 29a and 29b are formed.
　図７Ａ、７Ｂに示したように、半導体チップ３０におけるI/O系パッド列３１、CA系パッド列３２、I/O系接続パッド列３３ａおよび３３ｂ、CA系接続パッド列３４ａおよび３４ｂは、それぞれ、半導体チップ２０におけるI/O系パッド列２１、CA系パッド列２２、I/O系接続パッド列２３ａおよび２３ｂ、CA系接続パッド列２４ａおよび２４ｂと対応する。 As shown in FIGS. 7A and 7B, the I / O pad row 31, the CA pad row 32, the I / O connection pad rows 33a and 33b, and the CA connection pad rows 34a and 34b in the semiconductor chip 30 are respectively This corresponds to the I / O pad row 21, the CA pad row 22, the I / O connection pad rows 23a and 23b, and the CA connection pad rows 24a and 24b in the semiconductor chip 20.
　半導体チップ３０では、半導体チップ２０のCA系接続パッド列２４ａ内のパッド（例えば、CA1に対応するパッド２４ａａ）と接続されているCA系パッド列２２内のパッド（CA1に対応するパッド２２ａ）に対応する、CA系パッド列３２内のパッド（CA1に対応するパッド３２ａ）は、CA系接続パッド列３４ｂ内のパッド（CA1に対応するパッド３４ｂｂ）と接続されている。 In the semiconductor chip 30, the pads in the CA pad row 22 (pads 22a corresponding to CA1) connected to the pads in the CA connection pad row 24a of the semiconductor chip 20 (for example, the pads 24aa corresponding to CA1). The corresponding pad in the CA system pad row 32 (pad 32a corresponding to CA1) is connected to the pad in the CA system connection pad row 34b (pad 34bb corresponding to CA1).
　また、半導体チップ３０では、半導体チップ２０のCA系接続パッド列２４ｂ内のパッド（例えば、CA0に対応するパッド２４ｂｂ）と接続されているCA系パッド列２２内のパッド（CA0に対応するパッド２２ｂ）に対応する、CA系パッド列３２内のパッド（CA0に対応するパッド３２ｂ）は、CA系接続パッド列３４ａ内のパッド（CA0に対応するパッド３４ａａ）と接続されている。 In the semiconductor chip 30, the pads in the CA system pad row 22 connected to the pads in the CA system connection pad row 24b (for example, the pad 24bb corresponding to CA0) of the semiconductor chip 20 (pads 22b corresponding to CA0). ) Corresponding to the pad in the CA system pad row 32 (pad 32b corresponding to CA0) is connected to the pad in the CA system connection pad row 34a (pad 34aa corresponding to CA0).
　なお、半導体チップ３０においてCA1に対応するパッド３２ａは、第１の電極の一例である。パッド３２ａと接続されているパッド３５ｂｂは、第４の電極の一例である。また、半導体チップ３０においてCA0に対応するパッド３２ｂは、第２の電極の一例である。パッド３２ｂと接続されているパッド３４ａａは第３の電極の一例である。 Note that the pad 32a corresponding to CA1 in the semiconductor chip 30 is an example of the first electrode. The pad 35bb connected to the pad 32a is an example of a fourth electrode. The pad 32b corresponding to CA0 in the semiconductor chip 30 is an example of a second electrode. The pad 34aa connected to the pad 32b is an example of a third electrode.
　このように、半導体チップ２０と３０では、CA系パッド列内の各パッドにおいて、再配線層２８によって引き出される方向が反対の方向になっている。 Thus, in the semiconductor chips 20 and 30, the direction drawn by the rewiring layer 28 is opposite in each pad in the CA-based pad row.
　半導体チップ３０は、図６Ｂに示すように、半導体チップ３０の第１の端部３６が配線基板１０の第２の端部１２側に位置するように、フェイスアップで半導体チップ２０上に配置されている。すなわち、半導体チップ３０は、第１の端部３６側に配置されたI/O系接続パッド列３３ａおよび３３ｂが、配線基板１０の第２の端部１２側に配置された半導体チップ３０用のI/O用ランド１３ｃと隣接するように、配置されている。 6B, the semiconductor chip 30 is disposed on the semiconductor chip 20 face up so that the first end 36 of the semiconductor chip 30 is located on the second end 12 side of the wiring substrate 10. As shown in FIG. ing. That is, the semiconductor chip 30 has the I / O connection pad rows 33a and 33b arranged on the first end portion 36 side for the semiconductor chip 30 arranged on the second end portion 12 side of the wiring board 10. It is arranged so as to be adjacent to the I / O land 13c.
　半導体チップ２０と半導体チップ３０の間には、接着部材であるFOW４１ｂが配置されている。半導体チップ２０と配線基板１０とを電気的に接続するワイヤ４２の一部は、FOW４１ｂに埋め込まれている。 Between the semiconductor chip 20 and the semiconductor chip 30, an FOW 41b that is an adhesive member is disposed. A part of the wire 42 that electrically connects the semiconductor chip 20 and the wiring substrate 10 is embedded in the FOW 41b.
　半導体チップ３０のI/O系接続パッド列３３ａ、３３ｂに含まれる各パッドは、ボンドフィンガー列１５ｃに含まれるボンドフィンガーと、ワイヤ４２により個別に結線されることで、電気的に接続されている。 Each pad included in the I / O system connection pad row 33a, 33b of the semiconductor chip 30 is electrically connected to the bond finger included in the bond finger row 15c by being individually connected by the wire 42. .
　なお、ボンドフィンガー列１５ｃは、ボンドフィンガー列１５ｂと並置するように、チップ搭載面１０ａに形成されている。 The bond finger row 15c is formed on the chip mounting surface 10a so as to be juxtaposed with the bond finger row 15b.
　半導体チップ３０のCA系接続パッド列３４ａ、３４ｂに含まれる各パッドは、ボンドフィンガー列１５ｄに含まれるボンドフィンガーと、ワイヤ４２により個別に結線されることで、電気的に接続されている。 Each pad included in the CA connection pad row 34a, 34b of the semiconductor chip 30 is electrically connected to the bond finger included in the bond finger row 15d by being individually connected by the wire 42.
　なお、ボンドフィンガー列１５ｄは、ボンドフィンガー列１５ａ、１５ｂと並置するように、チップ搭載面１０ａに形成されている。 The bond finger row 15d is formed on the chip mounting surface 10a so as to be juxtaposed with the bond finger rows 15a and 15b.
　図８は、半導体チップ２０用のボンドフィンガー列１５ｂ内のCA0用ボンドフィンガー１５ｂ０とCA0用ランド１３ｂ０との接続と、ボンドフィンガー列１５ｄ内のCA0用ボンドフィンガー１５ｄ０とCA0用ランド１３ｂ０との接続と、を説明するための図である。 FIG. 8 shows the connection between the CA0 bond finger 15b0 and the CA0 land 13b0 in the bond finger row 15b for the semiconductor chip 20, and the connection between the CA0 bond finger 15d0 and the CA0 land 13b0 in the bond finger row 15d. It is a figure for demonstrating.
　図３に示した接続関係と比較すると、図８に示した半導体装置１では、CA0用ボンドフィンガー１５ｂ０とCA0用ランド１３ｂ０との配線と、CA0用ボンドフィンガー１５ｄ０とCA0用ランド１３ｂ０との配線と、の長さの差が小さくなっている。 Compared with the connection relationship shown in FIG. 3, in the semiconductor device 1 shown in FIG. 8, the wiring between the CA0 bond finger 15b0 and the CA0 land 13b0, and the wiring between the CA0 bond finger 15d0 and the CA0 land 13b0 The difference in length is small.
　なお、図４に示すように、配線基板１０のチップ搭載面１０ａには、例えばエポキシ樹脂等の熱硬化性樹脂からなる封止体４３が形成されている。半導体チップ２０および３０やワイヤ４２は、封止体４３によって覆われ、外界から保護されている。 As shown in FIG. 4, a sealing body 43 made of a thermosetting resin such as an epoxy resin is formed on the chip mounting surface 10 a of the wiring substrate 10. The semiconductor chips 20 and 30 and the wire 42 are covered with a sealing body 43 and protected from the outside.
　このように、本実施形態による半導体装置１は、基板１０と、基板１０上に搭載された第１の半導体チップ２０と、第１の半導体チップ２０上に積層された第２の半導体チップ３０と、を有する。 As described above, the semiconductor device 1 according to the present embodiment includes the substrate 10, the first semiconductor chip 20 mounted on the substrate 10, and the second semiconductor chip 30 stacked on the first semiconductor chip 20. Have.
　第１と第２の半導体チップ２０、３０は、互いに対向する第１と第２の辺２５ａ、２５ｂ、３５ａ、３５ｂによって区画された一面２０ａ、３０ａと、一面２０ａ、３０ａの中央領域に第１の辺２５ａ、３５ａに平行に配置されたコマンドアドレス系の第１と第２の電極２２ａ、２２ｂ、３２ａ、３２ｂを含む電極群（２１、２２）、（３１、３２）と、第１の辺２５ａ、３５ａに沿って一面２０ａ、３０ａに配置された第３の電極２４ａａ、３４ａａと、第２の辺２５ｂ、３５ｂに沿って一面２０ａ、３０ａに配置された第４の電極２４ｂｂ、３４ｂｂと、をそれぞれ有する。 The first and second semiconductor chips 20 and 30 have first surfaces 20a and 30a defined by first and second sides 25a, 25b, 35a and 35b facing each other, and a first region in the central region of the first surfaces 20a and 30a. A group of electrodes (21, 22), (31, 32) including first and second electrodes 22a, 22b, 32a, 32b of a command address system arranged in parallel to the sides 25a, 35a of the first side; Third electrodes 24aa, 34aa disposed on one surface 20a, 30a along 25a, 35a, and fourth electrodes 24bb, 34bb disposed on one surface 20a, 30a along second sides 25b, 35b, Respectively.
　第１の半導体チップ２０は、第１の半導体チップ２０の第１の電極２２ａが第１の半導体チップ２０の第３の電極２４ａａに、第１の半導体チップ２０の第２の電極２２ｂが第１の半導体チップ２０の第４の電極２４ｂｂにそれぞれ電気的に接続するように構成されている。 In the first semiconductor chip 20, the first electrode 22a of the first semiconductor chip 20 is the third electrode 24aa of the first semiconductor chip 20, and the second electrode 22b of the first semiconductor chip 20 is the first. The semiconductor chip 20 is configured to be electrically connected to the fourth electrode 24bb.
　第２の半導体チップ３０は、第２の半導体チップ３０の第１の電極３２ａが第２の半導体チップ３０の第４の電極３４ｂｂに、第２の半導体チップ３０の第２の電極３２ｂが第２の半導体チップ３０の第３の電極３４ａａにそれぞれ電気的に接続するように構成され、第２の半導体チップ３０の第１の辺３５ａが第１の半導体チップ２０の第２の辺２５ｂ側に、第２の半導体チップ３０の第２の辺３５ｂが第１の半導体チップ２０の第１の辺２５ａ側にそれぞれ位置するように、第１の半導体チップ２０上に積層されている。 In the second semiconductor chip 30, the first electrode 32a of the second semiconductor chip 30 is the fourth electrode 34bb of the second semiconductor chip 30, and the second electrode 32b of the second semiconductor chip 30 is the second. The first side 35a of the second semiconductor chip 30 is on the second side 25b side of the first semiconductor chip 20, and is electrically connected to the third electrode 34aa of the semiconductor chip 30. The second semiconductor chip 30 is stacked on the first semiconductor chip 20 so that the second side 35b is positioned on the first side 25a side of the first semiconductor chip 20, respectively.
　このため、半導体チップ２０の第１の電極２２ａに接続された第３の電極２４ａａと、半導体チップ３０の第１の電極３２ａに接続された第４の電極３５ｂｂとを、半導体チップ２０の第１の辺２５ａ側に配置できる。また、半導体チップ２０の第２の電極２２ｂに接続された第４の電極２４ｂｂと、半導体チップ３０の第２の電極３２ｂに接続された第３の電極３４ａａとを、半導体チップ２０の第２の辺２５ｂ側に配置できる。 Therefore, the third electrode 24aa connected to the first electrode 22a of the semiconductor chip 20 and the fourth electrode 35bb connected to the first electrode 32a of the semiconductor chip 30 are replaced with the first electrode of the semiconductor chip 20. Can be arranged on the side 25a side. In addition, the fourth electrode 24bb connected to the second electrode 22b of the semiconductor chip 20 and the third electrode 34aa connected to the second electrode 32b of the semiconductor chip 30 are connected to the second electrode 22b of the semiconductor chip 20. It can be arranged on the side 25b side.
　したがって、基板上での上下の半導体チップにおける対応するコマンドアドレス系の配線長の差を低減することが可能になる。 Therefore, it becomes possible to reduce the difference in wiring length of the corresponding command address system in the upper and lower semiconductor chips on the substrate.
　よって、この配線長の差に伴う動作タイミングのずれの調整が容易になり、半導体装置１の高速化を図ることが可能になる。 Therefore, it becomes easy to adjust the shift of the operation timing due to the difference in the wiring length, and the semiconductor device 1 can be speeded up.
　また、本実施形態による半導体装置１では、第１の半導体チップ２０は、第１の半導体チップ２０の一面２０ａの裏側の面が基板１０と対向するように、基板１０上に搭載され、第２の半導体チップ３０は、第２の半導体チップ３０の一面３０ａの裏側の面が第１の半導体チップ２０と対向するように、第１の半導体チップ２０上に搭載されている。 In the semiconductor device 1 according to the present embodiment, the first semiconductor chip 20 is mounted on the substrate 10 so that the surface on the back side of the one surface 20a of the first semiconductor chip 20 faces the substrate 10. The semiconductor chip 30 is mounted on the first semiconductor chip 20 so that the back surface of the one surface 30 a of the second semiconductor chip 30 faces the first semiconductor chip 20.
　このため、第１の半導体チップ２０と第２の半導体チップ３０とをフェイスアップで積層することが可能になる。 Therefore, the first semiconductor chip 20 and the second semiconductor chip 30 can be stacked face up.
　次に、図９Ａ－９Ｆを参照して、本実施形態の半導体装置１の製造方法について説明する。 Next, with reference to FIGS. 9A-9F, a method for manufacturing the semiconductor device 1 of the present embodiment will be described.
　図９Ａ－９Ｆは、本実施形態の半導体装置１の製造方法の各工程を概略的に示す断面図である。 9A to 9F are cross-sectional views schematically showing each step of the method for manufacturing the semiconductor device 1 of the present embodiment.
　まず、図９Ａに示すように、配線母基板５０を準備する。本実施形態で用いられる配線母基板５０は、MAP（Mold Array Process）方式で処理される。配線母基板５０には、複数の製品形成部５１がマトリクス状に配置されている。 First, as shown in FIG. 9A, a wiring mother board 50 is prepared. The wiring mother board 50 used in this embodiment is processed by a MAP (Mold Array Process) method. A plurality of product forming portions 51 are arranged in a matrix on the wiring mother board 50.
　製品形成部５１は、切断分離された後で前述の配線基板１０となる領域である。各製品形成部５１間には、ダイシングライン５２が設けられている。マトリックス状に配置された製品形成部５１の周囲には、枠部（不図示）が設けられている。枠部には、配線母基板５０の搬送・位置決めを行うための位置決め孔（不図示）が所定の間隔で設けられている。 The product forming part 51 is an area to be the wiring board 10 after being cut and separated. A dicing line 52 is provided between the product forming portions 51. A frame part (not shown) is provided around the product forming part 51 arranged in a matrix. Positioning holes (not shown) for carrying and positioning the wiring mother board 50 are provided in the frame portion at predetermined intervals.
　次に、図９Ｂに示すように、配線母基板５０の各製品形成部５１に、半導体チップ２０を、DAF、例えば絶縁基材の両面に接着層を有するテープ部材、あるいはエラストマ等の接着部材４１ａを介して接着固定する。 Next, as shown in FIG. 9B, the semiconductor chip 20 is placed on each product forming portion 51 of the wiring mother board 50, and a DAF, for example, a tape member having an adhesive layer on both surfaces of an insulating substrate, or an adhesive member 41a such as an elastomer. Adhering and fixing through.
　このとき、半導体チップ２０は、半導体チップ２０のパッド形成面２０ａの裏側の面が製品形成部（配線基板）５１に対向するように、製品形成部５１上に配置される。 At this time, the semiconductor chip 20 is arranged on the product forming portion 51 so that the back surface of the pad forming surface 20a of the semiconductor chip 20 faces the product forming portion (wiring substrate) 51.
　そして、半導体チップ２０のI/O系接続パッド列２３ａおよび２３ｂ内のパッドと、配線基板１０のボンドフィンガー列１５ａ内のボンドフィンガーとを、ワイヤ４２によって結線する。また、半導体チップ２０のCA系接続パッド列２４ａおよび２４ｂ内のパッドと、配線基板１０のボンドフィンガー列１５ｂ内のボンドフィンガーとを、ワイヤ４２によって結線する。 Then, the pads in the I / O system connection pad rows 23 a and 23 b of the semiconductor chip 20 and the bond fingers in the bond finger row 15 a of the wiring substrate 10 are connected by wires 42. Further, the pads in the CA-based connection pad rows 24 a and 24 b of the semiconductor chip 20 and the bond fingers in the bond finger row 15 b of the wiring substrate 10 are connected by wires 42.
　このように、本実施形態では、半導体チップ２０のワイヤボンディングは、半導体チップ２０のパッド形成面２０ａに半導体チップ３０を搭載する前に行われる。 As described above, in this embodiment, the wire bonding of the semiconductor chip 20 is performed before the semiconductor chip 30 is mounted on the pad forming surface 20a of the semiconductor chip 20.
　次に、図９Ｃに示すように、半導体チップ２０のパッド形成面２０ａに、FOW等の接着部材４１ｂを介し半導体チップ３０を搭載し、半導体チップ２０と半導体チップ３０とを積層させる。 Next, as shown in FIG. 9C, the semiconductor chip 30 is mounted on the pad forming surface 20a of the semiconductor chip 20 via an adhesive member 41b such as FOW, and the semiconductor chip 20 and the semiconductor chip 30 are laminated.
　そして、半導体チップ２０と同様の方法で、半導体チップ３０の電極パッドと、製品形成部５１の境界付近に形成されたボンドフィンガー１５とを、ワイヤ４２によって結線する。なお、ワイヤ４２による電極パッドとボンドフィンガー１５との接続は、ワイヤループを低くするために、逆ボンディングによって行うこともできる。 Then, the electrode pads of the semiconductor chip 30 and the bond fingers 15 formed near the boundary of the product forming portion 51 are connected by the wire 42 in the same manner as the semiconductor chip 20. The connection between the electrode pad and the bond finger 15 by the wire 42 can also be performed by reverse bonding in order to lower the wire loop.
　次に、図９Ｄに示すように、配線母基板５０のチップ搭載面５０ａを一括して覆う絶縁性の樹脂からなる封止体４３を形成する。 Next, as shown in FIG. 9D, a sealing body 43 made of an insulating resin that collectively covers the chip mounting surface 50a of the wiring motherboard 50 is formed.
　この場合、まず、配線母基板５０を、例えば図示しないトランスファモールド装置の上型と下型とからなる成型金型で型閉めする。そして、図示しないゲートから上型と下型によって形成されたキャビティ内に、熱硬化性のエポキシ樹脂を圧入し、キャビティ内を樹脂で充填した後で熱硬化させることで封止体４３が形成される。 In this case, first, the wiring mother board 50 is closed with a molding die including an upper mold and a lower mold (not shown), for example. Then, a sealing body 43 is formed by press-fitting a thermosetting epoxy resin into a cavity formed by an upper mold and a lower mold from a gate (not shown), filling the cavity with resin, and then thermosetting the resin. The
　次に、図９Ｅに示すように、配線母基板５０の電極形成面５０ｂに格子状に配置された複数のランド１３上に、半田等からなる導電性の半田ボール１７を搭載する。このボールマウント工程では、配線母基板５０上のランド１３の配置に合わせて複数の吸着孔が形成されたボールマウントツール（不図示）を使用する。半田ボール１７を吸着孔に保持し、保持された半田ボール１７にフラックスを転写形成した後で、配線母基板５０のランド１３に一括搭載する。半田ボール１７を搭載した後、所定の温度でリフローすることで、半田ボール１７を配線母基板５０に固着させる。こうして、すべてのランド１３への半田ボール１７の搭載が完了した配線母基板５０は、基板ダイシング工程へと送られる。 Next, as shown in FIG. 9E, conductive solder balls 17 made of solder or the like are mounted on the plurality of lands 13 arranged in a grid pattern on the electrode formation surface 50b of the wiring mother board 50. In this ball mounting process, a ball mounting tool (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 13 on the wiring motherboard 50 is used. The solder balls 17 are held in the suction holes, and the flux is transferred and formed on the held solder balls 17 and then mounted on the lands 13 of the wiring mother board 50 in a lump. After mounting the solder balls 17, the solder balls 17 are fixed to the wiring mother board 50 by reflowing at a predetermined temperature. Thus, the wiring mother board 50 in which the mounting of the solder balls 17 on all the lands 13 is completed is sent to the board dicing process.
　次に、図９Ｆに示すように、配線母基板５０を、ダイシングライン５２に沿って切断し、製品形成部５１ごとに分離する。この基板ダイシング工程では、まず、配線母基板５０の封止体４３をダイシングテープ（不図示）に接着することで、ダイシングテープによって配線母基板５０を支持する。そして、ダイシングブレード（不図示）によって、配線母基板５０をダイシングライン５２に沿って縦横に切断して、配線母基板５０を個片化する。個片化完了後、ダイシングテープからピックアップすることで、図４に示すようなDDP型の半導体装置を得ることができる。 Next, as shown in FIG. 9F, the wiring mother board 50 is cut along the dicing lines 52 and separated into the product forming portions 51. In this substrate dicing process, first, the wiring mother substrate 50 is supported by the dicing tape by bonding the sealing body 43 of the wiring mother substrate 50 to a dicing tape (not shown). Then, the wiring mother board 50 is cut vertically and horizontally along the dicing line 52 by a dicing blade (not shown), and the wiring mother board 50 is separated into pieces. After completion of the singulation, a DDP type semiconductor device as shown in FIG. 4 can be obtained by picking up from the dicing tape.
　（第２の実施形態）
　図１０Ａ、１０Ｂは、本発明の第２実施形態の半導体装置１Ａに用いられる半導体チップ２０Ｘおよび３０Ｘを示した図である。図１０Ａ、１０Ｂにおいて、図７Ａ、７Ｂに示したものと同一構成のものには同一符号を付してある。 (Second Embodiment)
10A and 10B are diagrams showing semiconductor chips 20X and 30X used in the semiconductor device 1A according to the second embodiment of the present invention. 10A and 10B, the same components as those shown in FIGS. 7A and 7B are denoted by the same reference numerals.
　図１１Ａ、１１Ｂは、半導体装置１Ａを概略的に示す平面図である。図１１Ａ、１１Ｂは、複数のボンドフィンガー１５が形成されたチップ搭載面１０ａ側を示している。図１１Ａは、下側の半導体チップ２０Ｘとボンドフィンガー列１５ａ、１５ｂとの接続関係も示す。図１１Ｂは、上側の半導体チップ３０Ｘとボンドフィンガー列１５ｃ、１５ｄとの接続関係も示す。図１１Ａ、１１Ｂにおいて、図６Ａ、６Ｂに示したものと同一構成のものには同一符号を付してある。 11A and 11B are plan views schematically showing the semiconductor device 1A. 11A and 11B show the chip mounting surface 10a side on which a plurality of bond fingers 15 are formed. FIG. 11A also shows the connection relationship between the lower semiconductor chip 20X and the bond finger rows 15a and 15b. FIG. 11B also shows the connection relationship between the upper semiconductor chip 30X and the bond finger rows 15c and 15d. 11A and 11B, the same components as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.
　なお、図１０Ａ、１０Ｂ、１１Ａ、１１Ｂでは、再配線層２８上の絶縁層は省略されている。 In FIGS. 10A, 10B, 11A, and 11B, the insulating layer on the rewiring layer 28 is omitted.
　第１実施形態の半導体装置１では、半導体チップ２０および３０のCA系パッド列内の対応するパッド（例えば、CA0に対応するパッド）の再配線層の引き出し方向を、半導体チップ２０と半導体チップ３０とで反対方向とした。 In the semiconductor device 1 according to the first embodiment, the lead direction of the rewiring layer of the corresponding pad (for example, the pad corresponding to CA0) in the CA-based pad row of the semiconductor chips 20 and 30 is set to the semiconductor chip 20 and the semiconductor chip 30. And in the opposite direction.
　これに対して、第２実施形態の半導体装置１Ａでは、半導体チップ２０Ｘおよび３０ＸにおいてCA系パッド列内の対応するパッドの再配線層の引き出し方向に加えて、I/O系パッド列内の対応するパッド（例えば、DQSに対応するパッド）の再配線層の引き出し方向も、半導体チップ２０Ｘと半導体チップ３０Ｘとで反対方向としている。 On the other hand, in the semiconductor device 1A of the second embodiment, in the semiconductor chips 20X and 30X, in addition to the drawing direction of the rewiring layer of the corresponding pad in the CA pad row, the correspondence in the I / O pad row The drawing direction of the rewiring layer of the pads to be performed (for example, pads corresponding to DQS) is also opposite in the semiconductor chip 20X and the semiconductor chip 30X.
　以下、第２実施形態の半導体装置１Ａについて、第１実施形態の半導体装置１と異なる点を中心に説明する。 Hereinafter, the semiconductor device 1A of the second embodiment will be described focusing on differences from the semiconductor device 1 of the first embodiment.
　図１０Ａ、図１１Ａにおいて、半導体チップ２０Ｘは、図７Ａに示した半導体チップ２０と同一構成である。 10A and 11A, the semiconductor chip 20X has the same configuration as the semiconductor chip 20 shown in FIG. 7A.
　図１０Ｂ、図１１Ｂにおいて、半導体チップ３０Ｘでは、半導体チップ２０ＸのI/O系接続パッド列２３ａ内のパッド（例えば、ＤＱＳに対応するパッド；第７の電極）と接続されているI/O系パッド列２１内のパッド（ＤＱＳに対応するパッド；第５の電極）に対応する、I/O系パッド列３１内のパッド（ＤＱＳに対応するパッド；第５の電極）は、半導体チップ３０ＸのI/O系接続パッド列３３ｂ内のパッド（ＤＱＳに対応するパッド；第８の電極）と接続されている。 10B and 11B, in the semiconductor chip 30X, an I / O system connected to a pad (for example, a pad corresponding to DQS; a seventh electrode) in the I / O system connection pad row 23a of the semiconductor chip 20X. The pad (pad corresponding to DQS; fifth electrode) in the I / O-based pad row 31 corresponding to the pad (pad corresponding to DQS; fifth electrode) in the pad row 21 is formed on the semiconductor chip 30X. It is connected to a pad (pad corresponding to DQS; eighth electrode) in the I / O system connection pad row 33b.
　また、半導体チップ３０Ｘでは、半導体チップ２０ＸのI/O系接続パッド列２３ｂ内のパッド（例えば、ＤＱＳＢに対応するパッド；第８の電極）と接続されているI/O系パッド列２１内のパッド（ＤＱＳＢに対応するパッド；第６の電極）に対応する、I/O系パッド列３１内のパッド（ＤＱＳＢに対応するパッド；第６の電極）は、半導体チップ３０ＸのI/O系接続パッド列３３ａ内のパッド（ＤＱＳＢに対応するパッド；第７の電極）と接続されている。 In the semiconductor chip 30X, the I / O system pad row 21b connected to the pads (for example, the pad corresponding to DQSB; the eighth electrode) in the I / O system connection pad row 23b of the semiconductor chip 20X. The pad (pad corresponding to DQSB; sixth electrode) in the I / O system pad row 31 corresponding to the pad (pad corresponding to DQSB; sixth electrode) is connected to the I / O system of the semiconductor chip 30X. It is connected to a pad (pad corresponding to DQSB; seventh electrode) in the pad row 33a.
　第５の電極、第６の電極は、例えば、DQS、DQSB、DM（TDQS）、TDQSBに対応するパッドである。 The fifth electrode and the sixth electrode are pads corresponding to, for example, DQS, DQSB, DM (TDQS), and TDQSB.
　このように本実施形態では、電極群は、さらにI/O系パッド列２１、３１内の第５の電極、第６の電極を含む。第１、第２の半導体チップ２０Ｘ、３０Ｘは、さらに、第１の辺２５ａ、３５ａに沿ってパッド形成面２０ａ、３０ａに配置されたI/O系接続パッド列２３ａ、３３ａ内のパッド（第７の電極）と、第２の辺２５ｂ、３５ｂに沿ってパッド形成面２０ａ、３０ａに配置されたI/O系接続パッド列２３ｂ、３３ｂ内のパッド（第８の電極）と、をそれぞれ有する。 As described above, in this embodiment, the electrode group further includes the fifth electrode and the sixth electrode in the I / O-based pad rows 21 and 31. The first and second semiconductor chips 20X and 30X are further provided with pads (first pads) in the I / O connection pad rows 23a and 33a arranged on the pad forming surfaces 20a and 30a along the first sides 25a and 35a. 7) and pads (eighth electrodes) in the I / O connection pad rows 23b and 33b arranged on the pad forming surfaces 20a and 30a along the second sides 25b and 35b, respectively. .
　第１の半導体チップ２０Ｘは、第１の半導体チップ２０Ｘの第５の電極が第１の半導体チップ２０Ｘの第７の電極に、第１の半導体チップ２０Ｘの第６の電極が第１の半導体チップ２０Ｘの第８の電極にそれぞれ電気的に接続するように構成されている。 In the first semiconductor chip 20X, the fifth electrode of the first semiconductor chip 20X is the seventh electrode of the first semiconductor chip 20X, and the sixth electrode of the first semiconductor chip 20X is the first semiconductor chip. Each of the 20X eighth electrodes is electrically connected.
　第２の半導体チップ３０Ｘは、第２の半導体チップ３０Ｘの第５の電極が第２の半導体チップ３０Ｘの第８の電極に、第２の半導体チップ３０Ｘの第６の電極が第２の半導体チップ３０Ｘの第７の電極にそれぞれ電気的に接続するように構成されている。 In the second semiconductor chip 30X, the fifth electrode of the second semiconductor chip 30X is the eighth electrode of the second semiconductor chip 30X, and the sixth electrode of the second semiconductor chip 30X is the second semiconductor chip. It is configured to be electrically connected to each of the 30X seventh electrodes.
　このため、I/O系のチップパッドの割付の変更で対応できないチップパッド、例えば、DQS、DQSB、DM（TDQS）、TDQSBを配線基板１０の同じ側の配置できる。そのため、半導体装置の更なる高速化を図ることが可能になる。 For this reason, chip pads, such as DQS, DQSB, DM (TDQS), and TDQSB that cannot be handled by changing the allocation of I / O chip pads, can be arranged on the same side of the wiring board 10. Therefore, it is possible to further increase the speed of the semiconductor device.
　（第３実施形態）
　図１２Ａ、１２Ｂは、本発明の第３実施形態の半導体装置１Ｂに用いられる半導体チップ２０Ｙおよび３０Ｙを示した図である。図１２Ａ、１２Ｂにおいて、図７Ａ、７Ｂに示したものと同一構成のものには同一符号を付してある。 (Third embodiment)
12A and 12B are diagrams showing semiconductor chips 20Y and 30Y used in the semiconductor device 1B according to the third embodiment of the present invention. 12A and 12B, the same components as those shown in FIGS. 7A and 7B are denoted by the same reference numerals.
　図１３Ａ、１３Ｂは、半導体装置１Ｂを概略的に示す平面図である。図１３Ａ、１３Ｂは、複数のボンドフィンガー１５が形成されたチップ搭載面側を示している。図１３Ａは、下側の半導体チップ２０Ｙとボンドフィンガー列１５ａ、１５ｂとの接続関係も示す。図１３Ｂは、上側の半導体チップ３０Ｙとボンドフィンガー列１５ｃ、１５ｄとの接続関係も示す。図１３Ａ、１３Ｂにおいて、図６Ａ、６Ｂに示したものと同一構成のものには同一符号を付してある。 13A and 13B are plan views schematically showing the semiconductor device 1B. 13A and 13B show the chip mounting surface side on which a plurality of bond fingers 15 are formed. FIG. 13A also shows the connection relationship between the lower semiconductor chip 20Y and the bond finger rows 15a and 15b. FIG. 13B also shows the connection relationship between the upper semiconductor chip 30Y and the bond finger rows 15c and 15d. 13A and 13B, the same components as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.
　なお、図１２Ａ、１２Ｂ、１３Ａ、１３Ｂでは、再配線層２８上の絶縁層は省略されている。 In FIGS. 12A, 12B, 13A, and 13B, the insulating layer on the rewiring layer 28 is omitted.
　半導体チップ２０Ｙおよび３０Ｙは同一構成である。 The semiconductor chips 20Y and 30Y have the same configuration.
　半導体チップ２０Ｙおよび３０Ｙには、図１４に示すような切替回路６０が形成されている。 In the semiconductor chips 20Y and 30Y, a switching circuit 60 as shown in FIG. 14 is formed.
　図１４において、切替回路６０は、設定回路の一例である。切替回路６０は、受付部６１および６２と、セレクタ６３および６４と、を含む。 In FIG. 14, the switching circuit 60 is an example of a setting circuit. Switching circuit 60 includes receiving units 61 and 62 and selectors 63 and 64.
　まず、半導体チップ２０Ｙの切替回路６０について説明する。 First, the switching circuit 60 of the semiconductor chip 20Y will be described.
　切替回路６０は、CA系パッド列２２内のパッドの数の半分の数設けられている。切替回路６０は、CA系接続パッド列２４ａ内のパッド（第３の電極）と接続するCA系パッド列２２内の１つのパッド（第１の電極）と、CA系接続パッド列２４ｂ内のパッド（第４の電極）と接続するCA系パッド列２２内の１つのパッド（第２の電極）と、の組み合わせに対して１つ設けられている。 The number of switching circuits 60 is half that of the pads in the CA pad row 22. The switching circuit 60 includes one pad (first electrode) in the CA system pad row 22 connected to the pad (third electrode) in the CA system connection pad row 24a, and a pad in the CA system connection pad row 24b. One is provided for the combination of one pad (second electrode) in the CA-based pad row 22 connected to (fourth electrode).
　本実施形態では、CA系パッド列２２内のパッドを、パッドの配列方向に並ぶ２つのパッド単位に分け、その２つのパッドの１組に対して、切替回路６０が１つずつ設けられている。 In the present embodiment, the pads in the CA-based pad row 22 are divided into two pad units arranged in the pad arrangement direction, and one switching circuit 60 is provided for one set of the two pads. .
　半導体チップ２０Ｙでは、受付部６１は、CA系接続パッド列２４ａ内のパッド（第３の電極）と接続するCA系パッド列２２内の１つのパッド（第１の電極）から信号を受け付ける。また、受付部６２は、CA系接続パッド列２４ｂ内のパッド（第４の電極）と接続するCA系パッド列２２内の１つのパッド（第２の電極）から信号を受け付ける。 In the semiconductor chip 20Y, the accepting unit 61 accepts a signal from one pad (first electrode) in the CA system pad row 22 connected to the pad (third electrode) in the CA system connection pad row 24a. The receiving unit 62 receives a signal from one pad (second electrode) in the CA pad array 22 connected to the pad (fourth electrode) in the CA connection pad array 24b.
　受付部６１は、信号を受け付けると、その信号をセレクタ６３および６４に出力する。また、受付部６２は、信号を受け付けると、その信号をセレクタ６３および６４に出力する。 When the reception unit 61 receives the signal, the reception unit 61 outputs the signal to the selectors 63 and 64. In addition, when receiving the signal, receiving unit 62 outputs the signal to selectors 63 and 64.
　セレクタ６３の出力は、半導体チップ２０Ｙ内に信号を入力するための入力部８１に接続されている。セレクタ６４の出力は、半導体チップ２０Ｙ内に信号を入力するための入力部８２に接続されている。 The output of the selector 63 is connected to an input unit 81 for inputting a signal into the semiconductor chip 20Y. The output of the selector 64 is connected to an input unit 82 for inputting a signal into the semiconductor chip 20Y.
　セレクタ６３および６４は、例えばヒューズ回路（不図示）内のヒューズが切断されているか否かによって信号レベルが“０”と“１”の間で切り替わるＭＦ信号も受け付ける。 The selectors 63 and 64 also accept an MF signal whose signal level switches between “0” and “1” depending on, for example, whether or not a fuse in a fuse circuit (not shown) is cut.
　ＭＦ信号が“０”であるとき、セレクタ６３は、受付部６１からの信号を入力部８１に出力し、セレクタ６４は、受付部６２からの信号を入力部８２に出力する。 When the MF signal is “0”, the selector 63 outputs a signal from the receiving unit 61 to the input unit 81, and the selector 64 outputs a signal from the receiving unit 62 to the input unit 82.
　また、ＭＦ信号が“１”であるとき、セレクタ６３は、受付部６２からの信号を入力部８１に出力し、セレクタ６４は、受付部６１からの信号を入力部８２に出力する。 Further, when the MF signal is “1”, the selector 63 outputs a signal from the receiving unit 62 to the input unit 81, and the selector 64 outputs a signal from the receiving unit 61 to the input unit 82.
　次に、半導体チップ３０Ｙの切替回路６０について説明する。 Next, the switching circuit 60 of the semiconductor chip 30Y will be described.
　切替回路６０は、CA系パッド列２２内のパッドの数の半分の数設けられている。切替回路６０は、CA系接続パッド列３４ａ内のパッド（第３の電極）と接続するCA系パッド列３２内の１つのパッド（第１の電極）と、CA系接続パッド列３４ｂ内のパッド（第４の電極）と接続するCA系パッド列３２内の１つのパッド（第２の電極）と、の組み合わせに対して１つ設けられている。 The number of switching circuits 60 is half that of the pads in the CA pad row 22. The switching circuit 60 includes one pad (first electrode) in the CA system pad row 32 connected to the pad (third electrode) in the CA system connection pad row 34a, and a pad in the CA system connection pad row 34b. One is provided for a combination of one pad (second electrode) in the CA-based pad row 32 connected to (fourth electrode).
　本実施形態では、CA系パッド列３２内のパッドを、パッドの配列方向に並ぶ２つのパッド単位に分け、その２つのパッドの１組に対して、切替回路６０が１つずつ設けられている。 In the present embodiment, the pads in the CA-based pad row 32 are divided into two pad units arranged in the pad arrangement direction, and one switching circuit 60 is provided for one set of the two pads. .
　半導体チップ３０Ｙでは、受付部６１は、CA系接続パッド列３４ａ内のパッド（第３の電極）と接続するCA系パッド列３２内のパッド（第１の電極）から信号を受け付ける。また、受付部６２は、CA系接続パッド列３４ｂ内のパッド（第４の電極）と接続するCA系パッド列３２内のパッド（第２の電極）から信号を受け付ける。 In the semiconductor chip 30Y, the accepting unit 61 accepts a signal from the pad (first electrode) in the CA system pad row 32 connected to the pad (third electrode) in the CA system connection pad row 34a. The receiving unit 62 receives a signal from the pad (second electrode) in the CA system pad row 32 connected to the pad (fourth electrode) in the CA system connection pad row 34b.
　セレクタ６３の出力は、半導体チップ３０Ｙ内に信号を入力するための入力部に接続されている。セレクタ６４の出力は、半導体チップ３０Ｙ内に信号を入力するための入力部に接続されている。 The output of the selector 63 is connected to an input unit for inputting a signal into the semiconductor chip 30Y. The output of the selector 64 is connected to an input unit for inputting a signal into the semiconductor chip 30Y.
　なお、ＭＦ信号の値に応じた半導体チップ３０Ｙ内のセレクタ６３、６４の動作は、半導体チップ２０Ｙの動作に準じるので説明を割愛する。 Note that the operation of the selectors 63 and 64 in the semiconductor chip 30Y according to the value of the MF signal conforms to the operation of the semiconductor chip 20Y, and thus the description thereof is omitted.
　このように、本実施形態による半導体装置１Ｂは、基板１０と、基板１０上に搭載された第１の半導体チップ２０Ｙと、第１の半導体チップ２０Ｙ上に積層された第２の半導体チップ３０Ｙと、を有する。 As described above, the semiconductor device 1B according to the present embodiment includes the substrate 10, the first semiconductor chip 20Y mounted on the substrate 10, and the second semiconductor chip 30Y stacked on the first semiconductor chip 20Y. Have.
　第１と第２の半導体チップ２０Ｙ、３０Ｙは、互いに対向する第１と第２の辺２５ａ、２５ｂ、３５ａ、３５ｂによって区画された一面２０ａ、３０ａと、一面２０ａ、３０ａの中央領域に第１の辺２５ａ、３５ａに平行に配置されたコマンドアドレス系の第１と第２の電極２２ａ、２２ｂ、３２ａ、３２ｂを含む電極群（２１、２２）、（３１、３２）と、第１の辺２５ａ、３５ａに沿って一面２０ａ、３０ａに配置された第３の電極２４ａａ、３４ａａと、第２の辺２５ｂ、３５ｂに沿って一面２０ａ、３０ａに配置された第４の電極２４ｂｂ、３５ｂｂと、第１と第２の入力部８１、８２と、第１の電極を第１の入力部８１に接続すると共に第２の電極を第２の入力部８２に接続する第１接続状態と、第１の電極を第２の入力部８２に接続すると共に第２の電極を第１の入力部８１に接続する第２接続状態と、を択一的に設定する切替回路６０と、をそれぞれ有する。 The first and second semiconductor chips 20Y and 30Y have first surfaces 20a and 30a defined by first and second sides 25a, 25b, 35a and 35b facing each other, and a first region in the central region of the first surfaces 20a and 30a. A group of electrodes (21, 22), (31, 32) including first and second electrodes 22a, 22b, 32a, 32b of a command address system arranged in parallel to the sides 25a, 35a of the first side; Third electrodes 24aa, 34aa disposed on one surface 20a, 30a along 25a, 35a, and fourth electrodes 24bb, 35bb disposed on one surface 20a, 30a along second sides 25b, 35b, A first connection state in which the first and second input sections 81 and 82 are connected to the first input section 81 and the second electrode is connected to the second input section 82; The electrodes of the second input section 82 It has a second connection state of connecting the second electrode to the first input portion 81 as well as connection and switching circuit 60 to set alternatively to, respectively.
　第１の半導体チップ２０Ｙは、第１の半導体チップ２０Ｙの第１の電極２２ａが第１の半導体チップ２０Ｙの第３の電極２４ａａに、第１の半導体チップ２０Ｙの第２の電極２２ｂが第１の半導体チップ２０Ｙの第４の電極２４ｂｂにそれぞれ電気的に接続するように構成されている。 In the first semiconductor chip 20Y, the first electrode 22a of the first semiconductor chip 20Y is the third electrode 24aa of the first semiconductor chip 20Y, and the second electrode 22b of the first semiconductor chip 20Y is the first. The semiconductor chip 20Y is configured to be electrically connected to the fourth electrode 24bb.
　第２の半導体チップ３０Ｙは、第２の半導体チップ３０Ｙの第１の電極３２ａが第２の半導体チップ３０Ｙの第３の電極３４ａａに、第２の半導体チップ３０Ｙの第２の電極３２ｂが第２の半導体チップ３０Ｙの第４の電極３５ｂｂにそれぞれ電気的に接続するように構成され、第２の半導体チップ３０Ｙの第１の辺３５ａが第１の半導体チップ２０Ｙの第２の辺２５ｂ側に、第２の半導体チップ３０Ｙの第２の辺３５ｂが第１の半導体チップ２０Ｙの第１の辺２５ａ側にそれぞれ位置するように、第１の半導体チップ２０Ｙ上に積層されている。 In the second semiconductor chip 30Y, the first electrode 32a of the second semiconductor chip 30Y is the third electrode 34aa of the second semiconductor chip 30Y, and the second electrode 32b of the second semiconductor chip 30Y is the second. The first side 35a of the second semiconductor chip 30Y is on the second side 25b side of the first semiconductor chip 20Y, and is electrically connected to the fourth electrode 35bb of the semiconductor chip 30Y. The second semiconductor chip 30Y is stacked on the first semiconductor chip 20Y so that the second side 35b is positioned on the first side 25a side of the first semiconductor chip 20Y.
　このため、第２の半導体チップ３０Ｙと第２の半導体チップ３０Ｙにおいて、切替回路６０にて、第１接続状態と第２接続状態を適宜設定することによって、第１実施形態と同様に、基板上での上下の半導体チップにおける対応するコマンドアドレス系の配線長の差を低減することが可能になる。 For this reason, in the second semiconductor chip 30Y and the second semiconductor chip 30Y, the switching circuit 60 appropriately sets the first connection state and the second connection state, so that the substrate is mounted on the substrate as in the first embodiment. Thus, it is possible to reduce the difference in wiring length of the corresponding command address system in the upper and lower semiconductor chips.
　よって、この配線長の差に伴う動作タイミングのずれの調整が容易になり、半導体装置１の高速化を図ることが可能になる。 Therefore, it becomes easy to adjust the shift of the operation timing due to the difference in the wiring length, and the semiconductor device 1 can be speeded up.
　また、第３実施形態では、上下の半導体チップ２０、３０に形成される再配線層は同一構成となる。このため、上下の半導体チップとして準備される半導体チップは、１種類で済み、低コスト化を図ることが可能になる。 In the third embodiment, the redistribution layers formed on the upper and lower semiconductor chips 20 and 30 have the same configuration. Therefore, only one type of semiconductor chip is prepared as the upper and lower semiconductor chips, and the cost can be reduced.
　以上、各実施形態に基づき説明したが、本発明は上記各実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, although it demonstrated based on each embodiment, it cannot be overemphasized that this invention is not limited to each said embodiment, and can be variously changed in the range which does not deviate from the summary.
　例えば、上記実施形態では、半導体チップ上に再配線層を設けることでパッドの再配線が行われたが、半導体チップ上にサブ配線基板を搭載してパッドの再配線が行われるように構成してもよい。 For example, in the above embodiment, the rewiring of the pad is performed by providing the rewiring layer on the semiconductor chip. However, the subwiring board is mounted on the semiconductor chip so that the rewiring of the pad is performed. May be.
　例えば、第１、第２実施形態において、半導体チップ２０、２０Ｘの第１の電極と半導体チップ２０、２０Ｘの第３の電極との電気的な接続、半導体チップ２０、２０Ｘの第２の電極と半導体チップ２０、２０Ｘの第４の電極との電気的な接続、半導体チップ３０、３０Ｘの第１の電極と半導体チップ３０、３０Ｘの第４の電極との電気的な接続、および、半導体チップ３０、３０Ｘの第２の電極と半導体チップ３０、３０Ｘの第３の電極との電気的な接続のうち、少なくとも１つの接続は、再配線層または配線基板を介して行われてもよい。 For example, in the first and second embodiments, the electrical connection between the first electrode of the semiconductor chips 20 and 20X and the third electrode of the semiconductor chips 20 and 20X, the second electrode of the semiconductor chips 20 and 20X, and Electrical connection between the fourth electrodes of the semiconductor chips 20 and 20X, electrical connection between the first electrodes of the semiconductor chips 30 and 30X and the fourth electrodes of the semiconductor chips 30 and 30X, and the semiconductor chip 30 , 30X, and the third electrode of the semiconductor chip 30, 30X, at least one connection may be made via a redistribution layer or a wiring substrate.
　また、第３実施形態において、半導体チップ２０Ｙの第１の電極と半導体チップ２０Ｙの第３の電極との電気的な接続、半導体チップ２０Ｙの第２の電極と半導体チップ２０Ｙの第４の電極との電気的な接続、半導体チップ３０Ｙの第１の電極と半導体チップ３０Ｙの第４の電極との電気的な接続、および、半導体チップ３０Ｙの第２の電極と半導体チップ３０Ｙの第３の電極との電気的な接続のうち、少なくとも１つの接続は、再配線層または配線基板を介して行われてもよい。 In the third embodiment, the electrical connection between the first electrode of the semiconductor chip 20Y and the third electrode of the semiconductor chip 20Y, the second electrode of the semiconductor chip 20Y, and the fourth electrode of the semiconductor chip 20Y Electrical connection between the first electrode of the semiconductor chip 30Y and the fourth electrode of the semiconductor chip 30Y, and the second electrode of the semiconductor chip 30Y and the third electrode of the semiconductor chip 30Y. Of these electrical connections, at least one of the connections may be made via a rewiring layer or a wiring board.
　また上記各実施形態では、半導体チップとして、一面の中央領域で一列で複数の電極パッドが配置された半導体チップに適用したが、一面の中央領域に２列、或いは３列以上で複数の電極パッドが配置された半導体チップが適用されてもよい。 In each of the above embodiments, the semiconductor chip is applied to a semiconductor chip in which a plurality of electrode pads are arranged in a row in a central region of one surface. However, a plurality of electrode pads in two or three or more rows in a central region of one surface. A semiconductor chip in which is arranged may be applied.
　例えば、半導体チップにおいて、電極群に含まれる電極にて、第１の辺に平行に配置された複数の電極列が形成されてもよい。 For example, in a semiconductor chip, a plurality of electrode rows arranged in parallel to the first side may be formed by electrodes included in the electrode group.
　実施形態を参照して本願発明を説明したが、本願発明は上記実施形態に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。この出願は、２０１２年１２月１８日に出願された日本出願特願２０１２－２７５６２４を基礎とする優先権を主張し、その開示の全てをここに取り込む。 Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2012-275624 for which it applied on December 18, 2012, and takes in those the indications of all here.
　　　１、１Ａ、１Ｂ　半導体装置
　　　１０　　　配線基板
　　　１０ａ　　チップ搭載面
　　　１０ｂ　　電極形成面
　　　１５ａ～１５ｄ　ボンドフィンガー列
　　　２０、２０Ｘ、２０Ｙ、３０、３０Ｘ、３０Ｙ　半導体チップ
　　　２１、３１　　　I/O系パッド列
　　　２２、３２　　　CA系パッド列
　　　２３ａ、２３ｂ、３３ａ、３３ｂ　I/O系接続パッド列
　　　２４ａ、２４ｂ、３４ａ、３４ｂ　CA系接続パッド列
　　　２８　　　再配線層
　　　４２　　　ワイヤ 1, 1A, 1B Semiconductor device 10 Wiring substrate 10a Chip mounting surface 10b Electrode forming surface 15a to 15d Bond finger row 20, 20X, 20Y, 30, 30X, 30Y Semiconductor chip 21, 31 I / O system pad row 22, 32 CA System pad row 23a, 23b, 33a, 33b I / O system connection pad row 24a, 24b, 34a, 34b CA system connection pad row 28 Redistribution layer 42 Wire

Claims (7)

  1. 　基板と、前記基板上に搭載された第１の半導体チップと、前記第１の半導体チップ上に積層された第２の半導体チップと、を有し、
    　前記第１と第２の半導体チップは、
    　互いに対向する第１と第２の辺によって区画された一面と、
    　前記一面の中央領域に前記第１の辺に平行に配置されたコマンドアドレス系の第１と第２の電極を含む電極群と、
    　前記第１の辺に沿って前記一面に配置された第３の電極と、
    　前記第２の辺に沿って前記一面に配置された第４の電極と、をそれぞれ有し、
    　前記第１の半導体チップは、前記第１の半導体チップの前記第１の電極が前記第１の半導体チップの前記第３の電極に、前記第１の半導体チップの前記第２の電極が前記第１の半導体チップの前記第４の電極にそれぞれ電気的に接続するように構成され、
    　前記第２の半導体チップは、前記第２の半導体チップの前記第１の電極が前記第２の半導体チップの前記第４の電極に、前記第２の半導体チップの前記第２の電極が前記第２の半導体チップの前記第３の電極にそれぞれ電気的に接続するように構成され、前記第２の半導体チップの前記第１の辺が前記第１の半導体チップの前記第２の辺側に、前記第２の半導体チップの前記第２の辺が前記第１の半導体チップの前記第１の辺側にそれぞれ位置するように、前記第１の半導体チップ上に積層されている、半導体装置。     A substrate, a first semiconductor chip mounted on the substrate, and a second semiconductor chip stacked on the first semiconductor chip,
    The first and second semiconductor chips are:
    A surface defined by first and second sides facing each other;
    A group of electrodes including first and second electrodes of a command address system arranged in a central region of the one surface in parallel with the first side;
    A third electrode disposed on the one surface along the first side;
    Each having a fourth electrode disposed on the one surface along the second side,
    In the first semiconductor chip, the first electrode of the first semiconductor chip is the third electrode of the first semiconductor chip, and the second electrode of the first semiconductor chip is the first electrode. Each electrically connected to the fourth electrode of one semiconductor chip,
    In the second semiconductor chip, the first electrode of the second semiconductor chip is the fourth electrode of the second semiconductor chip, and the second electrode of the second semiconductor chip is the first electrode. Each of the second semiconductor chips is electrically connected to the third electrode, and the first side of the second semiconductor chip is on the second side of the first semiconductor chip, A semiconductor device stacked on the first semiconductor chip such that the second side of the second semiconductor chip is positioned on the first side of the first semiconductor chip.
  2. 　前記電極群は、さらに、前記一面の中央領域に前記第１の辺に平行に配置されたデータ入出力用の第５と第６の電極を含み、
    　前記第１と第２の半導体チップは、さらに、
    　前記第１の辺に沿って前記一面に配置された第７の電極と、
    　前記第２の辺に沿って前記一面に配置された第８の電極と、をそれぞれ有し、
    　前記第１の半導体チップは、前記第１の半導体チップの前記第５の電極が前記第１の半導体チップの前記第７の電極に、前記第１の半導体チップの前記第６の電極が前記第１の半導体チップの前記第８の電極にそれぞれ電気的に接続するように構成され、
    　前記第２の半導体チップは、前記第２の半導体チップの前記第５の電極が前記第２の半導体チップの前記第８の電極に、前記第２の半導体チップの前記第６の電極が前記第２の半導体チップの前記第７の電極にそれぞれ電気的に接続するように構成されている、請求項１に記載の半導体装置。     The electrode group further includes fifth and sixth electrodes for data input / output arranged in the central region of the one surface in parallel with the first side,
    The first and second semiconductor chips further include:
    A seventh electrode disposed on the one surface along the first side;
    An eighth electrode disposed on the one surface along the second side,
    In the first semiconductor chip, the fifth electrode of the first semiconductor chip is the seventh electrode of the first semiconductor chip, and the sixth electrode of the first semiconductor chip is the first electrode. Each electrically connected to the eighth electrode of one semiconductor chip,
    In the second semiconductor chip, the fifth electrode of the second semiconductor chip is the eighth electrode of the second semiconductor chip, and the sixth electrode of the second semiconductor chip is the first electrode. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be electrically connected to each of the seventh electrodes of the two semiconductor chips.
  3. 　前記第１の半導体チップの前記第１の電極と前記第１の半導体チップの前記第３の電極との電気的な接続、前記第１の半導体チップの前記第２の電極と前記第１の半導体チップの前記第４の電極との電気的な接続、前記第２の半導体チップの前記第１の電極と前記第２の半導体チップの前記第４の電極との電気的な接続、および、前記第２の半導体チップの前記第２の電極が前記第２の半導体チップの前記第３の電極との電気的な接続のうち、少なくとも１つの接続は、再配線層または配線基板を介して行われる、請求項１または２に記載の半導体装置。 Electrical connection between the first electrode of the first semiconductor chip and the third electrode of the first semiconductor chip, the second electrode of the first semiconductor chip and the first semiconductor Electrical connection with the fourth electrode of the chip, electrical connection between the first electrode of the second semiconductor chip and the fourth electrode of the second semiconductor chip, and the first Of the electrical connection between the second electrode of the second semiconductor chip and the third electrode of the second semiconductor chip, at least one connection is made via a redistribution layer or a wiring substrate. The semiconductor device according to claim 1.
  4. 　基板と、前記基板上に搭載された第１の半導体チップと、前記第１の半導体チップ上に積層された第２の半導体チップと、を有し、
    　前記第１と第２の半導体チップは、
    　互いに対向する第１と第２の辺によって区画された一面と、
    　前記一面の中央領域に前記第１の辺に平行に配置されたコマンドアドレス系の第１と第２の電極を含む電極群と、
    　前記第１の辺に沿って前記一面に配置された第３の電極と、
    　前記第２の辺に沿って前記一面に配置された第４の電極と、
    　自チップ内に信号を入力するための第１と第２の入力部と、
    　前記第１の電極を前記第１の入力部に接続すると共に前記第２の電極を前記第２の入力部に接続する第１接続状態と、前記第１の電極を前記第２の入力部に接続すると共に前記第２の電極を前記第１の入力部に接続する第２接続状態と、を択一的に設定する設定回路と、をそれぞれ有し、
    　前記第１の半導体チップは、前記第１の半導体チップの前記第１の電極が前記第１の半導体チップの前記第３の電極に、前記第１の半導体チップの前記第２の電極が前記第１の半導体チップの前記第４の電極にそれぞれ電気的に接続するように構成され、
    　前記第２の半導体チップは、前記第２の半導体チップの前記第１の電極が前記第２の半導体チップの前記第３の電極に、前記第２の半導体チップの前記第２の電極が前記第２の半導体チップの前記第４の電極にそれぞれ電気的に接続するように構成され、前記第２の半導体チップの前記第１の辺が前記第１の半導体チップの前記第２の辺側に、前記第２の半導体チップの前記第２の辺が前記第１の半導体チップの前記第１の辺側にそれぞれ位置するように、前記第１の半導体チップ上に積層されている、半導体装置。     A substrate, a first semiconductor chip mounted on the substrate, and a second semiconductor chip stacked on the first semiconductor chip,
    The first and second semiconductor chips are:
    A surface defined by first and second sides facing each other;
    A group of electrodes including first and second electrodes of a command address system arranged in a central region of the one surface in parallel with the first side;
    A third electrode disposed on the one surface along the first side;
    A fourth electrode disposed on the one surface along the second side;
    First and second input units for inputting signals into the chip;
    A first connection state in which the first electrode is connected to the first input unit and the second electrode is connected to the second input unit; and the first electrode is connected to the second input unit. And a setting circuit that alternatively sets a second connection state that connects and connects the second electrode to the first input unit,
    In the first semiconductor chip, the first electrode of the first semiconductor chip is the third electrode of the first semiconductor chip, and the second electrode of the first semiconductor chip is the first electrode. Each electrically connected to the fourth electrode of one semiconductor chip,
    In the second semiconductor chip, the first electrode of the second semiconductor chip is the third electrode of the second semiconductor chip, and the second electrode of the second semiconductor chip is the first electrode. Each of the second semiconductor chips is electrically connected to the fourth electrode, and the first side of the second semiconductor chip is on the second side of the first semiconductor chip, A semiconductor device stacked on the first semiconductor chip such that the second side of the second semiconductor chip is positioned on the first side of the first semiconductor chip.
  5. 　前記第１の半導体チップの前記第１の電極と前記第１の半導体チップの前記第３の電極との電気的な接続、前記第１の半導体チップの前記第２の電極と前記第１の半導体チップの前記第４の電極との電気的な接続、前記第２の半導体チップの前記第１の電極と前記第２の半導体チップの前記第３の電極との電気的な接続、および、前記第２の半導体チップの前記第２の電極が前記第２の半導体チップの前記第４の電極との電気的な接続のうち、少なくとも１つの接続は、再配線層または配線基板を介して行われる、請求項４に記載の半導体装置。 Electrical connection between the first electrode of the first semiconductor chip and the third electrode of the first semiconductor chip, the second electrode of the first semiconductor chip and the first semiconductor Electrical connection with the fourth electrode of the chip, electrical connection between the first electrode of the second semiconductor chip and the third electrode of the second semiconductor chip, and the first Of the electrical connection between the second electrode of the second semiconductor chip and the fourth electrode of the second semiconductor chip, at least one connection is made via a redistribution layer or a wiring substrate. The semiconductor device according to claim 4.
  6. 　前記電極群に含まれる電極にて、前記第１の辺に平行に配置された複数の電極列が形成されている、請求項１から５のいずれか１項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein a plurality of electrode rows arranged in parallel to the first side are formed by electrodes included in the electrode group.
  7. 　前記第１の半導体チップは、前記第１の半導体チップの前記一面の裏側の面が前記基板と対向するように、前記基板上に搭載され、
    　前記第２の半導体チップは、前記第２の半導体チップの前記一面の裏側の面が前記第１の半導体チップと対向するように、前記第１の半導体チップ上に搭載されている、請求項１から６のいずれか１項に記載の半導体装置。     The first semiconductor chip is mounted on the substrate such that the back surface of the one surface of the first semiconductor chip faces the substrate,
    2. The second semiconductor chip is mounted on the first semiconductor chip so that a surface on the back side of the one surface of the second semiconductor chip faces the first semiconductor chip. 7. The semiconductor device according to any one of items 1 to 6.
PCT/JP2013/082966 2012-12-18 2013-12-09 Semiconductor device WO2014097916A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310411A (en) * 2005-04-26 2006-11-09 Fujitsu Ltd Semiconductor device
WO2009079749A1 (en) * 2007-12-20 2009-07-02 Mosaid Technologies Incorporated Data storage and stackable configurations
JP2011222807A (en) * 2010-04-12 2011-11-04 Elpida Memory Inc Semiconductor device
JP2012004559A (en) * 2010-06-17 2012-01-05 Samsung Electronics Co Ltd Semiconductor chip package and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310411A (en) * 2005-04-26 2006-11-09 Fujitsu Ltd Semiconductor device
WO2009079749A1 (en) * 2007-12-20 2009-07-02 Mosaid Technologies Incorporated Data storage and stackable configurations
JP2011222807A (en) * 2010-04-12 2011-11-04 Elpida Memory Inc Semiconductor device
JP2012004559A (en) * 2010-06-17 2012-01-05 Samsung Electronics Co Ltd Semiconductor chip package and method of manufacturing the same

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