WO2014097916A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2014097916A1
WO2014097916A1 PCT/JP2013/082966 JP2013082966W WO2014097916A1 WO 2014097916 A1 WO2014097916 A1 WO 2014097916A1 JP 2013082966 W JP2013082966 W JP 2013082966W WO 2014097916 A1 WO2014097916 A1 WO 2014097916A1
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Prior art keywords
semiconductor chip
electrode
semiconductor
pad
row
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PCT/JP2013/082966
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English (en)
Japanese (ja)
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聡 伊佐
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ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014097916A1 publication Critical patent/WO2014097916A1/fr

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device.
  • a DDP (Dual Die Package) type semiconductor device in which two semiconductor chips are stacked on a wiring board is known.
  • Patent Document 1 describe a semiconductor device in which two semiconductor chips are stacked face up. Hereinafter, the semiconductor device shown in FIGS. 8 to 10 of Patent Document 1 will be described.
  • this semiconductor device includes a wiring board, a first semiconductor chip, and a second semiconductor chip.
  • the first semiconductor chip and the second semiconductor chip have the same configuration.
  • a plurality of I / O (Input / Output) lands for the first semiconductor chip are formed at one end of the electrode formation surface of the wiring board. (Referred to as “first I / O land”).
  • a plurality of I / O lands for the second semiconductor chip (hereinafter referred to as “second I / O lands”) are formed at the other end of the electrode formation surface.
  • a plurality of CA (command address) lands are formed near the center of the electrode formation surface. The CA land is connected to the first and second semiconductor chips.
  • first bond finger row for connection to the first semiconductor chip.
  • the first bond finger row is classified into a bond finger row connected to the first I / O land via the wiring and through via, and a bond finger row connected to the CA land via the wiring and through via. Is done.
  • a bond finger row (hereinafter referred to as “second bond finger row”) for connection to the second semiconductor chip. Is formed).
  • the second bond finger row is classified into a bond finger row connected to the second I / O land via wiring and through vias, and a bond finger row connected to the CA land.
  • CA land is connected to the bond fingers in the second bond finger row as well as the bond fingers in the first bond finger row.
  • the first semiconductor chip has a rectangular shape and includes an I / O pad row and a CA pad row.
  • the I / O pad row and the CA pad row are arranged along a center line parallel to a pair of long sides facing each other of the first semiconductor chip.
  • the I / O system pad array and the CA system pad array are arranged in series so as to be in a straight line.
  • the I / O system pad row is disposed on one end side of the first semiconductor chip.
  • the CA-based pad row is disposed on the other end side of the first semiconductor chip.
  • one end of the first semiconductor chip (the end where the I / O pad array is formed) is the end side where the first I / O land of the wiring board is formed. It is mounted face-up on the chip mounting surface of the wiring board via an adhesive member.
  • the second semiconductor chip having the same configuration as the first semiconductor chip has one end (I / O system) of the second semiconductor chip. Face-up on the first semiconductor chip via an adhesive member so that the end where the pad row is formed is located on the end where the second I / O land is formed on the wiring board. Mounted on.
  • the second semiconductor chip is stacked on the first semiconductor chip in a state where the second semiconductor chip is rotated 180 degrees with respect to the first semiconductor chip about a straight line in the thickness direction passing through the center of the chip.
  • each bond finger constituting the first bond finger row is individually connected with an I / O pad or a CA pad of the first semiconductor chip by a wire. Connected to.
  • each bond finger constituting the second bond finger row is a wire, an I / O pad or a CA pad of the second semiconductor chip. And connected individually.
  • the first I / O land of the wiring board is connected to the I / O pad of the first semiconductor chip via a bond finger or a wire.
  • the second I / O land of the wiring board is connected to the I / O system pad of the second semiconductor chip via a bond finger or a wire.
  • the CA land of the wiring board is connected to the CA pad of the first semiconductor chip and the CA pad of the second semiconductor chip via bond fingers and wires, respectively.
  • the lower semiconductor chip mounted on the wiring board is used as in the above-described conventional technology.
  • a method is conceivable in which the upper semiconductor chip is stacked on the lower semiconductor chip while being rotated 180 degrees around the straight line in the thickness direction passing through the center of the own chip.
  • the length of the wiring that connects the CA land and the CA electrode pad of the lower semiconductor chip and the length of the wiring that connects the CA land and the CA electrode pad of the upper semiconductor chip are the same. And the difference will be larger.
  • FIG. 1A is a diagram showing an example of the lower semiconductor chip 101.
  • FIG. 1B is a diagram illustrating an example of the upper semiconductor chip 102.
  • the upper semiconductor chip 102 has the same configuration as the lower semiconductor chip 101.
  • an I / O connection pad row 101c and a CA connection pad row 101d are formed in the lower semiconductor chip 101.
  • the I / O system connection pad row 101c and the CA system connection pad row 101d are respectively connected to the I / O system pad row 101a and the CA system pad row 101b via the rewiring layer 101e.
  • an I / O connection pad row 102c and a CA connection pad row 102d are formed on the upper semiconductor chip 102.
  • the I / O system pad row 102a, CA system pad row 102b, I / O system connection pad row 102c, and CA system connection pad row 102d of the upper semiconductor chip 102 are respectively connected to the I / O system of the lower semiconductor chip 101. This corresponds to the pad row 101a, the CA-type pad row 101b, the I / O-type connection pad row 101c, and the CA-type connection pad row 101d.
  • FIG. 2A is a diagram showing a connection relationship between the wiring board 103 and the lower semiconductor chip 101.
  • FIG. 2B is a diagram illustrating a connection relationship between the wiring substrate 103 and the upper semiconductor chip 102.
  • the chip mounting surface 103-1 of the wiring substrate 103 has an I / O pin bond finger row 103 a 1, a CA pin bond finger row 103 a 2, an I / O pin bond finger row 103 b 1, and a CA pin. Bond finger row 103b2 is formed.
  • the I / O pin bond finger row 103 a 1 is connected to the I / O connection pad row 101 c of the lower semiconductor chip 101 via the wire 104.
  • the CA pin bond finger row 103 a 2 is connected to the CA connection pad row 101 d of the lower semiconductor chip 101 through the wire 104.
  • the I / O pin bond finger row 103 b 1 is connected to the I / O connection pad row 102 c of the upper semiconductor chip 102 via the wire 104.
  • the CA pin bond finger row 103b2 is connected to the CA connection pad row 102d of the upper semiconductor chip 102 via the wire 104.
  • the bond finger 103a20 in the CA pin bond finger row 103a2 connected to the CA0 pad 101d0 of the lower semiconductor chip 101 and the CA0 pad 102d0 of the upper semiconductor chip 102 are connected.
  • the bond pin 103b20 in the CA pin bond finger row 103b2 is connected to a common CA0 land.
  • FIG. 3 is a diagram for explaining the connection between the bond finger 103a20 and the CA0 land 105c0 and the connection between the bond finger 103b20 and the CA0 land 105c0.
  • an electrode forming surface 103-2 which is the back surface of the chip mounting surface 103-1, is provided with an I / O land 105a for the lower semiconductor chip 101 and an I / O for the upper semiconductor chip 102.
  • An O land 105b and a CA land 105c are formed.
  • the CA0 lands 105c0 are connected to the bond fingers 103a20 and 103b20.
  • the length of the wiring from the CA0 land 105c0 to the bond finger 103a20 is significantly different from the length of the wiring from the CA0 land 105c0 to the bond finger 103b20.
  • the difference in the length of the wiring becomes larger as the CA0 land 105c0 is closer to one of the bond fingers 103a20 and 103b20.
  • This difference in wiring length makes it difficult to adjust the deviation of the operation timing of the upper and lower semiconductor chips, and becomes a factor that hinders the high-speed operation of the semiconductor device.
  • the semiconductor device of the present invention is A substrate, a first semiconductor chip mounted on the substrate, and a second semiconductor chip stacked on the first semiconductor chip,
  • the first and second semiconductor chips are: A surface defined by first and second sides facing each other; A group of electrodes including first and second electrodes of a command address system arranged in a central region of the one surface in parallel with the first side; A third electrode disposed on the one surface along the first side; Each having a fourth electrode disposed on the one surface along the second side,
  • the first electrode of the first semiconductor chip is the third electrode of the first semiconductor chip
  • the second electrode of the first semiconductor chip is the first electrode.
  • the first electrode of the second semiconductor chip is the fourth electrode of the second semiconductor chip
  • the second electrode of the second semiconductor chip is the first electrode.
  • Each of the second semiconductor chips is electrically connected to the third electrode, and the first side of the second semiconductor chip is on the second side of the first semiconductor chip,
  • the second semiconductor chip is stacked on the first semiconductor chip so that the second side of the second semiconductor chip is positioned on the first side of the first semiconductor chip.
  • the first semiconductor chip is configured such that the first electrode is electrically connected to the third electrode and the second electrode is electrically connected to the fourth electrode.
  • the second semiconductor chip is configured such that the first electrode is electrically connected to the fourth electrode, and the second electrode is electrically connected to the third electrode.
  • the first side of the second semiconductor chip is on the second side of the first semiconductor chip, and the second side of the second semiconductor chip is the first semiconductor chip. They are stacked on the first semiconductor chip so as to be positioned on the first side.
  • the third electrode connected to the first electrode of the first semiconductor chip and the fourth electrode connected to the first electrode of the second semiconductor chip are connected to the first electrode of the first semiconductor chip. 1 can be arranged on one side.
  • the fourth electrode connected to the second electrode of the first semiconductor chip and the third electrode connected to the second electrode of the second semiconductor chip are connected to the first electrode of the first semiconductor chip. It can be arranged on the two sides. For this reason, it becomes possible to reduce the difference in the wiring length of the corresponding command address system in the upper and lower semiconductor chips on the substrate.
  • the present invention it is possible to reduce the difference in the wiring length of the corresponding command address system in the upper and lower semiconductor chips on the wiring board. For this reason, it becomes easy to adjust the shift of the operation timing due to the difference in the wiring length, and the speed of the semiconductor device can be increased.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device 1 according to a first embodiment of the present invention.
  • 3 is a plan view showing an electrode forming surface side of the semiconductor device 1;
  • FIG. 2 is a plan view showing a chip mounting surface side of the semiconductor device 1;
  • FIG. 3 is a cross-sectional view schematically showing a semiconductor device 1 according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing a chip mounting surface side of the semiconductor device 1;
  • FIG. 1 is a plan view showing a semiconductor chip 20.
  • 2 is a plan view showing a semiconductor chip 30.
  • FIG. 3 It is a figure for demonstrating the connection of the bond finger for CA0, and the land for CA0.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • FIG. 3 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor device 1.
  • It is a figure showing semiconductor chip 20X used for semiconductor device 1A of a 2nd embodiment of the present invention. It is the figure which showed the semiconductor chip 30X used for the semiconductor device 1A of 2nd Embodiment of this invention.
  • 1 is a plan view schematically showing a semiconductor device 1A.
  • 1 is a plan view schematically showing a semiconductor device 1A. It is the figure which showed semiconductor chip 20Y used for the semiconductor device 1B of 3rd Embodiment of this invention.
  • FIG. 6 is a diagram showing a switching circuit 60.
  • FIG. 4 is a cross-sectional view schematically showing the semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 4 shows a cross section in a direction perpendicular to the substrate.
  • the semiconductor device 1 is a DDP type semiconductor package in which two semiconductor chips 20 and 30 are stacked.
  • the semiconductor chip 20 is an example of a first semiconductor chip.
  • the semiconductor chip 30 is an example of a second semiconductor chip.
  • FIG. 5 is a plan view schematically showing the semiconductor device 1 shown in FIG. FIG. 5 shows the electrode forming surface 10b side on which a plurality of lands 13 are formed.
  • FIG. 6A and 6B are plan views schematically showing the semiconductor device 1 shown in FIG. 6A and 6B show the chip mounting surface 10a side on which a plurality of bond fingers 15 are formed.
  • FIG. 6A also shows the connection relationship between the lower semiconductor chip 20 and the bond finger rows 15a and 15b.
  • FIG. 6B also shows a connection relationship between the upper semiconductor chip 30 and the bond finger rows 15c and 15d.
  • FIG. 7A is a plan view showing the lower semiconductor chip 20.
  • FIG. 7B is a plan view showing the upper semiconductor chip 30.
  • the insulating layer on the rewiring layer 28 is omitted.
  • the semiconductor device 1 has a wiring substrate 10 made of, for example, a 0.2 mm thick glass epoxy base material (insulating substrate).
  • the wiring board 10 is formed in a substantially rectangular shape.
  • the wiring substrate 10 has a chip mounting surface 10a on which the two semiconductor chips 20 and 30 are stacked, and an electrode forming surface 10b that is the back surface of the chip mounting surface 10a.
  • the wiring 18 made of a conductive material such as Cu is formed on the chip mounting surface 10a.
  • the wiring 18 is partially covered with an insulating film, for example, a solder resist 14.
  • Bond fingers 15 are formed in the wiring regions exposed from the solder resist 14 on the chip mounting surface 10a.
  • a plurality of lands (external electrodes) 13 on which solder balls 17 are mounted are formed on the electrode forming surface 10b.
  • the lands 13 are electrically connected to the bond fingers 15 on the chip mounting surface 10 a through through vias 19 and wirings 18 formed in the wiring substrate 10.
  • the lands 13a-13c formed on the electrode forming surface 10b are arranged in a grid at predetermined intervals.
  • Each land 13 includes a bond finger belonging to one of the bond finger rows 15a to 15d, a wire 42, an I / O connection pad row 23a, 23b, 33a, 33b, or a CA connection pad row 24a, 24b, 34a,
  • the connection pads belonging to any one of 34 b and the rewiring layer 28 are electrically connected to the pads belonging to any of the I / O pad rows 21 and 31 or the CA pad rows 22 and 32. ing.
  • the land 13 is classified into two types according to the input / output system of the pad rows 21, 22, 31, and 32 of the semiconductor chips 20 and 30.
  • I / O lands 13a and 13c connected to data (DQ) system signals and DQ system power supply / GND, that is, input / output system electrode pad (I / O system pad) rows 21 and 31. .
  • the other is the CA land 13b connected to the command address system electrode pad (CA system pad) rows 22 and 32.
  • the I / O lands 13a and 13c are arranged separately at both ends of the electrode forming surface 10b.
  • the I / O lands 13a and 13c arranged at each end are assigned to the semiconductor chips 20 and 30, respectively.
  • an I / O land 13a corresponding to the semiconductor chip 20 is disposed at an upper end portion (first end portion) 11 as viewed in FIG.
  • an I / O land 13c corresponding to the semiconductor chip 30 is disposed at the lower end (second end) 12 as viewed in FIG.
  • a CA land 13b is disposed between the I / O lands 13a and 13c.
  • the semiconductor chip 20 is mounted on the chip mounting surface 10a via an adhesive member 41a such as DAF (Die Attached Film) or elastomer.
  • an adhesive member 41a such as DAF (Die Attached Film) or elastomer.
  • the semiconductor chip 20 is formed in a substantially rectangular plate shape as shown in FIGS. 6A and 7A.
  • a memory circuit and a plurality of electrode pads are formed on a pad forming surface 20 a that is one surface.
  • the pad forming surface 20a is a surface partitioned by long sides 25a and 25b facing each other.
  • the long side 25a is an example of a first side.
  • the long side 25b is an example of the second side.
  • the pad forming surface 20a includes an I / O system pad row 21, a CA system pad row 22, I / O system connection pad rows 23a and 23b, and a CA system connection pad row 24a.
  • 24b, a rewiring layer 28, and insulating layers 29a and 29b are formed.
  • the pads (electrodes) included in the I / O system pad row 21 are electrode pads connected to the pads included in the I / O system connection pad row 23a via the rewiring layer 28, and I / O system connection pad rows. 23b and an electrode pad connected via the redistribution layer 28.
  • an insulating layer 29 a is formed under the rewiring layer 28.
  • an insulating layer 29b is formed except for the pad portion.
  • the pads (electrodes) included in the CA system pad row 22 are the electrode pads (for example, the pad 22a) connected to the pads included in the CA system connection pad row 24a via the rewiring layer 28, and the CA system connection pad row. 24b and an electrode pad (for example, pad 22b) connected via the redistribution layer 28.
  • the pad 22a is an example of the first electrode.
  • the pad 22b is an example of a second electrode.
  • the I / O system pad row 21 and the CA system pad row 22 are aligned along a center line parallel to a pair of opposing long sides 25a and 25b of the rectangular semiconductor chip 20. Are arranged in series.
  • the I / O system pad row 21 is arranged close to the first end portion 26 side of the semiconductor chip 20.
  • the CA pad row 22 is arranged close to the second end 27 side.
  • the I / O pad row 21 and the CA pad row 22 are included in the electrode group.
  • the I / O system connection pad row 23a and the CA system connection pad row 24a are arranged in series on the pad forming surface 20a so as to be in a straight line along the long side 25a.
  • the I / O system connection pad row 23 a is disposed on the first end portion 26 side of the semiconductor chip 20.
  • the CA connection pad row 24a is arranged on the second end portion 27 side.
  • the electrode pad (for example, pad 24aa) included in the CA-based connection pad row 24a is an example of a third electrode.
  • the I / O connection pad row 23b and the CA connection pad row 24b are arranged in series on the pad forming surface 20a so as to be in a straight line along the long side 25b.
  • the I / O system connection pad row 23b is disposed on the first end portion 26 side.
  • the CA connection pad row 24b is disposed on the second end 27 side.
  • the electrode pad (for example, pad 24bb) included in the CA-based connection pad row 24b is an example of a fourth electrode.
  • a passivation film (not shown) for protecting the pad formation surface 20a is formed on the pad formation surface 20a excluding the I / O connection pad rows 23a and 23b and the CA connection pads 24a and 24b.
  • the semiconductor chip 20 is arranged on the wiring substrate 10 face up so that the first end portion 26 of the semiconductor chip 20 is located on the first end portion 11 side of the wiring substrate 10. ing. That is, in the semiconductor chip 20, the I / O system connection pad rows 23 a and 23 b arranged at the first end portion 26 of the semiconductor chip 20 are arranged at the first end portion 11 of the wiring substrate 10. The I / O land 13a and the bond finger row 15a are adjacent to each other.
  • Each pad included in the I / O system connection pad rows 23a and 23b of the semiconductor chip 20 is individually connected to a bond finger included in the bond finger row 15a by a conductive wire 42 made of, for example, Au or Cu. So that they are electrically connected.
  • the bond finger row 15a of the chip mounting surface 10a is in the vicinity of this long side along two long sides of the wiring substrate 10 parallel to the direction in which the I / O pad row 21 of the stacked semiconductor chips 20 extends. Each is arranged. Further, the bond finger row 15 a is arranged close to the first end portion 11 side of the wiring substrate 10.
  • Each pad included in the CA connection pad rows 24a and 24b of the semiconductor chip 20 is electrically connected to the bond finger included in the bond finger row 15b by being individually connected by the wire 42.
  • the bond finger row 15b of the chip mounting surface 10a is in the vicinity of the long side along two long sides of the wiring substrate 10 parallel to the direction in which the I / O pad row 21 of the stacked semiconductor chips 20 extends. Each is arranged. Further, the bond finger row 15 b is arranged close to the second end portion 12 side of the wiring substrate 10.
  • the semiconductor chip 30 has the same configuration as the semiconductor chip 20 except for the connection relationship between the pads included in the CA system pad row and the pads included in the CA system connection pad row by the redistribution layer (see FIGS. 7A and 7B). .
  • the semiconductor chip 30 is formed in a substantially rectangular plate shape as shown in FIGS. 6B and 7B.
  • a memory circuit and a plurality of electrode pads are formed on a pad forming surface 30 a that is one surface of the semiconductor chip 30.
  • the pad forming surface 30a is a surface partitioned by long sides 35a and 35b facing each other.
  • the long side 35a is an example of a first side.
  • the long side 35b is an example of a second side.
  • the pad forming surface 30a includes an I / O pad row 31, a CA pad row 32, I / O connection pad rows 33a and 33b, CA connection pad rows 34a and 34b, and a rewiring layer 28. Insulating layers 29a and 29b are formed.
  • the I / O pad row 31, the CA pad row 32, the I / O connection pad rows 33a and 33b, and the CA connection pad rows 34a and 34b in the semiconductor chip 30 are respectively This corresponds to the I / O pad row 21, the CA pad row 22, the I / O connection pad rows 23a and 23b, and the CA connection pad rows 24a and 24b in the semiconductor chip 20.
  • the pads in the CA pad row 22 (pads 22a corresponding to CA1) connected to the pads in the CA connection pad row 24a of the semiconductor chip 20 (for example, the pads 24aa corresponding to CA1).
  • the corresponding pad in the CA system pad row 32 (pad 32a corresponding to CA1) is connected to the pad in the CA system connection pad row 34b (pad 34bb corresponding to CA1).
  • the pad 32a corresponding to CA1 in the semiconductor chip 30 is an example of the first electrode.
  • the pad 35bb connected to the pad 32a is an example of a fourth electrode.
  • the pad 32b corresponding to CA0 in the semiconductor chip 30 is an example of a second electrode.
  • the pad 34aa connected to the pad 32b is an example of a third electrode.
  • the direction drawn by the rewiring layer 28 is opposite in each pad in the CA-based pad row.
  • the semiconductor chip 30 is disposed on the semiconductor chip 20 face up so that the first end 36 of the semiconductor chip 30 is located on the second end 12 side of the wiring substrate 10. As shown in FIG. ing. That is, the semiconductor chip 30 has the I / O connection pad rows 33a and 33b arranged on the first end portion 36 side for the semiconductor chip 30 arranged on the second end portion 12 side of the wiring board 10. It is arranged so as to be adjacent to the I / O land 13c.
  • an FOW 41b that is an adhesive member is disposed between the semiconductor chip 20 and the semiconductor chip 30.
  • a part of the wire 42 that electrically connects the semiconductor chip 20 and the wiring substrate 10 is embedded in the FOW 41b.
  • Each pad included in the I / O system connection pad row 33a, 33b of the semiconductor chip 30 is electrically connected to the bond finger included in the bond finger row 15c by being individually connected by the wire 42. .
  • the bond finger row 15c is formed on the chip mounting surface 10a so as to be juxtaposed with the bond finger row 15b.
  • Each pad included in the CA connection pad row 34a, 34b of the semiconductor chip 30 is electrically connected to the bond finger included in the bond finger row 15d by being individually connected by the wire 42.
  • the bond finger row 15d is formed on the chip mounting surface 10a so as to be juxtaposed with the bond finger rows 15a and 15b.
  • FIG. 8 shows the connection between the CA0 bond finger 15b0 and the CA0 land 13b0 in the bond finger row 15b for the semiconductor chip 20, and the connection between the CA0 bond finger 15d0 and the CA0 land 13b0 in the bond finger row 15d. It is a figure for demonstrating.
  • a sealing body 43 made of a thermosetting resin such as an epoxy resin is formed on the chip mounting surface 10 a of the wiring substrate 10.
  • the semiconductor chips 20 and 30 and the wire 42 are covered with a sealing body 43 and protected from the outside.
  • the semiconductor device 1 includes the substrate 10, the first semiconductor chip 20 mounted on the substrate 10, and the second semiconductor chip 30 stacked on the first semiconductor chip 20. Have.
  • the first and second semiconductor chips 20 and 30 have first surfaces 20a and 30a defined by first and second sides 25a, 25b, 35a and 35b facing each other, and a first region in the central region of the first surfaces 20a and 30a.
  • the first electrode 22a of the first semiconductor chip 20 is the third electrode 24aa of the first semiconductor chip 20, and the second electrode 22b of the first semiconductor chip 20 is the first.
  • the semiconductor chip 20 is configured to be electrically connected to the fourth electrode 24bb.
  • the first electrode 32a of the second semiconductor chip 30 is the fourth electrode 34bb of the second semiconductor chip 30, and the second electrode 32b of the second semiconductor chip 30 is the second.
  • the first side 35a of the second semiconductor chip 30 is on the second side 25b side of the first semiconductor chip 20, and is electrically connected to the third electrode 34aa of the semiconductor chip 30.
  • the second semiconductor chip 30 is stacked on the first semiconductor chip 20 so that the second side 35b is positioned on the first side 25a side of the first semiconductor chip 20, respectively.
  • the third electrode 24aa connected to the first electrode 22a of the semiconductor chip 20 and the fourth electrode 35bb connected to the first electrode 32a of the semiconductor chip 30 are replaced with the first electrode of the semiconductor chip 20.
  • the fourth electrode 24bb connected to the second electrode 22b of the semiconductor chip 20 and the third electrode 34aa connected to the second electrode 32b of the semiconductor chip 30 are connected to the second electrode 22b of the semiconductor chip 20. It can be arranged on the side 25b side.
  • the first semiconductor chip 20 is mounted on the substrate 10 so that the surface on the back side of the one surface 20a of the first semiconductor chip 20 faces the substrate 10.
  • the semiconductor chip 30 is mounted on the first semiconductor chip 20 so that the back surface of the one surface 30 a of the second semiconductor chip 30 faces the first semiconductor chip 20.
  • the first semiconductor chip 20 and the second semiconductor chip 30 can be stacked face up.
  • 9A to 9F are cross-sectional views schematically showing each step of the method for manufacturing the semiconductor device 1 of the present embodiment.
  • a wiring mother board 50 is prepared.
  • the wiring mother board 50 used in this embodiment is processed by a MAP (Mold Array Process) method.
  • a plurality of product forming portions 51 are arranged in a matrix on the wiring mother board 50.
  • the product forming part 51 is an area to be the wiring board 10 after being cut and separated.
  • a dicing line 52 is provided between the product forming portions 51.
  • a frame part (not shown) is provided around the product forming part 51 arranged in a matrix. Positioning holes (not shown) for carrying and positioning the wiring mother board 50 are provided in the frame portion at predetermined intervals.
  • the semiconductor chip 20 is placed on each product forming portion 51 of the wiring mother board 50, and a DAF, for example, a tape member having an adhesive layer on both surfaces of an insulating substrate, or an adhesive member 41a such as an elastomer. Adhering and fixing through.
  • a DAF for example, a tape member having an adhesive layer on both surfaces of an insulating substrate, or an adhesive member 41a such as an elastomer. Adhering and fixing through.
  • the semiconductor chip 20 is arranged on the product forming portion 51 so that the back surface of the pad forming surface 20a of the semiconductor chip 20 faces the product forming portion (wiring substrate) 51.
  • the pads in the I / O system connection pad rows 23 a and 23 b of the semiconductor chip 20 and the bond fingers in the bond finger row 15 a of the wiring substrate 10 are connected by wires 42. Further, the pads in the CA-based connection pad rows 24 a and 24 b of the semiconductor chip 20 and the bond fingers in the bond finger row 15 b of the wiring substrate 10 are connected by wires 42.
  • the wire bonding of the semiconductor chip 20 is performed before the semiconductor chip 30 is mounted on the pad forming surface 20a of the semiconductor chip 20.
  • the semiconductor chip 30 is mounted on the pad forming surface 20a of the semiconductor chip 20 via an adhesive member 41b such as FOW, and the semiconductor chip 20 and the semiconductor chip 30 are laminated.
  • the electrode pads of the semiconductor chip 30 and the bond fingers 15 formed near the boundary of the product forming portion 51 are connected by the wire 42 in the same manner as the semiconductor chip 20.
  • the connection between the electrode pad and the bond finger 15 by the wire 42 can also be performed by reverse bonding in order to lower the wire loop.
  • a sealing body 43 made of an insulating resin that collectively covers the chip mounting surface 50a of the wiring motherboard 50 is formed.
  • the wiring mother board 50 is closed with a molding die including an upper mold and a lower mold (not shown), for example.
  • a sealing body 43 is formed by press-fitting a thermosetting epoxy resin into a cavity formed by an upper mold and a lower mold from a gate (not shown), filling the cavity with resin, and then thermosetting the resin.
  • conductive solder balls 17 made of solder or the like are mounted on the plurality of lands 13 arranged in a grid pattern on the electrode formation surface 50b of the wiring mother board 50.
  • a ball mounting tool (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 13 on the wiring motherboard 50 is used.
  • the solder balls 17 are held in the suction holes, and the flux is transferred and formed on the held solder balls 17 and then mounted on the lands 13 of the wiring mother board 50 in a lump.
  • the solder balls 17 are fixed to the wiring mother board 50 by reflowing at a predetermined temperature.
  • the wiring mother board 50 in which the mounting of the solder balls 17 on all the lands 13 is completed is sent to the board dicing process.
  • the wiring mother board 50 is cut along the dicing lines 52 and separated into the product forming portions 51.
  • the wiring mother substrate 50 is supported by the dicing tape by bonding the sealing body 43 of the wiring mother substrate 50 to a dicing tape (not shown).
  • the wiring mother board 50 is cut vertically and horizontally along the dicing line 52 by a dicing blade (not shown), and the wiring mother board 50 is separated into pieces.
  • a DDP type semiconductor device as shown in FIG. 4 can be obtained by picking up from the dicing tape.
  • FIGS. 7A and 7B are diagrams showing semiconductor chips 20X and 30X used in the semiconductor device 1A according to the second embodiment of the present invention.
  • 10A and 10B the same components as those shown in FIGS. 7A and 7B are denoted by the same reference numerals.
  • 11A and 11B are plan views schematically showing the semiconductor device 1A.
  • 11A and 11B show the chip mounting surface 10a side on which a plurality of bond fingers 15 are formed.
  • FIG. 11A also shows the connection relationship between the lower semiconductor chip 20X and the bond finger rows 15a and 15b.
  • FIG. 11B also shows the connection relationship between the upper semiconductor chip 30X and the bond finger rows 15c and 15d.
  • 11A and 11B the same components as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.
  • the insulating layer on the rewiring layer 28 is omitted.
  • the lead direction of the rewiring layer of the corresponding pad (for example, the pad corresponding to CA0) in the CA-based pad row of the semiconductor chips 20 and 30 is set to the semiconductor chip 20 and the semiconductor chip 30. And in the opposite direction.
  • the semiconductor device 1A of the second embodiment in addition to the drawing direction of the rewiring layer of the corresponding pad in the CA pad row, the correspondence in the I / O pad row
  • the drawing direction of the rewiring layer of the pads to be performed (for example, pads corresponding to DQS) is also opposite in the semiconductor chip 20X and the semiconductor chip 30X.
  • the semiconductor device 1A of the second embodiment will be described focusing on differences from the semiconductor device 1 of the first embodiment.
  • the semiconductor chip 20X has the same configuration as the semiconductor chip 20 shown in FIG. 7A.
  • an I / O system connected to a pad for example, a pad corresponding to DQS; a seventh electrode
  • the pad (pad corresponding to DQS; fifth electrode) in the I / O-based pad row 31 corresponding to the pad (pad corresponding to DQS; fifth electrode) in the pad row 21 is formed on the semiconductor chip 30X. It is connected to a pad (pad corresponding to DQS; eighth electrode) in the I / O system connection pad row 33b.
  • the pad (pad corresponding to DQSB; sixth electrode) in the I / O system pad row 31 corresponding to the pad (pad corresponding to DQSB; sixth electrode) is connected to the I / O system of the semiconductor chip 30X. It is connected to a pad (pad corresponding to DQSB; seventh electrode) in the pad row 33a.
  • the fifth electrode and the sixth electrode are pads corresponding to, for example, DQS, DQSB, DM (TDQS), and TDQSB.
  • the electrode group further includes the fifth electrode and the sixth electrode in the I / O-based pad rows 21 and 31.
  • the first and second semiconductor chips 20X and 30X are further provided with pads (first pads) in the I / O connection pad rows 23a and 33a arranged on the pad forming surfaces 20a and 30a along the first sides 25a and 35a. 7) and pads (eighth electrodes) in the I / O connection pad rows 23b and 33b arranged on the pad forming surfaces 20a and 30a along the second sides 25b and 35b, respectively. .
  • the fifth electrode of the first semiconductor chip 20X is the seventh electrode of the first semiconductor chip 20X
  • the sixth electrode of the first semiconductor chip 20X is the first semiconductor chip.
  • Each of the 20X eighth electrodes is electrically connected.
  • the fifth electrode of the second semiconductor chip 30X is the eighth electrode of the second semiconductor chip 30X
  • the sixth electrode of the second semiconductor chip 30X is the second semiconductor chip. It is configured to be electrically connected to each of the 30X seventh electrodes.
  • chip pads such as DQS, DQSB, DM (TDQS), and TDQSB that cannot be handled by changing the allocation of I / O chip pads, can be arranged on the same side of the wiring board 10. Therefore, it is possible to further increase the speed of the semiconductor device.
  • FIGS. 7A and 7B are diagrams showing semiconductor chips 20Y and 30Y used in the semiconductor device 1B according to the third embodiment of the present invention. 12A and 12B, the same components as those shown in FIGS. 7A and 7B are denoted by the same reference numerals.
  • FIGS. 6A and 6B are plan views schematically showing the semiconductor device 1B.
  • 13A and 13B show the chip mounting surface side on which a plurality of bond fingers 15 are formed.
  • FIG. 13A also shows the connection relationship between the lower semiconductor chip 20Y and the bond finger rows 15a and 15b.
  • FIG. 13B also shows the connection relationship between the upper semiconductor chip 30Y and the bond finger rows 15c and 15d.
  • 13A and 13B the same components as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.
  • the insulating layer on the rewiring layer 28 is omitted.
  • the semiconductor chips 20Y and 30Y have the same configuration.
  • a switching circuit 60 as shown in FIG. 14 is formed.
  • the switching circuit 60 is an example of a setting circuit.
  • Switching circuit 60 includes receiving units 61 and 62 and selectors 63 and 64.
  • the number of switching circuits 60 is half that of the pads in the CA pad row 22.
  • the switching circuit 60 includes one pad (first electrode) in the CA system pad row 22 connected to the pad (third electrode) in the CA system connection pad row 24a, and a pad in the CA system connection pad row 24b.
  • One is provided for the combination of one pad (second electrode) in the CA-based pad row 22 connected to (fourth electrode).
  • the pads in the CA-based pad row 22 are divided into two pad units arranged in the pad arrangement direction, and one switching circuit 60 is provided for one set of the two pads. .
  • the accepting unit 61 accepts a signal from one pad (first electrode) in the CA system pad row 22 connected to the pad (third electrode) in the CA system connection pad row 24a.
  • the receiving unit 62 receives a signal from one pad (second electrode) in the CA pad array 22 connected to the pad (fourth electrode) in the CA connection pad array 24b.
  • the reception unit 61 When the reception unit 61 receives the signal, the reception unit 61 outputs the signal to the selectors 63 and 64. In addition, when receiving the signal, receiving unit 62 outputs the signal to selectors 63 and 64.
  • the output of the selector 63 is connected to an input unit 81 for inputting a signal into the semiconductor chip 20Y.
  • the output of the selector 64 is connected to an input unit 82 for inputting a signal into the semiconductor chip 20Y.
  • the selectors 63 and 64 also accept an MF signal whose signal level switches between “0” and “1” depending on, for example, whether or not a fuse in a fuse circuit (not shown) is cut.
  • the selector 63 When the MF signal is “0”, the selector 63 outputs a signal from the receiving unit 61 to the input unit 81, and the selector 64 outputs a signal from the receiving unit 62 to the input unit 82.
  • the selector 63 outputs a signal from the receiving unit 62 to the input unit 81, and the selector 64 outputs a signal from the receiving unit 61 to the input unit 82.
  • the number of switching circuits 60 is half that of the pads in the CA pad row 22.
  • the switching circuit 60 includes one pad (first electrode) in the CA system pad row 32 connected to the pad (third electrode) in the CA system connection pad row 34a, and a pad in the CA system connection pad row 34b.
  • One is provided for a combination of one pad (second electrode) in the CA-based pad row 32 connected to (fourth electrode).
  • the pads in the CA-based pad row 32 are divided into two pad units arranged in the pad arrangement direction, and one switching circuit 60 is provided for one set of the two pads. .
  • the accepting unit 61 accepts a signal from the pad (first electrode) in the CA system pad row 32 connected to the pad (third electrode) in the CA system connection pad row 34a.
  • the receiving unit 62 receives a signal from the pad (second electrode) in the CA system pad row 32 connected to the pad (fourth electrode) in the CA system connection pad row 34b.
  • the output of the selector 63 is connected to an input unit for inputting a signal into the semiconductor chip 30Y.
  • the output of the selector 64 is connected to an input unit for inputting a signal into the semiconductor chip 30Y.
  • the semiconductor device 1B includes the substrate 10, the first semiconductor chip 20Y mounted on the substrate 10, and the second semiconductor chip 30Y stacked on the first semiconductor chip 20Y. Have.
  • the first and second semiconductor chips 20Y and 30Y have first surfaces 20a and 30a defined by first and second sides 25a, 25b, 35a and 35b facing each other, and a first region in the central region of the first surfaces 20a and 30a.
  • a first connection state in which the first and second input sections 81 and 82 are connected to the first input section 81 and the second electrode is connected to the second input section 82;
  • the electrodes of the second input section 82 It has a second connection state of connecting the second electrode to the first input portion 81 as well as connection and switching circuit 60 to
  • the first electrode 22a of the first semiconductor chip 20Y is the third electrode 24aa of the first semiconductor chip 20Y, and the second electrode 22b of the first semiconductor chip 20Y is the first.
  • the semiconductor chip 20Y is configured to be electrically connected to the fourth electrode 24bb.
  • the first electrode 32a of the second semiconductor chip 30Y is the third electrode 34aa of the second semiconductor chip 30Y
  • the second electrode 32b of the second semiconductor chip 30Y is the second.
  • the first side 35a of the second semiconductor chip 30Y is on the second side 25b side of the first semiconductor chip 20Y, and is electrically connected to the fourth electrode 35bb of the semiconductor chip 30Y.
  • the second semiconductor chip 30Y is stacked on the first semiconductor chip 20Y so that the second side 35b is positioned on the first side 25a side of the first semiconductor chip 20Y.
  • the switching circuit 60 appropriately sets the first connection state and the second connection state, so that the substrate is mounted on the substrate as in the first embodiment.
  • the switching circuit 60 it is possible to reduce the difference in wiring length of the corresponding command address system in the upper and lower semiconductor chips.
  • the redistribution layers formed on the upper and lower semiconductor chips 20 and 30 have the same configuration. Therefore, only one type of semiconductor chip is prepared as the upper and lower semiconductor chips, and the cost can be reduced.
  • the rewiring of the pad is performed by providing the rewiring layer on the semiconductor chip.
  • the subwiring board is mounted on the semiconductor chip so that the rewiring of the pad is performed. May be.
  • the electrical connection between the first electrode of the semiconductor chips 20 and 20X and the third electrode of the semiconductor chips 20 and 20X, the second electrode of the semiconductor chips 20 and 20X, and Electrical connection between the fourth electrodes of the semiconductor chips 20 and 20X, electrical connection between the first electrodes of the semiconductor chips 30 and 30X and the fourth electrodes of the semiconductor chips 30 and 30X, and the semiconductor chip 30 , 30X, and the third electrode of the semiconductor chip 30, 30X, at least one connection may be made via a redistribution layer or a wiring substrate.
  • the electrical connection between the first electrode of the semiconductor chip 20Y and the third electrode of the semiconductor chip 20Y, the second electrode of the semiconductor chip 20Y, and the fourth electrode of the semiconductor chip 20Y Electrical connection between the first electrode of the semiconductor chip 30Y and the fourth electrode of the semiconductor chip 30Y, and the second electrode of the semiconductor chip 30Y and the third electrode of the semiconductor chip 30Y.
  • at least one of the connections may be made via a rewiring layer or a wiring board.
  • the semiconductor chip is applied to a semiconductor chip in which a plurality of electrode pads are arranged in a row in a central region of one surface.
  • a plurality of electrode pads in two or three or more rows in a central region of one surface.
  • a semiconductor chip in which is arranged may be applied.
  • a plurality of electrode rows arranged in parallel to the first side may be formed by electrodes included in the electrode group.

Abstract

La présente invention a trait à un dispositif à semi-conducteur qui comprend un substrat et des première et seconde puces semi-conductrices. Chacune des première et seconde puces semi-conductrices comprend : une surface qui est divisée en fonction de premier et second bords qui sont des côtés opposés ; un groupe d'électrodes qui est prévu sur une zone centrale de la surface en parallèle avec le premier bord, le groupe d'électrodes comprenant des premières et deuxièmes électrodes de type à adresse de commande ; des troisièmes électrodes qui sont prévues sur la surface le long du premier bord ; et des quatrièmes électrodes qui sont prévues sur la surface le long du second bord. Dans la première puce semi-conductrice, les premières électrodes sont électriquement connectées aux troisièmes électrodes, et les deuxièmes électrodes sont électriquement connectées aux quatrièmes électrodes. Dans la seconde puce semi-conductrice, les premières électrodes sont électriquement connectées aux quatrièmes électrodes, et les deuxièmes électrodes sont électriquement connectées aux troisièmes électrodes. La seconde puce semi-conductrice est superposée sur la première puce semi-conductrice de manière à ce que le premier bord de la seconde puce semi-conductrice soit positionné du côté du second bord de la première puce semi-conductrice et de manière à ce que le second bord de la seconde puce semi-conductrice soit positionné du côté du premier bord de la première puce semi-conductrice.
PCT/JP2013/082966 2012-12-18 2013-12-09 Dispositif à semi-conducteur WO2014097916A1 (fr)

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JP2012-275624 2012-12-18

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310411A (ja) * 2005-04-26 2006-11-09 Fujitsu Ltd 半導体装置
WO2009079749A1 (fr) * 2007-12-20 2009-07-02 Mosaid Technologies Incorporated Stockage de données et configurations empilables
JP2011222807A (ja) * 2010-04-12 2011-11-04 Elpida Memory Inc 半導体装置
JP2012004559A (ja) * 2010-06-17 2012-01-05 Samsung Electronics Co Ltd 半導体チップパッケージ及び半導体チップパッケージの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310411A (ja) * 2005-04-26 2006-11-09 Fujitsu Ltd 半導体装置
WO2009079749A1 (fr) * 2007-12-20 2009-07-02 Mosaid Technologies Incorporated Stockage de données et configurations empilables
JP2011222807A (ja) * 2010-04-12 2011-11-04 Elpida Memory Inc 半導体装置
JP2012004559A (ja) * 2010-06-17 2012-01-05 Samsung Electronics Co Ltd 半導体チップパッケージ及び半導体チップパッケージの製造方法

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