TW201432879A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate and first and second semiconductor chips. Each of the first and second semiconductor chips includes: a surface that is divided according to first and second edges that are on opposite sides an electrode group provided in a center area of the surface in parallel with the first edge, the electrode group including first and second electrodes of a command address type third electrodes provided on the surface along the first edge and fourth electrodes provided on the surface along the second edge. In the first semiconductor chip, the first electrodes are electrically connected with the third electrodes, and the second electrodes are electrically connected to the fourth electrodes. In the second semiconductor chip, the first electrodes are electrically connected with the fourth electrodes, and the second electrodes are electrically connected with the third electrodes. The second semiconductor chip is stacked on the first semiconductor chip in such a manner that the first edge of the second semiconductor chip is positioned on the second edge side of the first semiconductor chip and the second edge of the second semiconductor chip is positioned on the first edge side of the first semiconductor chip.

Description

Semiconductor device

The present invention relates to a semiconductor device.

A DDP (Dual Die Package) type semiconductor device in which two semiconductor wafers are stacked on a wiring board is known.

FIGS. 8 to 10 of Patent Document 1 are semiconductor devices in which two semiconductor wafers are stacked face up. Hereinafter, a semiconductor device shown in FIGS. 8 to 10 of Patent Document 1 will be described.

As shown in FIG. 8 of Patent Document 1, the semiconductor device includes a wiring substrate, a first semiconductor wafer, and a second semiconductor wafer. The first semiconductor wafer and the second semiconductor wafer have the same configuration.

In addition, as shown in FIG. 10 of the patent document 1, one end of the electrode forming surface of the wiring board is a plurality of I/O (Input/Output) end faces for forming a first semiconductor wafer (hereinafter referred to as It is "the first I/O connection end face"). The other end portion of the electrode forming surface is a plurality of I/O connecting end faces (hereinafter referred to as "second I/O connecting end faces") for forming a second semiconductor wafer. Also, it is shaped near the center of the electrode forming surface A CA (command. address) with a complex number is used. The CA terminal is connected to the first and second semiconductor wafers.

As shown in FIG. 9(b) of the patent document 1, a bond finger array (hereinafter referred to as a "first joint finger row" for forming a connection with the first semiconductor wafer is formed on the wafer mounting surface of the wiring board. ).

The first bonding finger is classified into a bonding finger that is connected to the first I/O connecting end surface via the wiring and the through hole, and a bonding finger that is connected to the CA connecting end surface via the wiring and the through hole.

Further, as shown in FIG. 9(a) of Patent Document 1, a bonding finger (hereinafter referred to as a "second bonding finger") for connecting to the second semiconductor wafer is formed on the wafer mounting surface of the wiring board.

The second bonding finger is classified into a bonding finger that is connected to the second I/O connecting end surface via the wiring and the through hole, and a bonding finger that is connected to the CA connecting end surface.

In this manner, the CA end face is also connected to the joint finger in the second joint finger row together with the joint finger in the first joint finger row.

As shown in FIG. 9(b) of Patent Document 1, the first semiconductor wafer has a rectangular shape and includes an I/O pad array and a CA pad array.

The I/O pad row and the CA pad row are arranged along a center line parallel to the pair of long sides facing the first semiconductor wafer. The I/O pad row and the CA pad array are arranged in series so as to form a straight line. The I/O pad row is disposed on one end side of the first semiconductor wafer. The CA-based pad row is disposed on the other end side of the first semiconductor wafer.

The first semiconductor wafer is such that one end portion of the first semiconductor wafer (the end portion in which the I/O pad row is formed) is located on the end side of the first I/O connection end surface on which the wiring substrate is formed. The surface is mounted on the wafer mounting surface of the wiring board via the bonding member.

Further, as shown in FIG. 9(a) of Patent Document 1, the second semiconductor wafer having the same configuration as that of the first semiconductor wafer is one end portion of the second semiconductor wafer (the I/O type pad row is formed). The end portion is placed on the end portion side of the second I/O connecting end surface on which the wiring board is formed, and is mounted on the first semiconductor wafer via the bonding member.

In other words, the second semiconductor wafer is stacked on the first semiconductor wafer in a state where the first semiconductor wafer is rotated by 180 degrees with the straight line passing through the thickness direction of the center of the self-wafer as the axis.

As shown in FIG. 9(b) of Patent Document 1, each of the bonding fingers constituting the first bonding finger row is individually connected to the I/O pad or the CA pad of the first semiconductor wafer by wiring.

Further, as shown in FIG. 9(a) of Patent Document 1, each of the bonding fingers constituting the second bonding finger is individually connected to the I/O pad or the CA pad of the second semiconductor wafer by wiring. .

Therefore, the first I/O connection end surface of the wiring board is connected to the I/O type pad of the first semiconductor wafer via the bonding fingers or the wiring. The second I/O connection end surface of the wiring board is connected to the I/O type pad of the second semiconductor wafer via a bonding finger or a wiring.

Moreover, the CA end face of the wiring board is a CA type pad and a second semiconductor crystal of the first semiconductor wafer via bonding fingers or wires, respectively. The piece of CA is soldered to the pad.

[Advanced technical literature] [Patent Literature]

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2011-249582

In the semiconductor device in which a plurality of semiconductor wafers are stacked, when the electrode pad array is disposed in the central region of the semiconductor wafer, the wiring of the bonding fingers connecting the electrode pads of the semiconductor wafer and the wiring substrate becomes long. For this reason, wafer lamination in FOW (Film Over Wire) becomes difficult. Therefore, the RDL (Redistribution Layer) technique was used to review the electrode pad row to be rewired near the edge of the semiconductor wafer.

For this reason, for example, two semiconductor wafers having the same structure in which the electrode pads are rewiring to the vicinity of the edge of the semiconductor wafer are used, and the semiconductor wafer mounted on the lower side of the wiring substrate is as described in the above-described conventional technique. The method of laminating the upper semiconductor wafer on the lower semiconductor wafer in a state where the straight line in the thickness direction of the center of the self-wafer is rotated by 180 degrees.

However, in this method, the length of the wiring for connecting the CA electrode pads of the semiconductor end face and the lower semiconductor wafer, and the length of the wiring for connecting the CA terminal face and the CA electrode pad of the upper semiconductor wafer. The difference will become bigger.

The inventors of the present invention have made it clear that the difference is difficult to adjust the variation in the timing of the operation of the upper and lower semiconductor wafers, and there is a fear that the high-speed operation of the DDP-type semiconductor device is hindered. Hereinafter, this problem will be described with reference to FIGS. 1A, 1B, 2A, 2B, and 3.

FIG. 1A is a view showing an example of the semiconductor wafer 101 on the lower side. FIG. 1B is a view showing an example of the upper semiconductor wafer 102.

The upper semiconductor wafer 102 has the same configuration as the lower semiconductor wafer 101.

The semiconductor wafer 101 on the lower side is formed with an I/O type connection pad row 101c and a CA type connection pad row 101d in addition to the I/O pad row 101a and the CA pad row 101b. The I/O type connection pad row 101c and the CA type connection pad row 101d are connected to the I/O pad row 101a and the CA pad row 101b via the rewiring layer 101e, respectively.

The upper semiconductor wafer 102 is formed with an I/O type connection pad row 102c and a CA type connection pad row 102d in addition to the I/O pad row 102a and the CA pad row 102b.

The I/O pad row 102a of the upper semiconductor wafer 102, the CA pad row 102b, the I/O type connection pad row 102c, and the CA type connection pad row 102d are the I and the lower semiconductor wafer 101, respectively. The /O type pad row 101a, the CA type pad row 101b, the I/O type connection pad row 101c, and the CA type connection pad row 101d correspond.

FIG. 2A is a view showing a connection relationship between the wiring substrate 103 and the lower semiconductor wafer 101. FIG. 2B is a view showing a connection relationship between the wiring substrate 103 and the upper semiconductor wafer 102.

In the wafer mounting surface 103-1 of the wiring board 103, the I/O type stitch bonding finger 103a1, the CA type pin bonding finger 103a2, the I/O type stitch bonding finger 103b1, and the CA type stitch are formed. Refers to column 103b2.

As shown in FIG. 2A, the I/O type stitch bonding finger 103a1 is connected to the I/O system connection pad row 101c of the lower semiconductor wafer 101 via the wiring 104. The CA-type stitch bonding finger 103a2 is connected to the CA-type connection pad row 101d of the lower semiconductor wafer 101 via the wiring 104.

Further, as shown in FIG. 2B, the I/O type stitch bonding finger row 103b1 is connected to the I/O system connection pad row 102c of the upper semiconductor wafer 102 via the wiring 104. The CA-based stitch bonding finger 103b2 is connected to the CA-based connection pad row 102d of the upper semiconductor wafer 102 via the wiring 104.

Here, the bonding finger 103a20 (see FIG. 2A) in the bonding pin 103a2 of the CA type pin connected to the CA0 pad 101d0 of the lower semiconductor wafer 101 is connected to the bonding pad 102d0 of the CA0 of the upper semiconductor wafer 102. The bonding fingers 103b20 (see FIG. 2B) in the bonding finger row 103b2 of the CA-based stitch are formed to be connected to the common CA0 terminal.

3 is a view for explaining the connection between the joint finger 103a20 and the CA0 contact end surface 105c0, and the connection of the joint finger 103b20 and the CA0 joint end surface 105c0.

In FIG. 3, the electrode forming surface 103-2 of the surface on the back side of the wafer mounting surface 103-1 is formed with I/O for the semiconductor wafer 101 on the lower side. The connecting end face 105a, the I/O connecting end face 105b for the upper semiconductor wafer 102, and the CA connecting end face 105c.

Among the CA connecting end faces 105c, the CA0 connecting end faces 105c0 are connected to the engaging fingers 103a20 and the engaging fingers 103b20.

As shown in FIG. 3, the length of the wiring from the CA0 connecting end face 105c0 to the bonding finger 103a20 and the length of the wiring from the CA0 connecting end face 105c0 to the bonding finger 103b20 are significantly different. The difference in length of this wiring is larger as the CAO use end surface 105c0 approaches the one of the joint fingers 103a20 and 103b20.

The difference in the length of the wiring makes it difficult to adjust the variation in the timing of the operation of the upper and lower semiconductor wafers, and forms a factor that hinders the high-speed operation of the semiconductor device.

A semiconductor device according to the present invention includes a substrate, a first semiconductor wafer mounted on the substrate, and a second semiconductor wafer laminated on the first semiconductor wafer. Each of the first and second semiconductor wafers has a surface that is defined by the first and second sides facing each other, and a command address system that is disposed in parallel with the first side in a central region of the one surface. An electrode group of the first electrode and the second electrode; and a third electrode disposed on the one surface along the first side; and a fourth electrode disposed on the one surface along the second side, wherein the first semiconductor wafer is The first part of the first semiconductor wafer The first electrode is electrically connected to the third electrode of the first semiconductor wafer, and the second electrode of the first semiconductor wafer is electrically connected to the fourth electrode of the first semiconductor wafer. In the second semiconductor wafer, the first electrode of the second semiconductor wafer is electrically connected to the fourth electrode of the second semiconductor wafer, and the second electrode of the second semiconductor wafer is electrically connected to the second electrode. The third electrode of the semiconductor wafer is configured such that the first side of the second semiconductor wafer is located on the second side of the first semiconductor wafer, and the second side of the second semiconductor wafer is located in the second side The first side of the first semiconductor wafer is laminated on the first semiconductor wafer.

Therefore, in the first semiconductor wafer, the first electrode is electrically connected to the third electrode, and the second electrode is electrically connected to the fourth electrode. In the second semiconductor wafer, the first electrode is electrically connected to the fourth electrode, and the second electrode is electrically connected to the third electrode. Further, in the second semiconductor wafer, the first side of the second semiconductor wafer is positioned on the second side of the first semiconductor wafer, and the second side of the second semiconductor wafer is placed on the first side of the first semiconductor wafer. On the first semiconductor wafer.

Therefore, the third electrode connected to the first electrode of the first semiconductor wafer and the fourth electrode connected to the first electrode of the second semiconductor wafer can be disposed on the first side of the first semiconductor wafer. Further, the fourth electrode connected to the second electrode of the first semiconductor wafer and the third electrode connected to the second electrode of the second semiconductor wafer may be disposed on the second side of the first semiconductor wafer. Therefore, the corresponding instruction bits of the upper and lower semiconductor wafers on the substrate can be reduced. The difference in wiring length of the address system.

According to the present invention, it is possible to reduce the difference in wiring length of the corresponding command address system of the upper and lower semiconductor wafers on the wiring substrate. Therefore, it is easy to adjust the variation of the operation timing due to the difference in wiring length, and the speed of the semiconductor device can be increased.

1, 1A, 1B‧‧‧ semiconductor devices

10‧‧‧Wiring substrate

10a‧‧‧ wafer mounting surface

10b‧‧‧electrode forming surface

15a~15d‧‧‧Joining

20, 20X, 20Y‧‧‧ semiconductor wafer

30, 30X, 30Y‧‧‧ semiconductor wafer

21, 31‧‧‧I/O solder pad columns

22, 32‧‧‧CA welding pad column

23a, 23b, 33a, 33b‧‧‧I/O system connection pads

24a, 24b, 34a, 34b‧‧‧CA connection pads

28‧‧‧Rewiring layer

42‧‧‧ wiring

FIG. 1A is a view showing an example of a semiconductor wafer used in a DDR type semiconductor device.

FIG. 1B is a view showing an example of a semiconductor wafer used in a DDR type semiconductor device.

2A is a view showing an example of a DDR type semiconductor device on which a semiconductor wafer is mounted.

2B is a view showing an example of a DDR type semiconductor device on which a semiconductor wafer is mounted.

3 is a view showing an electrode forming surface side of a DDR type semiconductor device.

FIG. 4 is a cross-sectional view schematically showing the semiconductor device 1 according to the first embodiment of the present invention.

FIG. 5 is a plan view showing the electrode formation surface side of the semiconductor device 1.

FIG. 6A is a plan view showing the wafer mounting surface side of the semiconductor device 1.

FIG. 6B is a plan view showing the wafer mounting surface side of the semiconductor device 1.

FIG. 7A is a plan view showing the semiconductor wafer 20.

FIG. 7B is a plan view showing the semiconductor wafer 30.

Fig. 8 is a view for explaining the connection between the joint fingers for CA0 and the joint end faces of CA0.

FIG. 9A is a cross-sectional view schematically showing each process of the method of manufacturing the semiconductor device 1.

FIG. 9B is a cross-sectional view schematically showing each item of the method of manufacturing the semiconductor device 1.

FIG. 9C is a cross-sectional view schematically showing each item of the method of manufacturing the semiconductor device 1.

FIG. 9D is a cross-sectional view schematically showing each item of the method of manufacturing the semiconductor device 1.

9E is a cross-sectional view schematically showing each process of the method of manufacturing the semiconductor device 1.

FIG. 9F is a cross-sectional view schematically showing each process of the method of manufacturing the semiconductor device 1.

FIG. 10A is a view showing a semiconductor wafer 20X used in the semiconductor device 1A of the second embodiment of the present invention.

FIG. 10B is a view showing a semiconductor wafer 30X used in the semiconductor device 1A of the second embodiment of the present invention.

FIG. 11A is a plan view schematically showing the semiconductor device 1A.

FIG. 11B is a plan view schematically showing the semiconductor device 1A.

FIG. 12A is a view showing a semiconductor wafer 20Y used in the semiconductor device 1B of the third embodiment of the present invention.

FIG. 12B is a view showing a semiconductor wafer 30Y used in the semiconductor device 1B of the third embodiment of the present invention.

FIG. 13A is a plan view schematically showing the semiconductor device 1B.

FIG. 13B is a plan view schematically showing the semiconductor device 1B.

FIG. 14 is a diagram showing the switching circuit 60.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)

FIG. 4 is a cross-sectional view schematically showing the semiconductor device 1 according to the first embodiment of the present invention. 4 is a cross section showing a direction perpendicular to a substrate. The semiconductor device 1 is a DDP type semiconductor package in which two semiconductor wafers 20, 30 are stacked. The semiconductor wafer 20 is an example of a first semiconductor wafer. The semiconductor wafer 30 is an example of a second semiconductor wafer.

FIG. 5 is a plan view schematically showing the semiconductor device 1 shown in FIG. 4. Fig. 5 shows the electrode forming surface 10b side on which a plurality of joint end faces 13 are formed.

6A and 6B are plan views schematically showing the semiconductor device 1 shown in Fig. 4. 6A and 6B show the wafer mounting surface 10a side on which a plurality of bonding fingers 15 are formed. Fig. 6A also shows the connection relationship between the semiconductor wafer 20 on the lower side and the bonding fingers 15a, 15b. Fig. 6B also shows the connection relationship between the upper semiconductor wafer 30 and the bonding fingers 15c, 15d.

FIG. 7A is a plan view showing the semiconductor wafer 20 on the lower side. Fig. 7B is a plan view showing the upper semiconductor wafer 30.

In addition, the insulating layer on the rewiring layer 28 is omitted in FIGS. 6A, 6B, 7A, and 7B.

The semiconductor device 1 is a wiring substrate 10 having, for example, a 0.2 mm thick glass epoxy substrate (insulated substrate). The wiring board 10 is formed in a substantially rectangular shape.

The wiring board 10 is an electrode forming surface 10b having a wafer mounting surface 10a on which two semiconductor wafers 20 and 30 are stacked, and a surface on the back side of the wafer mounting surface 10a.

A wiring 18 made of a conductive material such as Cu is formed on the wafer mounting surface 10a. The wiring 18 is partially covered with an insulating film such as a solder resist 14.

In the wafer mounting surface 10a, the wiring region exposed from the solder resist 14 is formed with the bonding fingers 15 respectively.

The electrode forming surface 10b is formed with a plurality of end faces (external electrodes) 13 on which the solder balls 17 are respectively mounted. The connection end surface 13 is electrically connected to the bonding fingers 15 of the wafer mounting surface 10 a via the through holes 19 and the wirings 18 formed on the wiring substrate 10 .

As shown in Fig. 5, the joint end faces 13a-13c formed on the electrode forming surface 10b are arranged in a lattice shape at predetermined intervals.

Each of the joint end faces 13 is via a joint finger to which any one of the joint fingers 15a-15d belongs, and a wire 42 and an I/O type connection pad row 23a, 23b, 33a, 33b or a CA-type connection pad row 24a, Within 24b, 34a, 34b Any of the associated connection pads and the rewiring layer 28 are electrically connected to the pads of the I/O pad row 21, 31 or the CA pad rows 22, 32.

The terminal faces 13 are classified into two types according to the input and output systems of the pad rows 21, 22, 31, 32 of the semiconductor wafers 20, 30.

One is connected to the data (DQ) system signal and the DQ system power supply/GND, that is, the input/output type electrode pad (I/O type pad) 21, 31 I/O connection end face 13a, 13c.

The other is the CA junction end face 13b that is connected to the electrode pad (CA pad) column 22, 32 of the command address system.

The I/O connecting end faces 13a and 13c are disposed at both end portions of the electrode forming surface 10b as shown in Fig. 5 .

The I/O connection end faces 13a, 13c disposed at the respective ends are distributed to the semiconductor wafers 20, 30, respectively. In the present embodiment, as shown in FIG. 5, the upper end portion (first end portion) 11 is provided with an I/O connecting end surface 13a corresponding to the semiconductor wafer 20. In addition, as shown in FIG. 5, the lower end portion (second end portion) 12 is provided with an I/O connection end surface 13c corresponding to the semiconductor wafer 30. Further, a CA connecting end face 13b is disposed between the I/O connecting end faces 13a and 13c.

As shown in FIG. 4, the semiconductor wafer 20 is mounted on the wafer mounting surface 10a via a bonding member 41a such as a DAE (Die Attached Film) or an elastomer.

The semiconductor wafer 20 has a substantially rectangular plate shape as shown in FIGS. 6A and 7A. The semiconductor wafer 20 is a pad forming surface on one surface For example, 20a is formed with a memory circuit and a plurality of electrode pads.

Referring to Fig. 7A, the pad forming surface 20a is a side on which the long sides 25a, 25b opposed to each other are partitioned. The long side 25a is an example of the first side. The long side 25b is an example of the second side.

Referring to FIGS. 7A and 4, the pad forming surface 20a is formed with an I/O pad row 21, a CA pad row 22, an I/O pad pad row 23a and 23b, and a CA connection. Pad rows 24a and 24b, rewiring layer 28, and insulating layers 29a and 29b.

The pad (electrode) included in the I/O pad row 21 includes an electrode pad that is connected to the pad included in the I/O-based pad row 23a via the rewiring layer 28, and The rewiring layer 28 is connected to the electrode pads connected to the pads included in the pad row 23b of the I/O system.

Further, an insulating layer 29a is formed under the rewiring layer 28. On the rewiring layer 28, an insulating layer 29b is formed in addition to the pad portion.

The pad (electrode) included in the CA pad row 22 includes an electrode pad (for example, pad 22a) connected to the pad included in the CA-based pad row 24a via the rewiring layer 28. And an electrode pad (for example, pad 22b) connected to the pad included in the CA-based connection pad row 24b via the rewiring layer 28. Moreover, the pad 22a is an example of a 1st electrode. The pad 22b is an example of the second electrode.

The I/O pad row 21 and the CA pad row 22 are formed along a center line parallel to a pair of long sides 25a and 25b opposed to the rectangular semiconductor wafer 20 as shown in FIG. 7A. A straight line configuration in series. The I/O pad row 21 is disposed on the first end portion 26 side of the semiconductor wafer 20. The CA-based pad row 22 is disposed on the second end portion 27 side. Further, the I/O pad row 21 and the CA pad row 22 are included in the electrode group.

The I/O system connection pad row 23a and the CA system connection pad row 24a are arranged in series on the pad formation surface 20a so as to form a straight line along the long side 25a. The I/O-based connection pad row 23a is disposed on the first end portion 26 side of the semiconductor wafer 20. The CA-based connection pad row 24a is disposed on the second end portion 27 side. Further, the electrode pads (for example, the pads 24aa) included in the CA-based connection pad row 24a are examples of the third electrode.

The I/O system connection pad row 23b and the CA system connection pad row 24b are arranged in series on the pad formation surface 20a so as to form a straight line along the long side 25b. The I/O system connection pad row 23b is disposed on the first end portion 26 side. The CA-based connection pad row 24b is disposed on the second end portion 27 side. Further, the electrode pads (for example, the pads 24bb) included in the CA-based connection pad row 24b are examples of the fourth electrode.

The pad forming surface 20a other than the I/O-connecting pad rows 23a and 23b and the CA-based bonding pads 24a and 24b is formed with a passivation film (not shown) for protecting the pad forming surface 20a.

As shown in FIG. 6A, the semiconductor wafer 20 is placed on the wiring substrate 10 with the first end portion 26 of the semiconductor wafer 20 positioned on the first end portion 11 side of the wiring substrate 10. In other words, the semiconductor wafer 20 is used for the semiconductor wafer 20 disposed on the first end portion 11 of the wiring substrate 10 in the I/O-connecting pad rows 23a and 23b disposed at the first end portion 26 of the semiconductor wafer 20. The I/O connecting end face 13a and the joining finger row 15a are adjacent to each other. Set.

Each of the pads included in the I/O-type connection pad rows 23a and 23b of the semiconductor wafer 20 is individually and included in the bonding finger 15a by a conductive wiring 42 made of, for example, Au or Cu. The joints are electrically connected by finger lines.

Further, the bonding finger row 15a of the wafer mounting surface 10a is disposed along the two long sides of the wiring substrate 10 which are parallel to the direction in which the I/O pad row 21 of the semiconductor wafer 20 to be stacked is extended. Near the side. Further, the bonding finger array 15a is disposed on the first end portion 11 side of the wiring substrate 10.

The pads included in the CA-type connection pad rows 24a and 24b of the semiconductor wafer 20 are electrically connected to the bonding finger wires included in the bonding fingers 15b by the wires 42 individually.

In addition, the bonding finger row 15b of the wafer mounting surface 10a is disposed along the two long sides of the wiring substrate 10 which are parallel to the direction in which the I/O pad row 21 of the semiconductor wafer 20 to be stacked is extended. Near the side. Further, the bonding finger array 15b is disposed on the second end portion 12 side of the wiring substrate 10.

The semiconductor wafer 30 has the same configuration as the semiconductor wafer 20 except for the connection relationship between the pads included in the CA-based pad row and the pads included in the CA-type connection pad row (see FIG. 7A). , Figure 7B).

The semiconductor wafer 30 has a substantially rectangular plate shape as shown in FIG. 6B and FIG. 7B. For example, a memory circuit and a plurality of electrode pads are formed on the pad forming surface 30a of one surface of the semiconductor wafer 30.

The pad forming surface 30a is a long side 35a, 35b opposite to each other The side of the division. The long side 35a is an example of the first side. The long side 35b is an example of the second side.

The pad forming surface 30a is formed with an I/O pad row 31, a CA pad row 32, I/O-connected pad rows 33a and 33b, a CA-connecting pad row 34a and 34b, and a wiring. Layer 28, insulating layers 29a and 29b.

As shown in FIGS. 7A and 7B, the I/O pad row 31 of the semiconductor wafer 30, the CA pad array 32, the I/O type connection pad columns 33a and 33b, and the CA type connection pad columns 34a and 34b. The I/O type pad row 21, the CA type pad row 22, the I/O type connection pad row 23a and 23b, and the CA type connection pad rows 24a and 24b correspond to the semiconductor wafer 20, respectively.

In the semiconductor wafer 30, corresponding to the pads in the CA-type pad row 22 connected to the pads (for example, pads 24aa corresponding to CA1) in the CA-type connection pad row 24a of the semiconductor wafer 20 (corresponding to The pads (corresponding to the pads 32a of CA1) in the CA-type pad row 32 of the CA1 pad 22a) are connected to pads (corresponding to the pad 34bb of CA1) in the CA-type pad row 34b.

Further, in the semiconductor wafer 30, the pads in the CA-type pad row 22 connected to the pads in the CA-based pad row 24b of the semiconductor wafer 20 (for example, the pad 24bb corresponding to CA0) are connected (for example) The pads in the CA pad array 32 corresponding to the pad 22b of CA0 (corresponding to the pads 32b of CA0) are pads in the pad row 34a connected to the CA system (corresponding to pads 34aa of CA0) connection.

Further, the pad 32a corresponding to CA1 in the semiconductor wafer 30 is an example of the first electrode. The pad 35bb connected to the pad 32a is the fourth electric A very rare example. Further, the pad 32b corresponding to CA0 in the semiconductor wafer 30 is an example of the second electrode. The pad 34aa connected to the pad 32b is an example of the third electrode.

As described above, in the semiconductor wafers 20 and 30, in the pads in the CA-type pad row, the direction in which the rewiring layer 28 is pulled out forms an opposite direction.

As shown in FIG. 6B, the semiconductor wafer 30 is placed on the semiconductor wafer 20 with the first end portion 36 of the semiconductor wafer 30 positioned on the second end portion 12 side of the wiring substrate 10. In other words, the semiconductor wafer 30 is an I/O-based pad row 33a and 33b disposed on the first end portion 36 side and I/O for the semiconductor wafer 30 disposed on the second end portion 12 side of the wiring substrate 10. O is arranged such that the end faces 13c are adjacent to each other.

Between the semiconductor wafer 20 and the semiconductor wafer 30 is a FOW 41b in which an adhesive member is disposed. A part of the wiring 42 electrically connecting the semiconductor wafer 20 and the wiring substrate 10 is buried in the FOW 41b.

Each of the pads included in the I/O-based pad rows 33a, 33b of the semiconductor wafer 30 is electrically connected to the bonding finger line included in the bonding finger 15c by the wiring 42.

Further, the bonding finger 15c is formed on the wafer mounting surface 10a so as to be juxtaposed with the bonding finger 15b.

The pads included in the CA-type connection pad rows 34a, 34b of the semiconductor wafer 30 are electrically connected to the bonding finger wires included in the bonding fingers 15d by the wires 42 individually.

In addition, the joint finger 15d is a joint finger 15a, 15b The juxtaposition method is formed on the wafer mounting surface 10a.

8 is a view for explaining the connection of the CA0 bonding fingers 15b0 and the CA0 connecting end faces 13b0 in the bonding finger array 15b for the semiconductor wafer 20, and the CA0 bonding fingers 15d0 and the CA0 bonding end faces 13b0 in the bonding finger array 15d. Connected map.

In comparison with the connection relationship shown in FIG. 3, the semiconductor device 1 shown in FIG. 8 is a wiring for the bonding end 15b0 of CA0 and the end face 13b0 for CA0, and a wiring for the bonding end 15b0 of CA0 and the end face 13b0 for CA0. The difference in length will become smaller.

In addition, as shown in FIG. 4, the wafer mounting surface 10a of the wiring board 10 is formed with a sealing body 43 made of, for example, a thermosetting resin such as an epoxy resin. The semiconductor wafers 20 and 30 or the wires 42 are covered by the sealing body 43 and are protected from the outside.

As described above, the semiconductor device 1 of the present embodiment includes the substrate 10, the first semiconductor wafer 20 mounted on the substrate 10, and the second semiconductor wafer 30 laminated on the first semiconductor wafer 20.

The first and second semiconductor wafers 20, 30 each have a surface 20a, 30a which is defined by the first and second sides 25a, 25b, 35a, 35b facing each other; and a central field included in one side 20a, 30a. Electrode groups (21, 22), (31, 32) of the first and second electrodes 22a, 22b, 32a, 32b of the command address system arranged in parallel with the first sides 25a, 35a; along the first side 25a, 35a is disposed on the third electrodes 24aa, 34aa of one side 20a, 30a; and The fourth electrodes 24bb and 34bb are disposed on the surfaces 20a and 30a along the second sides 25b and 35b.

The first semiconductor wafer 20 is electrically connected to the third electrode 24aa of the first semiconductor wafer 20 by the first electrode 22a of the first semiconductor wafer 20, and the second electrode 22b of the first semiconductor wafer 20 is electrically connected to the first electrode The fourth electrode 24bb of the semiconductor wafer 20 is configured as described above.

The second semiconductor wafer 30 is electrically connected to the fourth electrode 34bb of the second semiconductor wafer 30 by the first electrode 32a of the second semiconductor wafer 30, and the second electrode 32b of the second semiconductor wafer 30 is electrically connected to the second electrode 32b. The third electrode 34aa of the semiconductor wafer 30 is configured such that the first side 35a of the second semiconductor wafer 30 is located on the second side 25b side of the first semiconductor wafer 20, and the second side 35b of the second semiconductor wafer 30 is located at the second side The semiconductor wafer 20 is stacked on the first semiconductor wafer 20 so as to be on the first side 25a side.

Therefore, the third electrode 24aa connected to the first electrode 22a of the semiconductor wafer 20 and the fourth electrode 35bb connected to the first electrode 32a of the semiconductor wafer 30 can be disposed on the first side 25a side of the semiconductor wafer 20. Further, the fourth electrode 24bb connected to the second electrode 22b of the semiconductor wafer 20 and the third electrode 34aa connected to the second electrode 32b of the semiconductor wafer 30 can be disposed on the second side 25b side of the semiconductor wafer 20.

Therefore, the difference in wiring length of the corresponding command address system of the semiconductor wafer above and below the substrate can be reduced.

Therefore, it is easy to adjust the variation of the operation timing due to the difference in wiring length, and the speed of the semiconductor device 1 can be increased.

Further, in the semiconductor device 1 of the present embodiment, the first The semiconductor wafer 20 is mounted on the substrate 10 such that the back surface of the one surface 20a of the first semiconductor wafer 20 faces the substrate 10, and the second semiconductor wafer 30 is the back side of the one surface 30a of the second semiconductor wafer 30. The surface is mounted on the first semiconductor wafer 20 so as to face the first semiconductor wafer 20.

Therefore, the first semiconductor wafer 20 and the second semiconductor wafer 30 can be stacked face up.

Next, a method of manufacturing the semiconductor device 1 of the present embodiment will be described with reference to Figs. 9A to 9F.

9A to 9F are cross-sectional views schematically showing respective processes of the method of manufacturing the semiconductor device 1 of the embodiment.

First, as shown in FIG. 9A, the wiring mother substrate 50 is prepared. The wiring mother substrate 50 used in the present embodiment is processed by a MAP (Mold Array Process) method. In the wiring mother substrate 50, a plurality of product forming portions 51 are arranged in a matrix.

The product forming portion 51 is a field in which the wiring board 10 is formed as described above after being cut and separated. A cutting line 52 is provided between the product forming portions 51. A frame portion (not shown) is provided around the product forming portion 51 arranged in a matrix. The frame portion is used for carrying the wiring mother substrate 50. Positioning positioning holes (not shown) are set at predetermined intervals.

Next, as shown in FIG. 9B, the semiconductor wafer 20 is bonded and fixed to the wiring mother via a DAF (Die Attached Film), for example, a tape member having an adhesive layer on both sides of the insulating substrate or an adhesive member 41a such as an elastic body. Each of the product forming portions 51 of the substrate 50.

At this time, the semiconductor wafer 20 is soldered to the semiconductor wafer 20. The surface on the back side of the pad forming surface 20a is disposed on the product forming portion 51 so as to face the product forming portion (wiring substrate) 51.

Then, the bonding fingers in the bonding pads 15a and 23b of the semiconductor wafer 20 and the bonding fingers in the bonding fingers 15a of the wiring substrate 10 are connected by the wires 42. Further, the bonding fingers in the bonding pads 15a and 24b of the CA-type connection pad rows 24a and 24b of the semiconductor wafer 20 and the bonding fingers 15b of the wiring substrate 10 are connected by the wires 42.

As described above, in the present embodiment, the wire bonding of the semiconductor wafer 20 is performed before the semiconductor wafer 30 is mounted on the pad forming surface 20a of the semiconductor wafer 20.

Then, as shown in FIG. 9C, the semiconductor wafer 30 is mounted on the pad forming surface 20a of the semiconductor wafer 20 via the bonding member 41b such as FOW, and the semiconductor wafer 20 and the semiconductor wafer 30 are laminated.

Further, in the same manner as the semiconductor wafer 20, the electrode pads of the semiconductor wafer 30 and the bonding fingers 15 formed in the vicinity of the boundary of the product forming portion 51 are connected by the wires 42. Further, the connection between the electrode pads of the wiring 42 and the bonding fingers 15 can be performed by reverse bonding in order to reduce the wire loop.

Next, as shown in FIG. 9D, a sealing body 43 made of an insulating resin that covers the wafer mounting surface 50a of the wiring mother substrate 50 is formed.

In this case, first, the wiring mother substrate 50 is molded to a molding die composed of, for example, an upper mold and a lower mold of a transfer molding device (not shown). Then, from the gate (not shown) to the upper mold and the lower mold A thermosetting epoxy resin is press-fitted into the cavity, and is thermally cured by filling the cavity with a resin, thereby forming a sealing body 43.

Then, as shown in FIG. 9E, conductive solder balls 17 made of solder or the like are mounted on a plurality of end faces 13 of the electrode forming surface 50b which are arranged in a lattice shape on the wiring mother substrate 50. In this Ball Mount project, a ball placement tool (not shown) that forms a plurality of adsorption holes is formed by using the arrangement of the joint end faces 13 on the wiring mother substrate 50. The solder ball 17 is held in the adsorption hole, and a flux is transferred and formed on the held solder ball 17 and then mounted on the connection end surface 13 of the wiring mother substrate 50. After the solder ball 17 is mounted, the solder ball 17 is fixed to the wiring mother substrate 50 by reflowing at a predetermined temperature. As a result, all of the mounted wiring mother substrates 50 of the solder balls 17 of the forward end faces 13 are sent to the substrate cutting process.

Next, as shown in FIG. 9F, the wiring mother substrate 50 is cut along the dicing line 52, and is separated for each product forming portion 51. In the substrate cutting process, first, the sealing body 43 of the wiring mother substrate 50 is adhered to a dicing tape (not shown), and the wiring mother substrate 50 is supported by a dicing tape. Then, the wiring mother substrate 50 is cut vertically and horizontally along the dicing line 52 by a dicing blade (not shown) to make the wiring mother substrate 50 small. After the die is finished, it is picked up from the dicing tape, whereby a DDP type semiconductor device as shown in FIG. 4 can be obtained.

(Second embodiment)

10A and 10B are views showing the use of the second embodiment of the present invention. A diagram of semiconductor wafers 20X and 30X of conductor device 1A. In Figs. 10A, 10B, the same reference numerals are attached to the same configurations as those shown in Figs. 7A, 7B.

11A and 11B are plan views schematically showing the semiconductor device 1A. 11A and 11B show the wafer mounting surface 10a side on which a plurality of bonding fingers 15 are formed. Fig. 11A also shows the connection relationship between the semiconductor wafer 20X on the lower side and the bonding fingers 15a, 15b. Fig. 11B also shows the connection relationship between the upper semiconductor wafer 30X and the bonding fingers 15c, 15d. In FIGS. 11A and 11B, the same configurations as those shown in FIGS. 6A and 6B are denoted by the same reference numerals.

In addition, in FIGS. 10A, 10B, 11A, and 11B, the insulating layer on the rewiring layer 28 is omitted.

In the semiconductor device 1 of the first embodiment, the pull-out direction of the rewiring layer of the corresponding pad (for example, the pad corresponding to CA0) in the CA-type pad row of the semiconductor wafers 20 and 30 is The semiconductor wafer 20 and the semiconductor wafer 30 are set in opposite directions.

On the other hand, in the semiconductor device 1A of the second embodiment, in addition to the pull-out direction of the rewiring layer of the corresponding pad in the CA-type pad row in the semiconductor wafers 20X and 30X, the I/O pad is used. The pull-out direction of the rewiring layer of the corresponding pad (for example, the pad corresponding to DQS) in the column is also set in the opposite direction to the semiconductor wafer 20X and the semiconductor wafer 30X.

Hereinafter, the semiconductor device 1A according to the second embodiment will be described focusing on a point different from the semiconductor device 1 of the first embodiment.

In FIG. 10A, FIG. 11A, the semiconductor wafer 20X is shown in FIG. The semiconductor wafer 20 shown in 7A has the same structure.

In FIG. 10B, FIG. 11B, in relation to the semiconductor wafer 30X, a pad (for example, a pad corresponding to DQS; a seventh electrode) connected to the I/O-based pad row 23a of the semiconductor wafer 20X is connected. The pad in the I/O pad row 21 (corresponding to the DQS pad; the fifth electrode) in the I/O pad row 31 (corresponding to the DQS pad; the fifth electrode) It is connected to a pad (corresponding to the DQS pad; the eighth electrode) in the I/O system connection pad row 33b of the semiconductor wafer 30X.

Further, in the semiconductor wafer 30X, I/O welding is performed in accordance with a pad (for example, a pad corresponding to DQSB; an eighth electrode) in the I/O-based pad row 23b of the semiconductor wafer 20X. A pad (corresponding to the DQSB pad; the sixth electrode) in the I/O pad row 31 of the pad (corresponding to the DQSB pad; the sixth electrode) in the pad row 21 is the semiconductor wafer 30X The pads in the I/O system connection pad row 33a (corresponding to the pads of the DQSB; the seventh electrode) are connected.

The fifth electrode, the sixth electrode is, for example, a pad corresponding to DQS, DQSB, DM (TDQS), TDQSB.

As described above, in the present embodiment, the electrode group further includes the fifth electrode and the sixth electrode in the I/O pad arrays 21, 31. The first and second semiconductor wafers 20X and 30X further have solder pads disposed in the I/O-connected pad rows 23a and 33a of the pad forming surfaces 20a and 30a along the first sides 25a and 35a. The seventh electrode) and the pads (the eighth electrode) in the I/O-connected pad rows 23b and 33b which are disposed on the pad forming surfaces 20a and 30a along the second sides 25b and 35b.

The first semiconductor wafer 20X is electrically connected to the seventh electrode of the first semiconductor wafer 20X via the fifth electrode of the first semiconductor wafer 20X, and the sixth electrode of the first semiconductor wafer 20X is electrically connected to the first semiconductor wafer 20X. The eighth electrode is constructed in a manner.

The second semiconductor wafer 30X is electrically connected to the eighth electrode of the second semiconductor wafer 30X via the fifth electrode of the second semiconductor wafer 30X, and the sixth electrode of the second semiconductor wafer 30X is electrically connected to the second semiconductor wafer 30X. The seventh electrode is constructed in a manner.

Therefore, it is possible to arrange the wafer pads, such as DQS, DQSB, DM (TDQS), and TDQSB, which are not compatible with the transfer of the I/O-based wafer pads, on the same side of the wiring substrate 10. Therefore, it is possible to increase the speed of the semiconductor device.

(Third embodiment)

12A and 12B are views showing semiconductor wafers 20Y and 30Y used in the semiconductor device 1B of the third embodiment of the present invention. In Figs. 12A and 12B, the same reference numerals are attached to the same configurations as those shown in Figs. 7A and 7B.

13A and 13B are plan views schematically showing the semiconductor device 1B. 13A and 13B show the wafer mounting surface side on which a plurality of bonding fingers 15 are formed. Fig. 13A also shows the connection relationship between the semiconductor wafer 20Y on the lower side and the bonding fingers 15a, 15b. Fig. 13B also shows the connection relationship between the upper semiconductor wafer 30Y and the bonding fingers 15c, 15d. In Figs. 13A and 13B, the same reference numerals are attached to the configurations similar to those shown in Figs. 6A and 6B.

In addition, in FIGS. 12A, 12B, 13A, and 13B, the insulating layer on the rewiring layer 28 is omitted.

The semiconductor wafers 20Y and 30Y have the same configuration.

A switching circuit 60 as shown in FIG. 14 is formed in the semiconductor wafers 20Y and 30Y.

In FIG. 14, the switching circuit 60 is an example of a setting circuit. The switching circuit 60 includes receiving units 61 and 62 and selectors 63 and 64.

First, the switching circuit 60 relating to the semiconductor wafer 20Y will be described.

The switching circuit 60 is a number that sets half of the number of pads in the CA-based pad row 22. The switching circuit 60 is a bonding pad (first electrode) and a CA-based connection pad row 24b in the CA-type pad row 22 connected to the pad (third electrode) in the CA-based connection pad row 24a. One of the pads (second electrodes) in the CA-type pad row 22 connected to the inner pad (fourth electrode) is provided in combination.

In the present embodiment, the pads in the CA-type pad row 22 are divided into two pad units arranged in the direction in which the pads are arranged, and the switching circuit 60 is provided for each of the two pads.

In the semiconductor wafer 20Y, the receiving portion 61 receives a signal from one pad (first electrode) in the CA-type pad row 22 connected to the pad (third electrode) in the CA-based pad row 24a. Further, the receiving unit 62 receives a signal from one pad (second electrode) in the CA-type pad row 22 connected to the pad (fourth electrode) in the CA-based connection pad row 24b.

Once the receiving unit 61 receives the signal, the signal is output to Selectors 63 and 64. Further, when the receiving unit 62 receives the signal, the signal is output to the selectors 63 and 64.

The output of the selector 63 is connected to an input portion 81 for inputting a signal into the semiconductor wafer 20Y. The output of selector 64 is coupled to input portion 82 for inputting signals into semiconductor wafer 20Y.

The selectors 63 and 64 are also accepted, for example, depending on whether or not the fuse in the fuse circuit (not shown) is turned off, and the MF signal whose signal level is switched between "0" and "1" is also accepted.

When the MF signal is "0", the selector 63 outputs the signal from the accepting unit 61 to the input unit 81, and the selector 64 outputs the signal from the accepting unit 62 to the input unit 82.

Further, when the MF signal is "1", the selector 63 outputs the signal from the accepting unit 62 to the input unit 81, and the selector 64 outputs the signal from the accepting unit 61 to the input unit 82.

Next, the switching circuit 60 relating to the semiconductor wafer 30Y will be described.

The switching circuit 60 is a number that sets half of the number of pads in the CA-based pad row 22. The switching circuit 60 is a bonding pad (first electrode) and a CA-based connection pad row 34b in the CA-type pad row 32 connected to the pad (third electrode) in the CA-based connection pad row 34a. One of the pads (second electrodes) in the CA-type pad row 32 to which the inner pads (fourth electrodes) are connected is provided in combination.

In this embodiment, the pads in the CA pad array 32 are divided into two pad units arranged in the direction in which the pads are arranged, and the switching circuit 60 will One set of each of the two pads is provided.

In the semiconductor wafer 30Y, the receiving portion 61 receives the signal from the pad (first electrode) in the CA-type pad row 32 connected to the pad (third electrode) in the CA-based pad row 34a. Further, the receiving unit 62 receives the signal from the pad (second electrode) in the CA-type pad row 32 connected to the pad (fourth electrode) in the CA-based pad row 34b.

The output of the selector 63 is connected to an input for inputting signals into the semiconductor wafer 30Y. The output of selector 64 is coupled to an input for inputting signals into semiconductor wafer 30Y.

Further, since the operations of the selectors 63, 64 in the semiconductor wafer 30Y corresponding to the value of the MF signal are operations of the semiconductor wafer 20Y, the description thereof is omitted.

As described above, the semiconductor device 1B of the present embodiment includes the substrate 10, the first semiconductor wafer 20Y mounted on the substrate 10, and the second semiconductor wafer 30Y stacked on the first semiconductor wafer 20Y.

Each of the first and second semiconductor wafers 20Y and 30Y has one surface 20a, 30a partitioned by the first and second sides 25a, 25b, 35a, 35b facing each other, and a central field included in one surface 20a, 30a. Electrode groups (21, 22), (31, 32) of the first and second electrodes 22a, 22b, 32a, 32b of the command address system arranged in parallel with the first sides 25a, 35a; along the first side 25a, 35a is disposed on the third electrodes 24aa, 34aa of one surface 20a, 30a; and is disposed on the fourth electrode of one surface 20a, 30a along the second sides 25b, 35b 24bb, 35bb; first and second input units 81, 82; and alternatively, a first connection state in which the first electrode is connected to the first input unit 81 and the second electrode is connected to the second input unit 82. And a switching circuit 60 that connects the first electrode to the second input unit 82 and connects the second electrode to the second connection state of the first input unit 81.

The first semiconductor wafer 20Y is electrically connected to the third electrode 24aa of the first semiconductor wafer 20Y by the first electrode 22a of the first semiconductor wafer 20Y, and the second electrode 22b of the first semiconductor wafer 20Y is electrically connected to the first electrode The fourth electrode 24bb of the semiconductor wafer 20Y is configured as described above.

The second semiconductor wafer 30Y is electrically connected to the third electrode 34aa of the second semiconductor wafer 30Y by the first electrode 32a of the second semiconductor wafer 30Y, and the second electrode 32b of the second semiconductor wafer 30Y is electrically connected to the second electrode 32a. The fourth electrode 35bb of the semiconductor wafer 30Y is configured such that the first side 35a of the second semiconductor wafer 30Y is located on the second side 25b side of the first semiconductor wafer 20Y, and the second side 35b of the second semiconductor wafer 30Y is located at the second side 35b. The semiconductor wafer 20Y is stacked on the first semiconductor wafer 20Y so as to be on the first side 25a side.

Therefore, in the second semiconductor wafer 30Y and the second semiconductor wafer 30Y, the first connection state and the second connection state are appropriately set by using the switching circuit 60, and as in the first embodiment, the upper and lower sides on the substrate can be reduced. The difference in wiring length of the corresponding command address of the semiconductor wafer.

Therefore, it is easy to adjust the variation of the operation timing due to the difference in wiring length, and the speed of the semiconductor device 1 can be increased.

Further, in the third embodiment, the semiconductor is formed on the upper and lower sides. The rewiring layers of the bulk wafers 20, 30 have the same configuration. Therefore, the semiconductor wafer prepared as the upper and lower semiconductor wafers is completed in one type, and the cost can be reduced.

The present invention has been described above with reference to the embodiments. However, the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit and scope of the invention.

For example, in the above embodiment, the rewiring of the pad is performed by providing a rewiring layer on the semiconductor wafer. However, the sub wiring substrate may be mounted on the semiconductor wafer to rewire the pad.

For example, in the first and second embodiments, the first electrodes of the semiconductor wafers 20 and 20X are electrically connected to the third electrodes of the semiconductor wafers 20 and 20X, and the second electrodes of the semiconductor wafers 20 and 20X and the semiconductor wafer 20 are electrically connected. The fourth electrode of 20X is electrically connected, the first electrode of the semiconductor wafer 30, 30X is electrically connected to the fourth electrode of the semiconductor wafer 30, 30X, and the second electrode of the semiconductor wafer 30, 30X and the semiconductor wafer 30, 30X Among the electrical connections of the third electrodes, at least one of the connections may be performed via a rewiring layer or a wiring board.

Further, in the third embodiment, the first electrode of the semiconductor wafer 20Y is electrically connected to the third electrode of the semiconductor wafer 20Y, and the second electrode of the semiconductor wafer 20Y is electrically connected to the fourth electrode of the semiconductor wafer 20Y. The first electrode of the wafer 30Y is electrically connected to the fourth electrode of the semiconductor wafer 30Y, and at least one of the second electrode of the semiconductor wafer 30Y and the third electrode of the semiconductor wafer 30Y is electrically connected. This can be done via a rewiring layer or a wiring substrate.

Further, in each of the above-described embodiments, the semiconductor wafer is a semiconductor wafer in which a plurality of electrode pads are arranged in one central region, but a plurality of electrode pads may be applied to two or more columns in one central region. Semiconductor wafer.

For example, in the semiconductor wafer, a plurality of electrode rows arranged in parallel with the first side may be formed by electrodes included in the electrode group.

The present invention will be described with reference to the embodiments, but the invention is not limited to the above embodiments. The configuration or the details of the invention of the present invention are such that various modifications can be made by those skilled in the art within the scope of the invention. The application is based on the priority of Japanese Patent Application No. 2012-275624, filed on Dec.

10‧‧‧Wiring substrate

10a‧‧‧ wafer mounting surface

11‧‧‧1st end

12‧‧‧2nd end

15a~15d‧‧‧Joining

15b0‧‧‧ joint finger

20‧‧‧Semiconductor wafer

20a‧‧‧pad forming surface

21‧‧‧I/O solder pad column

22‧‧‧CA welding pad column

23a, 23b‧‧‧I/O system connection pad column

24a, 24b‧‧‧CA connection pad row

26‧‧‧1st end

28‧‧‧Rewiring layer

42‧‧‧ wiring

Claims (7)

A semiconductor device characterized by comprising: a substrate; and a first semiconductor wafer mounted on the substrate; and a second semiconductor wafer laminated on the first semiconductor wafer, wherein the first and second semiconductor wafers each have: a surface of the first and second electrodes including the first and second sides facing each other; and an electrode group of the first and second electrodes of the command address system arranged in parallel with the first side in the central region of the one surface; a third electrode disposed on the one side and a fourth electrode disposed on the one surface along the second side, wherein the first semiconductor wafer is electrically connected to the first electrode of the first semiconductor wafer The third electrode connected to the first semiconductor wafer, wherein the second electrode of the first semiconductor wafer is electrically connected to the fourth electrode of the first semiconductor wafer, and the second semiconductor wafer is configured as described above The first electrode of the second semiconductor wafer is electrically connected to the fourth electrode of the second semiconductor wafer, and the second electrode of the second semiconductor wafer is electrically connected to the second semiconductor The third electrode of the wafer is configured such that the first side of the second semiconductor wafer is located on the second side of the first semiconductor wafer, and the second side of the second semiconductor wafer is located in the first side The first side of the semiconductor wafer is laminated on the first semiconductor wafer. The semiconductor device according to claim 1, wherein the electrode group further includes: a central region on the one surface and the first side The fifth and sixth electrodes for data output and output in parallel, wherein the first and second semiconductor wafers each have a seventh electrode disposed on the one surface along the first side; and along the second side The eighth electrode disposed on the one surface, wherein the first semiconductor wafer is electrically connected to the seventh electrode of the first semiconductor wafer to the seventh electrode of the first semiconductor wafer, and the first semiconductor wafer is The sixth electrode is electrically connected to the eighth electrode of the first semiconductor wafer, and the second semiconductor wafer is electrically connected to the second semiconductor wafer by the fifth electrode of the second semiconductor wafer. In the eighth electrode, the sixth electrode of the second semiconductor wafer is electrically connected to the seventh electrode of the second semiconductor wafer. The semiconductor device according to claim 1 or 2, wherein the first electrode of the first semiconductor wafer is electrically connected to the third electrode of the first semiconductor wafer, and the second electrode of the first semiconductor wafer The electrode is electrically connected to the fourth electrode of the first semiconductor wafer, the first electrode of the second semiconductor wafer is electrically connected to the fourth electrode of the second semiconductor wafer, and the second semiconductor wafer is electrically connected At least one of the electrical connection between the second electrode and the third electrode of the second semiconductor wafer is performed via a rewiring layer or a wiring substrate. A semiconductor device characterized by comprising: a substrate; and a first semiconductor wafer mounted on the substrate; and a second semiconductor wafer laminated on the first semiconductor wafer Each of the first and second semiconductor wafers has a surface that is defined by the first and second sides facing each other, and a command address system that is disposed in parallel with the first side in a central region of the one surface. And an electrode group of the second electrode; a third electrode disposed on the one surface along the first side; and a fourth electrode disposed on the one surface along the second side; for inputting a signal into the self-wafer And the first and second input units; and the first connection state in which the first electrode is connected to the first input unit and the second electrode is connected to the second input unit, and the a first electrode connected to the second input unit and connected to the second connection state of the first input unit, wherein the first semiconductor wafer is formed by the first electrode of the first semiconductor wafer Electrically connecting to the third electrode of the first semiconductor wafer, wherein the second electrode of the first semiconductor wafer is electrically connected to the fourth electrode of the first semiconductor wafer, and the second semiconductor wafer is configured The aforementioned second semiconductor The first electrode of the wafer is electrically connected to the third electrode of the second semiconductor wafer, and the second electrode of the second semiconductor wafer is electrically connected to the fourth electrode of the second semiconductor wafer. The first side of the second semiconductor wafer is located on the second side of the first semiconductor wafer, and the second side of the second semiconductor wafer is located on the first side of the first semiconductor wafer. Way cascading On the first semiconductor wafer. The semiconductor device according to claim 4, wherein the first electrode of the first semiconductor wafer and the third electrode of the first semiconductor wafer are electrically connected to each other, and the second electrode of the first semiconductor wafer and Electrical connection between the fourth electrode of the first semiconductor wafer, electrical connection between the first electrode of the second semiconductor wafer and the third electrode of the second semiconductor wafer, and the first of the second semiconductor wafer Among the electrical connection between the two electrodes and the fourth electrode of the second semiconductor wafer, at least one of the connections is performed via a rewiring layer or a wiring substrate. The semiconductor device according to any one of claims 1 to 5, wherein the electrode array included in the electrode group forms a plurality of electrode rows arranged in parallel with the first side. The semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor wafer is such that a surface on a back side of the one surface of the first semiconductor wafer faces the substrate The second semiconductor wafer is mounted on the first semiconductor wafer so that the back surface of the one surface of the second semiconductor wafer faces the first semiconductor wafer.