JP2010278334A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010278334A
JP2010278334A JP2009130945A JP2009130945A JP2010278334A JP 2010278334 A JP2010278334 A JP 2010278334A JP 2009130945 A JP2009130945 A JP 2009130945A JP 2009130945 A JP2009130945 A JP 2009130945A JP 2010278334 A JP2010278334 A JP 2010278334A
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semiconductor
pad
interposer substrate
pads
semiconductor element
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Emi Sawayama
絵美 澤山
Masahiro Yamaguchi
昌浩 山口
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device in a multi-chip package form by layering semiconductor elements having pads disposed at plane positions different from each other. <P>SOLUTION: A semiconductor device 1 includes a plurality of semiconductor elements 2, 3 and an interposer substrate 14 interposed between the semiconductor elements 2, 3. On one surface of the interposer substrate 14, a pad 15 is formed which is disposed at a plane position matched to a plane position of a pad 8a of the semiconductor element 2 positioned on the one surface. On the other surface of the interposer substrate 14, a pad 16 is formed which is disposed at a plane position matched to a plane position of a pad 12 of the semiconductor element 3 positioned on the other surface. The pad 15 formed on the one surface and the pad 16 formed on the other surface are connected to each other in the interposer substrate 14. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

種類の異なる複数の半導体素子を積層して構成したマルチチップパッケージ（ＭＣＰ）の形態の従来の半導体装置が、特許文献１に開示されている。この半導体装置は、貫通ビア（ＴＳＶ）を有する複数の半導体基板（メモリコアチップ）が積層された半導体素子と、貫通ビアを有していない単層の半導体基板（インターフェースチップ）からなる半導体素子とが積層された構成である。この２種類の半導体素子は、平面的に見て、それぞれの表面に設けられた接続用のパッドの位置が一致しているため、直接積層して良好な電気接続を実現することができる。なお、本明細書中では、平面的に見たときの位置を「平面位置」という。   A conventional semiconductor device in the form of a multichip package (MCP) configured by stacking a plurality of different types of semiconductor elements is disclosed in Patent Document 1. This semiconductor device includes a semiconductor element in which a plurality of semiconductor substrates (memory core chips) having through vias (TSV) are stacked, and a semiconductor element made of a single layer semiconductor substrate (interface chip) having no through vias. It is a laminated structure. Since these two types of semiconductor elements have the same positions of connection pads provided on the respective surfaces in plan view, they can be directly stacked to achieve good electrical connection. In the present specification, a position when viewed in a plane is referred to as a “planar position”.

特開２００６−３０１８６３号JP 2006-301863 A

前記したように、特許文献１に記載された構成では、互いに積層される半導体素子のパッドの平面位置が一致しているため、それらの半導体素子を積層してマルチチップパッケージの形態の半導体装置を容易に製造することができる。   As described above, in the configuration described in Patent Document 1, since the planar positions of the pads of the semiconductor elements stacked on each other coincide with each other, the semiconductor elements are stacked to form a semiconductor device in the form of a multichip package. It can be manufactured easily.

しかし、互いに異なる平面位置に配置されたパッドを有する半導体素子同士を積層してマルチチップパッケージの形態の半導体装置を製造することは困難である。   However, it is difficult to manufacture a semiconductor device in the form of a multichip package by stacking semiconductor elements having pads arranged at different planar positions.

このことは、必ずしもパッドの平面位置が一致していない可能性がある、予め作製された複数の半導体素子同士を任意に積層して半導体装置を製造する上での妨げとなる。   This obstructs the manufacture of a semiconductor device by arbitrarily stacking a plurality of semiconductor elements prepared in advance, which may not necessarily match the planar positions of the pads.

実際には、複数の半導体素子を積層してマルチチップパッケージの形態の半導体装置を製造する場合には、一方の半導体素子の表面に形成するパッドを、他方の半導体素子の表面に形成されたパッドと同じ平面位置になるようにその都度設計を行って作製している。   Actually, when a semiconductor device in the form of a multichip package is manufactured by stacking a plurality of semiconductor elements, a pad formed on the surface of one semiconductor element is replaced with a pad formed on the surface of the other semiconductor element. The design is made each time so that it is in the same plane position.

すなわち、いわばオーダーメイド式に半導体素子の作製を行うのが一般的であり、パッドの平面位置が共通化されていない予め作製された複数種類の半導体素子を様々に組み合わせて多様な半導体装置を製造することや、１種類の半導体素子を広く使い回して様々な半導体素子と組み合わせて多様な半導体装置を製造することは、従来ほとんど行われていない。その結果、半導体装置の製造効率が悪く製造コストが高くなっている。   In other words, it is common to produce semiconductor elements in a custom-made manner, and various semiconductor devices are manufactured by combining various types of semiconductor elements that have been prepared in advance, where the planar positions of the pads are not shared. In the past, it has been rarely used to manufacture various semiconductor devices by combining a variety of semiconductor elements by widely using one type of semiconductor element. As a result, the manufacturing efficiency of the semiconductor device is poor and the manufacturing cost is high.

本発明の半導体装置は、複数の半導体素子と、半導体素子の間に介在するインターポーザ基板とを有している。そして、インターポーザ基板の一方の面には、該一方の面上に位置する半導体素子のパッドの平面位置に一致する平面位置に配置されたパッドが形成されており、インターポーザ基板の他方の面には、該他方の面上に位置する半導体素子のパッドの平面位置に一致する平面位置に配置されたパッドが形成されている。一方の面に形成されたパッドと他方の面に形成されたパッドとは、インターポーザ基板の内部で接続されている。   The semiconductor device of the present invention has a plurality of semiconductor elements and an interposer substrate interposed between the semiconductor elements. And on one surface of the interposer substrate, there is formed a pad arranged at a planar position that matches the planar position of the pad of the semiconductor element located on the one surface, and on the other surface of the interposer substrate A pad arranged at a planar position that coincides with the planar position of the pad of the semiconductor element located on the other surface is formed. The pad formed on one surface and the pad formed on the other surface are connected inside the interposer substrate.

この構成によると、インターポーザ基板の両面に形成された、互いに平面位置が異なるパッドが、インターポーザ基板の内部で接続されているため、インターポーザ基板がパッドの平面位置を調整する働きをする。従って、このインターポーザ基板を介在させることにより、互いに異なる平面位置に配置されたパッドを有する半導体基板同士を積層しても両半導体素子の電気接続を確保することができ、両半導体素子からなる半導体装置を良好に機能させることができる。   According to this configuration, since the pads formed on both surfaces of the interposer substrate and having different planar positions are connected inside the interposer substrate, the interposer substrate functions to adjust the planar position of the pads. Therefore, by interposing this interposer substrate, even if semiconductor substrates having pads arranged at different planar positions are stacked, electrical connection between both semiconductor elements can be secured, and a semiconductor device comprising both semiconductor elements Can function well.

本発明によると、パッドの平面位置が異なる半導体素子同士を、インターポーザ基板を介して重ね合わせることにより、容易に半導体装置を製造することができる。従って、予め作製しておいた半導体素子を様々に組み合わせて多様な半導体装置を製造することが容易に可能であり、半導体装置を製造するたびに半導体素子をその都度オーダーメイド式に設計および作製する必要がないため、高効率化および低コスト化に寄与する。   According to the present invention, a semiconductor device can be easily manufactured by superimposing semiconductor elements having different pad planar positions via an interposer substrate. Therefore, it is possible to easily manufacture various semiconductor devices by combining various semiconductor elements prepared in advance. Each time a semiconductor device is manufactured, the semiconductor elements are designed and manufactured in a custom-made manner. This is unnecessary, contributing to higher efficiency and lower costs.

本発明の一実施形態の半導体装置の断面図である。It is sectional drawing of the semiconductor device of one Embodiment of this invention. 図１に示す半導体素子の製造方法の一工程を説明するための断面図である。It is sectional drawing for demonstrating 1 process of the manufacturing method of the semiconductor element shown in FIG. 図１に示す半導体素子の製造方法の、図２に示す工程に続く工程を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a step following the step shown in FIG. 2 in the method for manufacturing the semiconductor element shown in FIG. 1. 図１に示す半導体素子の製造方法の、図３に示す工程に続く工程を説明するための断面図である。FIG. 4 is a cross-sectional view for explaining a step following the step shown in FIG. 3 in the method for manufacturing the semiconductor element shown in FIG. 1. 図１に示す半導体素子の製造方法の、図４に示す工程に続く工程を説明するための断面図である。FIG. 5 is a cross-sectional view for explaining a step following the step shown in FIG. 4 in the method for manufacturing the semiconductor element shown in FIG. 1. 本発明の他の実施形態の半導体装置の断面図である。It is sectional drawing of the semiconductor device of other embodiment of this invention.

以下、本発明の実施の形態について説明する。   Embodiments of the present invention will be described below.

図１に示す本発明の半導体装置１は、いわゆるマルチチップパッケージ（ＭＣＰ）の形態であり、複数の半導体素子２，３が間接的に積層された構造である。   A semiconductor device 1 of the present invention shown in FIG. 1 is in the form of a so-called multichip package (MCP), and has a structure in which a plurality of semiconductor elements 2 and 3 are indirectly stacked.

半導体素子２は、シリコン基板に半導体が作り込まれた複数の半導体基板４ａ〜４ｄが積層された構成である。各半導体基板４ａ〜４ｄはそれぞれ一方の面に複数のパッド９ａ〜９ｄが設けられており、このパッド９ａ〜９ｄを除いて、ポリイミドなどの樹脂層５ａ〜５ｄによって覆われて保護されている。そして、パッド９ａ〜９ｄ上に接続用のバンプ６ａ〜６ｄが設けられている。各半導体基板４ａ〜４ｄの内部には、板厚方向に貫通するスルーホール内に銅などの金属が埋め込まれた構成の貫通ビア（ＴＳＶ）７ａ〜７ｄが設けられている。各貫通ビア７ａ〜７ｄは、各パッド９ａ〜９ｄに平面的に重なる位置に配置されて直接接触している。また、各半導体基板４ａ〜４ｄの他方の面、すなわちパッド９ａ〜９ｄおよび樹脂層５ａ〜５ｄが形成されていない面に、各貫通ビア７ａ〜７ｄと一体化された、各貫通ビア７ａ〜７ｄよりも大面積のパッド８ａ〜８ｄが設けられている。各半導体基板４ａ〜４ｄの、パッド９ａ〜９ｄと、バンプ６ａ〜６ｄと、貫通ビア７ａ〜７ｄと、パッド８ａ〜８ｄの平面位置は全て一致している。この半導体素子２の、各半導体基板４ａ〜４ｄの間の隙間やそれらの外側のスペースは、樹脂１０ａによって埋められている。   The semiconductor element 2 has a configuration in which a plurality of semiconductor substrates 4a to 4d in which a semiconductor is formed on a silicon substrate are stacked. Each of the semiconductor substrates 4a to 4d is provided with a plurality of pads 9a to 9d on one surface, and except for the pads 9a to 9d, they are covered and protected by resin layers 5a to 5d such as polyimide. Then, bumps 6a to 6d for connection are provided on the pads 9a to 9d. Inside each of the semiconductor substrates 4a to 4d, through vias (TSV) 7a to 7d having a structure in which a metal such as copper is embedded in a through hole penetrating in the plate thickness direction are provided. The through vias 7a to 7d are arranged at positions that overlap the pads 9a to 9d in plan and are in direct contact with each other. The through vias 7a to 7d integrated with the through vias 7a to 7d on the other surfaces of the semiconductor substrates 4a to 4d, that is, the surfaces where the pads 9a to 9d and the resin layers 5a to 5d are not formed. Larger pads 8a to 8d are provided. The planar positions of the pads 9a to 9d, the bumps 6a to 6d, the through vias 7a to 7d, and the pads 8a to 8d of the semiconductor substrates 4a to 4d are all the same. The gap between the semiconductor substrates 4a to 4d and the outer space of the semiconductor element 2 are filled with the resin 10a.

もう１つの半導体素子３は、シリコン基板に半導体が作り込まれた単一の半導体基板１１からなる。半導体基板１１は一方の面に複数のパッド１２が設けられ、さらにパッド１２上に接続用のバンプ１３が形成されている。   Another semiconductor element 3 includes a single semiconductor substrate 11 in which a semiconductor is formed on a silicon substrate. The semiconductor substrate 11 is provided with a plurality of pads 12 on one surface, and further, bumps 13 for connection are formed on the pads 12.

半導体素子３の半導体基板１１の面内のパッド１２の平面位置は、半導体素子２の半導体基板４ａ〜４ｄのパッド９ａ〜９ｄ、バンプ６ａ〜６ｄ、貫通ビア７ａ〜７ｄ、およびパッド８ａ〜８ｄの平面位置と異なっている。特に、本実施形態の場合、半導体素子３の半導体基板１１のパッド１２のピッチと、半導体素子２の半導体基板４ａ〜４ｄのパッド９ａ〜９ｄおよびパッド８ａ〜８ｄのピッチが異なっている。この半導体素子３は貫通ビア（ＴＳＶ）を有していない。   The planar positions of the pads 12 in the plane of the semiconductor substrate 11 of the semiconductor element 3 are the pads 9a to 9d, the bumps 6a to 6d, the through vias 7a to 7d, and the pads 8a to 8d of the semiconductor substrates 4a to 4d of the semiconductor element 2. It is different from the plane position. In particular, in the present embodiment, the pitch of the pads 12 of the semiconductor substrate 11 of the semiconductor element 3 is different from the pitches of the pads 9a to 9d and the pads 8a to 8d of the semiconductor substrates 4a to 4d of the semiconductor element 2. The semiconductor element 3 does not have a through via (TSV).

本実施形態の半導体装置１においては、半導体素子２と半導体素子３の間にインターポーザ基板１４が介在している。このインターポーザ基板１４の一方の面の、半導体素子２の半導体基板４ａ〜４ｄのパッド９ａ〜９ｄおよびパッド８ａ〜８ｄと対向する平面位置に、パッド１５が設けられている。また、インターポーザ基板１４の他方の面の、半導体素子３の半導体基板１１のパッド１２と対向する平面位置に、パッド１６が設けられている。そして、図１に示すように、各パッド１５と各パッド１６はインターポーザ基板１４の内部配線２４によりそれぞれ接続されている。ただし、パッド１５，１６が設けられている個数によっては、インターポーザ基板１４の内部で接続されていないパッド１５および／またはパッド１６が存在する場合もある。また、インターポーザ基板１４の一方の面上には、半導体素子２に対向する部分の外側に、後述する有機基板１８のパッド１９に接続されるパッド１７が設けられている。そして、インターポーザ基板１４と半導体素子２の半導体基板４ａとの接合部分は樹脂１０ｂによって封止されており、インターポーザ基板１４と半導体素子３の半導体基板１１との接合部分は樹脂１０ｃによって封止されている。   In the semiconductor device 1 of the present embodiment, an interposer substrate 14 is interposed between the semiconductor element 2 and the semiconductor element 3. A pad 15 is provided on one surface of the interposer substrate 14 at a planar position facing the pads 9a to 9d and the pads 8a to 8d of the semiconductor substrates 4a to 4d of the semiconductor element 2. A pad 16 is provided on the other surface of the interposer substrate 14 at a planar position facing the pad 12 of the semiconductor substrate 11 of the semiconductor element 3. As shown in FIG. 1, each pad 15 and each pad 16 are connected by an internal wiring 24 of the interposer substrate 14. However, depending on the number of pads 15, 16, there may be pads 15 and / or pads 16 that are not connected inside the interposer substrate 14. Further, on one surface of the interposer substrate 14, a pad 17 connected to a pad 19 of an organic substrate 18 described later is provided outside a portion facing the semiconductor element 2. The joint portion between the interposer substrate 14 and the semiconductor substrate 4a of the semiconductor element 2 is sealed with the resin 10b, and the joint portion between the interposer substrate 14 and the semiconductor substrate 11 with the semiconductor element 3 is sealed with the resin 10c. Yes.

半導体装置１は、半導体素子２とインターポーザ基板１４と半導体素子３とからなる積層体を支持する有機基板（実装基板、パッケージ基板とも言う）１８をさらに有している。この有機基板１８の、半導体素子２とインターポーザ基板１４と半導体素子３とからなる積層体を支持する面上であって、この積層体に対向する部分の外側に、パッド１９が設けられている。そして、インターポーザ基板１４のパッド１７と、有機基板１８のパッド１９とが、ボンディングワイヤ２０によって接続（ワイヤボンディング）されている。また、有機基板１８の、積層体を支持する面と反対側の面に複数のボールパッド２１が設けられ、これらのボールパッド２１上にそれぞれはんだボール２２が固定されている。そして、有機基板１８内部には、各パッド１９と各ボールパッド２１および各はんだボール２２とを接続する内部配線２３が設けられている。なお、図面中では、切断線との位置関係に基づいて、はんだボール２２およびボールパッド２１のみが図示されていて、それらに対応する内部配線２３およびパッド１９と、さらにそれらに接続されるボンディングワイヤ２０およびパッド１７が図示されていない箇所もある。有機基板１８上で支持される半導体素子２とインターポーザ基板１４と半導体素子３とからなる積層体の外側は、樹脂１０ｄによって封止されている。   The semiconductor device 1 further includes an organic substrate (also referred to as a mounting substrate or a package substrate) 18 that supports a stacked body including the semiconductor element 2, the interposer substrate 14, and the semiconductor element 3. A pad 19 is provided on the surface of the organic substrate 18 that supports the laminated body including the semiconductor element 2, the interposer substrate 14, and the semiconductor element 3, and outside the portion facing the laminated body. The pads 17 of the interposer substrate 14 and the pads 19 of the organic substrate 18 are connected (wire bonding) by bonding wires 20. In addition, a plurality of ball pads 21 are provided on the surface of the organic substrate 18 opposite to the surface that supports the laminated body, and solder balls 22 are respectively fixed on these ball pads 21. In the organic substrate 18, internal wiring 23 that connects each pad 19, each ball pad 21, and each solder ball 22 is provided. In the drawing, only the solder ball 22 and the ball pad 21 are shown based on the positional relationship with the cutting line, the internal wiring 23 and the pad 19 corresponding to them, and bonding wires connected to them. In some places, 20 and pads 17 are not shown. The outer side of the laminate composed of the semiconductor element 2, the interposer substrate 14 and the semiconductor element 3 supported on the organic substrate 18 is sealed with a resin 10d.

半導体装置１は、以上説明した各構成要素からなるものであり、具体的には、有機基板１８の、はんだボール２２およびボールパッド２１が形成されている面と反対側の面上に、半導体素子３、インターポーザ基板１４、半導体素子２が順番に積層された構成である。各構成要素間の隙間や各構成要素の外側のスペースが樹脂１０ａ〜１０ｄで封止されることによって、各構成要素は固定されている。なお、樹脂１０ａ〜１０ｄは全て同じ樹脂材料であってよく、その場合、各樹脂１０ａ〜１０ｄは一体化して境界がなくなっている場合もある。ただし、後述する半導体の製造過程において各樹脂１０ａ〜１０ｄが供給されるタイミングがそれぞれ異なるため、本明細書および図面中では各樹脂１０ａ〜１０ｄを区別して表現している。   The semiconductor device 1 includes the components described above. Specifically, the semiconductor device 1 is formed on the surface of the organic substrate 18 opposite to the surface on which the solder balls 22 and the ball pads 21 are formed. 3, the interposer substrate 14 and the semiconductor element 2 are stacked in order. Each component is fixed by sealing a gap between each component or a space outside each component with the resins 10a to 10d. The resins 10a to 10d may all be the same resin material. In that case, the resins 10a to 10d may be integrated to have no boundary. However, since the timings at which the resins 10a to 10d are supplied in the semiconductor manufacturing process to be described later are different, the resins 10a to 10d are distinguished from each other in this specification and the drawings.

本実施形態では、半導体素子２，３、インターポーザ基板１４、および有機基板１８のそれぞれのパッドやビアや内部配線等はニッケル／金や銅などからなり、それぞれのバンプははんだからなる。ただし、各部材の材料はこれに限定されるものではない。   In the present embodiment, the pads, vias, internal wirings, etc. of the semiconductor elements 2, 3, the interposer substrate 14, and the organic substrate 18 are made of nickel / gold, copper, etc., and the bumps are made of solder. However, the material of each member is not limited to this.

次に、この半導体装置１の電気接続について説明する。半導体素子２の内部では、各半導体基板４ａ〜４ｄ同士が、パッド９ａ〜９ｄ、バンプ６ａ〜６ｄ、貫通ビア７ａ〜７ｄ、およびパッド８ａ〜８ｄの直接の接触によって電気的に接続されている。そして、この半導体素子２の、最もインターポーザ基板１４に近い面（図１では最も下側の面）のパッド８ａが、インターポーザ基板１４の一方の面のパッド１５と、バンプ６ｅを介して接続されている。一方、半導体素子３のパッド１２が、インターポーザ基板１４の他方の面のパッド１６と、バンプ１３を介して接続されている。そして、インターポーザ基板１４の一方の面のパッド１５と他方の面のパッド１６とは、内部配線２４を介して接続されている。   Next, electrical connection of the semiconductor device 1 will be described. Inside the semiconductor element 2, the semiconductor substrates 4a to 4d are electrically connected to each other by direct contact of the pads 9a to 9d, the bumps 6a to 6d, the through vias 7a to 7d, and the pads 8a to 8d. The pad 8a on the surface closest to the interposer substrate 14 (the lowermost surface in FIG. 1) of the semiconductor element 2 is connected to the pad 15 on one surface of the interposer substrate 14 via the bumps 6e. Yes. On the other hand, the pad 12 of the semiconductor element 3 is connected to the pad 16 on the other surface of the interposer substrate 14 via the bump 13. The pad 15 on one surface of the interposer substrate 14 and the pad 16 on the other surface are connected via an internal wiring 24.

インターポーザ基板１４の両面のパッド１５，１６は、内部配線２４および図示しない表面の配線を介してパッド１７に接続されており、このパッド１７は、ボンディングワイヤ２０と、有機基板１８のパッド１９、内部配線２３、およびボールパッド２１を介して、はんだボール２２に接続されている。はんだボール２２には、図示しないが様々な電気部品や回路基板等が直接または間接的に接続される。従って、はんだボール２２に接続された電気部品や回路基板等は、有機基板１８やインターポーザ基板１４を介して、半導体素子２および半導体素子３と電気的に接続されている。このような電気接続によって、半導体装置１は所望の機能を発揮することができる。   The pads 15 and 16 on both surfaces of the interposer substrate 14 are connected to the pad 17 via the internal wiring 24 and the surface wiring (not shown). The pad 17 includes the bonding wire 20, the pad 19 of the organic substrate 18, and the internal wiring. It is connected to the solder ball 22 via the wiring 23 and the ball pad 21. Although not shown, various electrical components, circuit boards, and the like are directly or indirectly connected to the solder balls 22. Therefore, the electrical components, circuit boards, and the like connected to the solder balls 22 are electrically connected to the semiconductor element 2 and the semiconductor element 3 through the organic substrate 18 and the interposer substrate 14. By such electrical connection, the semiconductor device 1 can exhibit a desired function.

半導体素子２の各半導体基板４ａ〜４ｄと、半導体素子３の半導体基板１１とは、互いのパッドの平面位置が異なるため、直接積層してパッケージ化することが困難なものであるが、本実施形態では、インターポーザ基板１４を介在させることにより、積層して接続することができる。すなわち、本実施形態では、インターポーザ基板１４が、半導体素子２，３のそれぞれのパッドの平面位置の違いを調整する働きをすることによって、パッドの平面位置が互いに異なる半導体素子２，３同士を積層したマルチチップパッケージ（ＭＣＰ）の形態の半導体装置１を容易に製造することができる。   The semiconductor substrates 4a to 4d of the semiconductor element 2 and the semiconductor substrate 11 of the semiconductor element 3 are different from each other in the planar position of the pads, and thus are difficult to directly stack and package. In the embodiment, the interposer substrate 14 can be interposed to be stacked and connected. That is, in the present embodiment, the interposer substrate 14 functions to adjust the difference in the planar position of the pads of the semiconductor elements 2 and 3, thereby stacking the semiconductor elements 2 and 3 having different pad planar positions. Thus, the semiconductor device 1 in the form of a multichip package (MCP) can be easily manufactured.

次に、本実施形態の半導体装置の製造方法について説明する。   Next, a method for manufacturing the semiconductor device of this embodiment will be described.

まず、図２に示すように、ステージ（図示せず）上に複数の（図示されている例では４つの）半導体基板４ａ〜４ｄを互いに重ね合わせて配置する。このとき、各半導体基板のパッド９ａ〜９ｃと、それに隣接する半導体基板の、対向するパッド８ｂ〜８ｄとを、はんだからなるバンプ６ａ〜６ｃによって接続する。このようにして全ての半導体基板４ａ〜４ｄを互いに接続したら、ステージを除去して、半導体基板４ａ〜４ｄからなる積層体を樹脂１０ａで覆って封止する。ただし、最外側の２つの半導体基板４ａ，４ｄのパッド８ａおよびバンプ６ｄは、樹脂１０ａで覆わずに露出させておく。そして、パッド８ａ上に、バンプ６ｅとなるはんだを供給しておく。こうして半導体素子２を完成させる。なお、本実施形態では、バンプ６ｄは、他部材との電気的な接続には関与しない。   First, as shown in FIG. 2, a plurality of (four in the illustrated example) semiconductor substrates 4 a to 4 d are arranged so as to overlap each other on a stage (not shown). At this time, the pads 9a to 9c of each semiconductor substrate and the opposing pads 8b to 8d of the semiconductor substrate adjacent thereto are connected by bumps 6a to 6c made of solder. After all the semiconductor substrates 4a to 4d are connected to each other in this way, the stage is removed, and the laminate composed of the semiconductor substrates 4a to 4d is covered with the resin 10a and sealed. However, the pads 8a and the bumps 6d of the two outermost semiconductor substrates 4a and 4d are exposed without being covered with the resin 10a. And the solder used as the bump 6e is supplied on the pad 8a. Thus, the semiconductor element 2 is completed. In the present embodiment, the bump 6d is not involved in electrical connection with other members.

次に、図３に示すように、完成した半導体素子２を上下反転させて、インターポーザ基板１４の一方の面上に配置する。そして、インターポーザ基板１４のパッド１５に、半導体素子２の露出しているパッド８ａを対向させ、はんだからなるバンプ６ｅによって接続する。そして、半導体素子２とインターポーザ基板１４の接合部分の周囲を樹脂１０ｂによって覆って封止する。ただし、少なくともインターポーザ基板１４のパッド１６，１７は、樹脂１０ｂで覆わずに露出させておく。   Next, as shown in FIG. 3, the completed semiconductor element 2 is turned upside down and placed on one surface of the interposer substrate 14. Then, the exposed pad 8a of the semiconductor element 2 is opposed to the pad 15 of the interposer substrate 14, and is connected by a bump 6e made of solder. Then, the periphery of the joint portion between the semiconductor element 2 and the interposer substrate 14 is covered and sealed with the resin 10b. However, at least the pads 16 and 17 of the interposer substrate 14 are exposed without being covered with the resin 10b.

このようにして接合されて一体化した半導体素子２およびインターポーザ基板１４を上下反転させる。そして、図４に示すように、インターポーザ基板１４の他方の面上に、予め作製していた半導体素子３を配置する。そして、インターポーザ基板１４の露出しているパッド１６に、半導体素子３のパッド１２を対向させ、はんだからなるバンプ１３によって接続する。   The semiconductor element 2 and the interposer substrate 14 thus joined and integrated are turned upside down. Then, as shown in FIG. 4, the semiconductor element 3 prepared in advance is disposed on the other surface of the interposer substrate 14. Then, the pads 12 of the semiconductor element 3 are opposed to the exposed pads 16 of the interposer substrate 14 and connected by bumps 13 made of solder.

以上のようにして作製した、半導体素子２とインターポーザ基板１４と半導体素子３の積層体を上下反転させ、図５に示すように、有機基板１８上に配置する。このとき、有機基板１８の、ボールパッド２１が設けられている面と反対側の面上、すなわちパッド１９が設けられている面上に、半導体素子３の、パッド１２が設けられている面と反対側の面を置く。ただし、積層体がパッド１９に重ならないようにする。半導体素子３と有機基板１８とを電気的に接続させることはなく、半導体素子３と有機基板１８の接合部分の周囲を樹脂１０ｃによって覆って封止する。ただし、少なくとも有機基板１８のパッド１９は樹脂１０ｃで覆わずに露出させるようにしておく。   The laminated body of the semiconductor element 2, the interposer substrate 14 and the semiconductor element 3 produced as described above is turned upside down and placed on the organic substrate 18 as shown in FIG. At this time, on the surface of the organic substrate 18 opposite to the surface on which the ball pad 21 is provided, that is, on the surface on which the pad 19 is provided, the surface of the semiconductor element 3 on which the pad 12 is provided. Place the opposite side. However, the stacked body is not allowed to overlap the pad 19. The semiconductor element 3 and the organic substrate 18 are not electrically connected, and the periphery of the joint portion between the semiconductor element 3 and the organic substrate 18 is covered with a resin 10c and sealed. However, at least the pad 19 of the organic substrate 18 is exposed without being covered with the resin 10c.

それから、図１に示すように、有機基板１８のパッド１９とインターポーザ基板１４のパッド１７とを、ボンディングワイヤ２０によって接続（ワイヤボンディング）する。そして、この積層体および有機基板１８を、有機基板１８の側面およびボールパッド２１が設けられている面を除いて、全体的に樹脂１０ｄで覆って封止する。最後に、上下反転させてから、有機基板１８のボールパッド２１にはんだボール２２を固定する。このようにして、図１に示すマルチチップパッケージの形態の半導体装置１が完成する。   Then, as shown in FIG. 1, the pads 19 of the organic substrate 18 and the pads 17 of the interposer substrate 14 are connected (wire bonding) by bonding wires 20. Then, the laminate and the organic substrate 18 are entirely covered and sealed with the resin 10d except for the side surface of the organic substrate 18 and the surface on which the ball pad 21 is provided. Finally, after turning upside down, the solder ball 22 is fixed to the ball pad 21 of the organic substrate 18. Thus, the semiconductor device 1 in the form of a multichip package shown in FIG. 1 is completed.

次に、本発明の半導体装置１の他の実施形態について説明する。ただし、前記した実施形態との相違点のみを以下に記載し、前記した実施形態と同様の内容については説明を省略する。   Next, another embodiment of the semiconductor device 1 of the present invention will be described. However, only differences from the above-described embodiment will be described below, and description of the same contents as those of the above-described embodiment will be omitted.

図６に示すこの実施形態の半導体装置１では、有機基板１８とインターポーザ基板１４との間にスペーサー２５が配置されている。この実施形態では、有機基板１８とインターポーザ基板１４の接合部分を樹脂１０ｃによって封止する代わりに、スペーサー２５によって保持し、その後に、積層体の周囲と同時にこの接合部分を樹脂１０ｄによって封止する。この構成によると、インターポーザ基板１４と有機基板１８との相対位置関係、特に両者の間隔がより精度良く保たれ、機械構造の面でも電気接続の面でも信頼性が高くなる。また、樹脂による封止工程を１工程少なくできるので、製造が簡単になる。   In the semiconductor device 1 of this embodiment shown in FIG. 6, a spacer 25 is disposed between the organic substrate 18 and the interposer substrate 14. In this embodiment, instead of sealing the joint portion between the organic substrate 18 and the interposer substrate 14 with the resin 10c, the joint portion is held by the spacer 25, and then the joint portion is sealed with the resin 10d simultaneously with the periphery of the laminate. . According to this configuration, the relative positional relationship between the interposer substrate 14 and the organic substrate 18, particularly the distance between the two, can be maintained with higher accuracy, and the reliability can be improved both in terms of mechanical structure and electrical connection. Moreover, since the sealing step with resin can be reduced by one step, the manufacturing is simplified.

以上説明したように、本発明によると、互いに異なる平面位置にパッドが配置された半導体素子２，３同士を積層して、マルチチップパッケージの形態の半導体装置１を容易に製造できる。これは、両半導体素子２，３の間に介在するインターポーザ基板１４が、パッドの平面位置を調整する機能を有しているからである。すなわち、このインターポーザ基板１４は、その一方の面と他方の面とにそれぞれ平面位置の異なるパッドを有し、具体的には、一方の面には半導体素子２のパッド８ａに対向する（一致する）平面位置にパッド１５を有し、他方の面には半導体素子３のパッド１２に対向する（一致する）平面位置にパッド１６を有しており、一方の面のパッド１５と他方の面のパッド１６とが、インターポーザ基板１４の内部で内部配線２４を介して接続されている（ただし、インターポーザ基板１４の内部で接続する必要がないパッド１５および／またはパッド１６が存在する場合には、内部配線２４を設けず接続を行わない箇所もある）。そのため、このインターポーザ基板１４の各面に半導体素子２，３をそれぞれ配置することにより、パッドの平面位置が異なる半導体素子２，３同士を積層して半導体装置１を容易に製造することが可能になっている。   As described above, according to the present invention, the semiconductor device 1 in the form of a multichip package can be easily manufactured by stacking the semiconductor elements 2 and 3 having pads arranged at different plane positions. This is because the interposer substrate 14 interposed between the semiconductor elements 2 and 3 has a function of adjusting the planar position of the pad. That is, the interposer substrate 14 has pads having different planar positions on one surface and the other surface, and specifically, faces (matches) the pads 8a of the semiconductor element 2 on one surface. ) A pad 15 is provided at a plane position, and a pad 16 is provided at a plane position opposite (coincident with) the pad 12 of the semiconductor element 3 on the other surface. The pad 15 on one surface and the pad 15 on the other surface The pad 16 is connected to the inside of the interposer substrate 14 via the internal wiring 24 (however, if there are the pad 15 and / or the pad 16 that do not need to be connected inside the interposer substrate 14, the internal There is a place where the connection is not performed without the wiring 24). Therefore, by arranging the semiconductor elements 2 and 3 on each surface of the interposer substrate 14, the semiconductor device 1 can be easily manufactured by stacking the semiconductor elements 2 and 3 having different pad planar positions. It has become.

言い換えると、インターポーザ基板１４の一方の面には、その面のパッド１５と同じ平面位置に配置されたパッド８ａを有する半導体素子２が配置されてパッド８ａ，１５同士が接続され、他方の面には、その面のパッド１６と同じ平面位置に配置されたパッド１２を有する他の半導体素子３が配置されてパッド１２，１６同士が接続されている。   In other words, on one surface of the interposer substrate 14, the semiconductor element 2 having the pads 8a arranged at the same plane position as the pads 15 on the surface is arranged so that the pads 8a and 15 are connected to each other, and the other surface is connected to the other surface. The other semiconductor element 3 which has the pad 12 arrange | positioned in the same plane position as the pad 16 of the surface is arrange | positioned, and pads 12 and 16 are connected.

なお、図１〜５には、半導体素子２，３のパッドのピッチが互いに異なっているためそれらのパッドの平面位置が互いにずれている例を示している。ただし、このような例に限られず、少なくとも一部のパッドのピッチは一致しているがいずれかのパッドの平面位置が少しでも互いに異なっている半導体素子同士を積層する場合にも、本発明を採用することは極めて効果的である。   1 to 5 show an example in which the pad positions of the semiconductor elements 2 and 3 are different from each other, so that the planar positions of the pads are shifted from each other. However, the present invention is not limited to such an example, and the present invention is also applied to a case where semiconductor elements are stacked in which the pitches of at least some of the pads are the same but the plane positions of any of the pads are slightly different from each other. Employing is extremely effective.

また、前記した２つの実施形態は、貫通ビア（ＴＳＶ）７ａ〜７ｄを有する半導体素子２と、貫通ビアを有していない半導体素子３とを積層して構成された半導体装置１に関するものである。しかし、貫通ビアを有する半導体素子同士を積層する場合や、貫通ビアを有していない半導体素子同士を積層する場合であっても、少なくとも一部のパッドの平面位置が互いに異なっている半導体素子同士を積層する構成であれば、本発明を採用することが効果的である。   The two embodiments described above relate to a semiconductor device 1 configured by stacking a semiconductor element 2 having through vias (TSV) 7a to 7d and a semiconductor element 3 having no through via. . However, even when semiconductor elements having through vias are stacked or when semiconductor elements having no through vias are stacked, semiconductor elements having at least some of the planar positions of pads differ from each other. If it is the structure which laminates | stacks, it is effective to employ | adopt this invention.

半導体装置１の一例としては、完成状態において有機基板１８側（下側）に位置する半導体素子３が、寸法（チップサイズ）が小さい素子、例えば論理回路素子（logic chip）であって、有機基板１８から遠い側（上側）に位置する半導体素子２が、寸法（チップサイズ）が大きい素子、例えばＤＲＡＭなどのメモリ素子である構成が挙げられる。このように、上側にチップサイズが大きい半導体素子２を、下側にチップサイズが小さい半導体素子３を配置する構成であっても、インターポーザ基板１４を介在させることにより、電気接続を確保できるとともに、機械的な安定性も得ることができる。特に、前記した製造方法のように、インターポーザ基板１４の一方の面に一方の半導体素子を実装する工程の後に、他方の面に他方の半導体素子を実装する工程を行うようにすると、精度良く安定して半導体装置を製造することができる。   As an example of the semiconductor device 1, the semiconductor element 3 located on the organic substrate 18 side (lower side) in the completed state is an element having a small size (chip size), for example, a logic circuit element (logic chip). A configuration in which the semiconductor element 2 positioned on the side (upper side) far from 18 is an element having a large size (chip size), for example, a memory element such as a DRAM. As described above, even when the semiconductor element 2 having a large chip size is arranged on the upper side and the semiconductor element 3 having a small chip size is arranged on the lower side, by interposing the interposer substrate 14, electrical connection can be secured, Mechanical stability can also be obtained. In particular, when the step of mounting one semiconductor element on one surface of the interposer substrate 14 is followed by the step of mounting the other semiconductor element on the other surface as in the manufacturing method described above, it is stable with high accuracy. Thus, a semiconductor device can be manufactured.

前記した２つの実施形態では、はんだボール２２を介して外部に接続される有機基板１８側（下側）に、チップサイズが小さく貫通ビアを持たない論理回路素子（logic chip）を配置し、有機基板１８から遠い側（上側）に、チップサイズが大きく貫通ビアを有するＤＲＡＭなどのメモリ素子を配置している。この構成の場合には、有機基板に近い論理回路素子が、外部への入出力と、メモリ素子との間の入出力とを行う。   In the two embodiments described above, the logic circuit element (logic chip) having a small chip size and no through via is arranged on the organic substrate 18 side (lower side) connected to the outside via the solder ball 22, A memory element such as a DRAM having a large chip size and a through via is disposed on the side (upper side) far from the substrate 18. In the case of this configuration, a logic circuit element close to the organic substrate performs input / output to / from the outside and input / output to / from the memory element.

これに対し、仮に、インターポーザ基板１４を有しておらず半導体素子同士を直接積層し、有機基板１８側（下側）に、チップサイズが大きく貫通ビアを有するＤＲＡＭなどのメモリ素子が配置されている構成の場合には、このメモリ素子が、論理回路素子への入出力を含めて半導体装置の全ての入出力を行うことになる。そのため、メモリ素子のパッドの位置を、論理回路素子のパッドの位置を考慮した上で設計しなければならない。このことは、半導体装置を構成する半導体素子の１つであるメモリ素子の汎用化を妨げるものであり、製造効率の低下と高コスト化をもたらすものであった。しかし、前記した２つの実施形態の構成によると、有機基板に近い論理回路素子が、外部への入出力と、メモリ素子との間の入出力とを行うため、メモリ素子の汎用化を可能にし、製造効率の低下および高コスト化を抑えることができる。   On the other hand, if the interposer substrate 14 is not provided and the semiconductor elements are directly stacked, a memory element such as a DRAM having a large chip size and a through via is disposed on the organic substrate 18 side (lower side). In the case of the configuration, this memory element performs all input / output of the semiconductor device including input / output to the logic circuit element. Therefore, the position of the pad of the memory element must be designed in consideration of the position of the pad of the logic circuit element. This hinders generalization of a memory element, which is one of the semiconductor elements constituting the semiconductor device, resulting in a decrease in manufacturing efficiency and an increase in cost. However, according to the configuration of the two embodiments described above, since the logic circuit element close to the organic substrate performs input / output to / from the outside and input / output to / from the memory element, the memory element can be generalized. Therefore, it is possible to suppress a decrease in manufacturing efficiency and an increase in cost.

なお、以上の説明は全て、１つのインターポーザ基板の両面にそれぞれ１つずつ半導体素子が配置された半導体装置に関するものであるが、複数のインターポーザ基板を用い、各々のインターポーザ基板の両面にそれぞれ半導体素子が配置されるような構成にすることもできる。このようにすることで、互いに異なる平面位置に配置されたパッドを有する３つ以上の半導体素子（一例としては、１つのメモリ素子（例えばＤＲＡＭ）と２つの論理回路素子）を順次積層して、１つのマルチチップパッケージの形態の半導体装置を容易に製造することができる。   The above description is all related to a semiconductor device in which one semiconductor element is disposed on each side of one interposer substrate. However, a plurality of interposer substrates are used, and the semiconductor elements are disposed on both sides of each interposer substrate. It is also possible to adopt a configuration in which are arranged. By doing so, three or more semiconductor elements (for example, one memory element (for example, DRAM) and two logic circuit elements) having pads arranged at different planar positions are sequentially stacked, A semiconductor device in the form of one multichip package can be easily manufactured.

１ 半導体装置
２，３ 半導体素子
４ａ〜４ｄ，１１ 半導体基板
５ａ〜５ｄ 樹脂層
６ａ〜６ｅ，１３ バンプ
７ａ〜７ｄ 貫通ビア
８ａ〜８ｄ，９ａ〜９ｄ，１２，１５〜１７，１９ パッド
１０ａ〜１０ｄ 樹脂
１４ インターポーザ基板
１８ 有機基板（実装基板）
２０ ボンディングワイヤ
２１ ボールパッド
２２ はんだボール
２３，２４ 内部配線
２５ スペーサー DESCRIPTION OF SYMBOLS 1 Semiconductor device 2, 3 Semiconductor element 4a-4d, 11 Semiconductor substrate 5a-5d Resin layer 6a-6e, 13 Bump 7a-7d Through-via 8a-8d, 9a-9d, 12, 15-17, 19 Pad 10a-10d Resin 14 Interposer substrate 18 Organic substrate (mounting substrate)
20 Bonding wire 21 Ball pad 22 Solder balls 23, 24 Internal wiring 25 Spacer

Claims (9)

複数の半導体素子と、前記半導体素子の間に介在するインターポーザ基板とを有し、
前記インターポーザ基板の一方の面には、該一方の面上に位置する前記半導体素子のパッドの平面位置に一致する平面位置に配置されたパッドが形成されており、
前記インターポーザ基板の他方の面には、該他方の面上に位置する前記半導体素子のパッドの平面位置に一致する平面位置に配置されたパッドが形成されており、
前記一方の面に形成された前記パッドと前記他方の面に形成された前記パッドとは、前記インターポーザ基板の内部で接続されている、半導体装置。 A plurality of semiconductor elements, and an interposer substrate interposed between the semiconductor elements,
On one surface of the interposer substrate, there is formed a pad arranged at a planar position that matches the planar position of the pad of the semiconductor element located on the one surface,
The other surface of the interposer substrate is formed with a pad disposed at a planar position that matches the planar position of the pad of the semiconductor element located on the other surface,
The semiconductor device, wherein the pad formed on the one surface and the pad formed on the other surface are connected inside the interposer substrate. 前記インターポーザ基板の一方の面に形成されたパッドと前記インターポーザ基板の他方の面に形成されたパッドとは、互いに異なる平面位置に配置されている、請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the pad formed on one surface of the interposer substrate and the pad formed on the other surface of the interposer substrate are arranged at different plane positions. 前記インターポーザ基板の一方の面に形成されたパッドと前記インターポーザ基板の他方の面に形成されたパッドとは、互いに異なるピッチで配置されている、請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the pads formed on one surface of the interposer substrate and the pads formed on the other surface of the interposer substrate are arranged at different pitches. 前記複数の半導体素子は互いに異なる寸法を有している、請求項１から３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the plurality of semiconductor elements have different dimensions. 前記複数の半導体素子のうち、小さな寸法の半導体素子が前記インターポーザ基板の下側に位置し、大きな寸法の半導体素子が前記インターポーザ基板の上側に位置している、請求項４に記載の半導体装置。   5. The semiconductor device according to claim 4, wherein among the plurality of semiconductor elements, a semiconductor element having a small size is positioned below the interposer substrate, and a semiconductor element having a large size is positioned above the interposer substrate. 前記複数の半導体素子のうち、前記インターポーザ基板の一方の面に位置する半導体素子は貫通ビアを有し、前記インターポーザ基板の他方の面に位置する半導体素子は貫通ビアを有していない、請求項１から５のいずれか１項に記載の半導体装置。   The semiconductor element located on one surface of the interposer substrate among the plurality of semiconductor elements has a through via, and the semiconductor element located on the other surface of the interposer substrate does not have a through via. 6. The semiconductor device according to any one of 1 to 5. 前記複数の半導体素子のうちの一方の半導体素子は、下側が小さい台形状に封止されていることを特徴とする、請求項１から６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein one semiconductor element of the plurality of semiconductor elements is sealed in a trapezoidal shape with a lower side. 前記半導体装置において、さらに実装基板を備えている、請求項１から７のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a mounting substrate. 前記実装基板と前記インターポーザ基板とは、ボンディングワイヤで接続されている、請求項８に記載の半導体装置。   The semiconductor device according to claim 8, wherein the mounting substrate and the interposer substrate are connected by a bonding wire.
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