JPH10284681A - Memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the internal interconnections of memory chips while maintaining a large capacity by a method, wherein at least a part of interconnections between a plurality of the memory chips are formed on a module board on which a plurality of the memory chips are mounted. SOLUTION: A memory module 10 is constituted by the COB mounting of a plurality of memory bare chips 1 on a module board 2. Interconnections between the respective memory bare chips 1 are formed on the module board 2, instead of a main board. With this constitution, instead of conducting a part of multilayer interconnections on the memory chips 1 formed on the module board 2, the interconnections on the respective memory bare chips 1 can be simplified in comparison with the case where the total capacity which is the summation of the respective capacities of the memory bare chips 1 is realized by a single memory chip. Further, the quantity of interconnections in the main board can be substantially reduced, in comparison with the case that the memory bare chips 1 mounted on the module board 2 are individually mounted on the main board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory module that can be mounted on a memory board, a motherboard, or the like.

[0002]

2. Description of the Related Art Computer equipment, such as personal computers and workstations, is designed so that the memory capacity can be changed as necessary.
mory Module) and DIMM (Dual Inline Memory Modul)
e) Slots for mounting memory boards are provided. Although a plurality of memory chips are mounted on these memory boards, they are often mounted in a packaged state, so the number of memory chips that can be mounted on the memory board is limited by the size of the package. .
Therefore, in order to increase the memory capacity of the computer device, the integration degree of the memory chip is increased to increase the memory chip 1.
The only option is to increase the memory capacity per unit.

[0003]

However, when one DRAM chip of 256 Mbits is mounted instead of four DRAM chips of 64 Mbits, for example, the memory capacity inside the chip is quadrupled. In addition to the increase, when four chips are individually mounted, the wiring on the substrate must be performed inside the chip, so that the structure inside the chip becomes more complicated. Therefore, it is necessary to increase the number of element formation layers inside the chip or to reduce the wiring width and the element formation region by using a more advanced microfabrication technique, which may require enormous costs for design changes.

[0004] The present invention has been made in view of the above points, and an object of the present invention is to provide a memory module which can simplify the internal wiring of a memory chip even when a large capacity is secured. To provide.

[0005]

According to a first aspect of the present invention, there is provided a module substrate having an even number of memory chips mounted thereon. The reason why an even number of memory chips are mounted is that a motherboard or the like of a computer device generally has a data bus configured in multiples of two, and when the module substrate is formed in a rectangular shape, each memory chip is mounted. There is also an advantage that it can be disposed on the surface without waste. Compared to the case where a single memory chip achieves the total capacity of the even number of memory chips mounted on the module substrate, a part of the multilayer wiring can be performed on the module substrate. The upper wiring can be simplified. Further, since the wiring is performed on the module substrate, the terminal arrangement of the module substrate can be changed using a common memory chip by only partially changing the wiring.

According to a second aspect of the present invention, an external connection terminal for exchanging signals with the main board is provided on the module board. Wiring is performed on the module board so that the number of external connection terminals is smaller than the total number of pads of the memory chip mounted on the module board, compared to the case where memory chips are individually mounted on the main board. The amount of wiring on the main board can be reduced, and the wiring length can be shortened.

According to a third aspect of the present invention, for pads corresponding to terminals commonly used by a plurality of memory chips, such as control terminals and address terminals, pads of the same type are used in a module substrate by using, for example, a wiring pattern. Connected to each other, eliminating the need for wiring on the main board side.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory module to which the present invention is applied will be specifically described with reference to the drawings.

FIG. 1 is a plan view schematically showing a memory module according to this embodiment, and FIG. 2 is a sectional view taken along line AA 'of FIG. As shown in FIG. 1, a memory module 10 includes four memory bare chips 1 individually cut out from a semiconductor wafer on a module substrate 2 by COB (Chip On Board).
) Implemented. Each memory bare chip 1
For example, it is a DRAM having a memory capacity of 4M × 4 bits. Each of the memory bare chips 1 has a rectangular shape, and the input / output pads 3 are formed in a line along the long side thereof.

On the other hand, the module substrate 2 is made of a SO
−DIMM (Small Outline Dual Inline Memory Modul
e) It has an external dimension that can be mounted on a board, and a plurality of pads 4 are formed in a row near the center of the module board 2 along the longitudinal direction. Two bare chips 1 for memory are mounted on both sides of these pads 4,
The direction in which the pads 4 of the module substrate 2 are arranged and the direction in which the input / output pads 3 of each memory bare chip 1 are arranged are substantially parallel.

The pads 4 of the module substrate 2 and the input / output pads 3 of the memory bare chip 1 are connected by bonding wires 5, respectively. The pad 4 includes a pad to which two bonding wires 5 are connected and a pad to which one bonding wire is connected. For those commonly connected to a plurality of memory bare chips 1, such as address terminals of the memory bare chip 1, the pads 4 are shared by connecting a plurality of bonding wires 5 to the pads 4 on the module substrate 2. Is being planned.

As described above, for some of the pads 4,
Since a plurality of bonding wires 5 are connected, the total number of pads 4 can be smaller than the total number of input / output pads 3 of all memory bare chips 1. Further, by connecting two bonding wires 5 to some of the pads 4, the two bonding wires 5 are connected via the common pad 4.
Since the connections can be made at the same time, the amount of wiring in the module substrate 2 can be reduced. For example, when the module substrate 2 is configured using a multilayer substrate, the number of layers of the substrate can be reduced, and the cost of the memory module 10 can be reduced.

The memory bare chips 1 are arranged so that the input / output pads 3 of the memory bare chip 1 are arranged in two rows in parallel with the longitudinal direction of the module substrate 2, and the pads 4 of the module substrate 2 are interposed therebetween. When the two memory bare chips 1 arranged adjacent to each other are aligned, when connecting the bonding wires 5 from each memory bare chip 1 to the common pad 4 of the module substrate 2, Bonding wires 5 are connected to the common pad 4 at the shortest distance.

In addition, when the corresponding input / output pads 3 of the two memory bare chips 1 are connected to each other, it is only necessary to connect the common pads 4 of the module substrate 2 with the bonding wires 5. There is no need to perform wiring using different wiring layers in the substrate 2, and wiring in the module substrate 2 can be simplified. On the other hand, considering the case where the direction of the memory bare chip 1 is reversed,
The corresponding identical input / output pads 3 are connected to the module substrate 2
However, even if an attempt is made to connect to the common pad 4, the connection cannot be made directly by the wire bonding 5, for example, once through another wiring layer in the module substrate 2, and the wiring of the module substrate 2 becomes complicated.

Pads 4 are formed substantially in a row at the center of the module substrate 2, and the bare chips 1 for memory are arranged on both sides of the pads 4 so that the pads 4 and the input / output pads 3 are bonded by bonding wires 5. Because of the connection, the lateral width of the module substrate 2 can be reduced, and the length of the bonding wires 5 can be made uniform.

As shown in FIG. 2, in the memory module 10 of the present embodiment, the upper surface of the wire-bonded memory bare chip 1 is covered with a resin 6 to prevent disconnection or the like. When the resin 6 is formed thick, the memory module 1
0 is too high, a sealing frame 7 having a predetermined height is attached near the outer periphery of the module substrate 2.
The resin 6 is poured into the inside, so that the resin thickness matches the height of the sealing frame 7. Thereby, variation in the height of the memory module 10 can be reliably suppressed.

The memory module 10 of this embodiment is mounted on various substrates such as an SO-DIMM substrate by a so-called LCC (Leadless Chip Carrier) method. FIG. 3 is a perspective view showing a part of the memory module 10 shown in FIG. 1. The LCC method will be described with reference to FIG. A plurality of external connection terminals 8 formed in a concave shape are provided on the outer surface of the module substrate 2, and these external connection terminals 8 are connected to the module substrate 2 via a wiring pattern 9.
Is electrically connected to the pad 4. For example, when the memory module 10 of the present embodiment is mounted on an SO-DIMM board, the external connection terminal 8 shown in FIG.
Solder is poured into the external connection terminals 8 and fixed to the pads on the MM substrate.

As described above, since the memory module 10 of the present embodiment is mounted on another substrate by pouring solder into the external connection terminals 8 on the outer surface, the mounting area substantially matches the module size, and C, one of the packaging technologies
CS that goes one step further than the SP (Chip Size Package) method
Mounting by the M (Chip Size Module) method can be realized.

Further, since the module substrate 2 is mounted on the main substrate by soldering, the repair (replacement) operation when the memory module 10 becomes defective can be performed relatively easily, and the main substrate on which the memory module 10 is mounted is mounted. Yield can be improved.

The memory module 10 according to the present embodiment
Is a memory bare chip 1 formed on a semiconductor wafer.
Is cut out and mounted on the module substrate 2 without packaging.
(For example, four) memory bare chips 1 can be mounted without difficulty.

FIG. 4 shows the memory module 10 shown in FIG.
FIG. In this figure, some terminals such as a power supply terminal and a ground terminal are omitted for simplification. As shown in the figure, some of the terminals of each memory bare chip 1 are commonly connected to all the memory bare chips 1. Specifically, address terminals A0 to A10 of each memory bare chip are commonly connected to external connection terminals ADR0 to ADR10, respectively, and a control terminal RAS
Is the external connection terminal RE, and the control terminal WE is the external connection terminal W
E, the control terminal OE is commonly connected to the external connection terminal OE. On the other hand, data terminals I / O0 to I / O
3 are separately connected to external connection terminals D0 to D15. The control terminal CAS is connected to the external connection terminals CE0 and CE1 as a set of two memory bare chips 1.

FIG. 5 is a diagram showing a pattern layout of the module substrate 2, wherein the hatched portions in FIG.
The dotted line in the figure indicates the mounting position of the memory bare chip 1. The module substrate 2 is formed of, for example, a four-layer printed wiring board, and a solid pattern 21 for grounding is formed on the uppermost layer and the lowermost layer.

FIG. 5 shows a pattern layout of the uppermost layer. Pads 4 are formed substantially in a row in the center of the uppermost layer in the longitudinal direction. 21 are formed. A wiring pattern 22 is connected to each pad 4, and the other ends of these wiring patterns 22 are connected to through holes 23 except for a part. The through hole 23 is connected to an inner layer pattern or a lowermost layer pattern, and each of these layer patterns is connected to the external connection terminal 8. In addition, for terminals commonly connected to a plurality of memory bare chips 1 such as address terminals and control terminals, a plurality of corresponding pads are connected to each other by a wiring pattern 22.

As described above, since one external connection terminal 8 is shared by the pads 3 of the plurality of bare chips 1 for memory, the number of external connection terminals 8 can be reduced, and the number of external connection terminals 8 corresponds to one bare chip for memory. And the total number of input / output pads 3 does not change much.

The memory module 10 of the present embodiment
Are a plurality of bare chips for memory 1 on a module substrate 2.
Is mounted by COB, and the wiring between each memory bare chip 1 is
Since it is performed on the module substrate 2 instead of on the main substrate, a part of the multilayer wiring on the chip is partially Since it can be performed on the substrate 2, the wiring on each memory bare chip 1 can be simplified. Further, compared with a case where the memory bare chips 1 mounted on the module substrate 2 are individually mounted on the main substrate, the amount of wiring in the main substrate can be far reduced.

Further, since the wiring is performed on the module substrate 2, only a part of the wiring is changed, and the wiring inside the module substrate 2 is changed by using the common memory bare chip 1. The arrangement of the connection terminals 8 can be changed.

FIG. 6 shows a memory module 10 according to this embodiment.
6A is a plan view showing an example in which is mounted on the SO-DIMM board 11, FIG. 6A shows the front side of the SO-DIMM board 11, and FIG. 6B shows the back side. SO-DIM shown in FIG.
Two memory modules 10 are mounted on the M board 11 both on the front side and the back side, and two capacitors (hereinafter referred to as decaps) 12 for preventing noise are provided for each memory module 10. . On the front side, a controller 13 for controlling reading and writing of each memory bare chip 1 is mounted.
Each memory module 10 is mounted by the above-described LCC method, and the bypass capacitor 12 and the controller 13
(Surface Mount Technology).

The SO-DIMM board shown in FIG. 6 has the same result as the mounting of 16 memory ICs, eight on each side. For example, the memory bare chips 1 constituting the memory module 10 are each 4M × 4 bits. , The memory capacity of each memory module 10 is 8
M-byte, total memory capacity of SO-DIMM is 32M
Become bytes.

In the above embodiment, the module substrate 2
An example in which a plurality of memory bare chips are mounted on a COB has been described above. Instead of the COB mounting, a so-called COG (Chip On Glass) mounting in which a chip is mounted on a glass substrate or a COF (COF) in which a chip is mounted on film Chip On Fi
lm) Mounting may be performed, and the material of the module substrate 2 may be appropriately changed as necessary.

Instead of mounting the memory bare chip 1 on the module substrate 2 using the bonding wires 5, the memory bare chip 1 is flip-chip mounted on the module substrate 2 using bumps such as solder balls and gold balls. You may. In the case of flip-chip mounting, as shown in FIG. 7, pads 4 'may be formed on the module substrate 2 at the same intervals as the input / output pads 3 of the memory bare chip 1.

In the above-described embodiment, the completed memory module 10 is connected to the SO-DIM by the LCC method.
Although an example of mounting on a main substrate such as M has been described, mounting may be performed by a BGA (Ball Grid Array) method using bumps such as solder balls.

In the above-described embodiment, an example in which the memory bare chip 1 formed on the semiconductor wafer is cut out one by one has been described. However, the cutout unit may be two or more. Can be cut out in a plurality of units so as to be arranged in two or more rows and mounted on the module substrate 2 of the memory module 10, so that the mounting area can be further reduced.
The outer dimensions of the memory module 10 can be further reduced. In addition, by cutting out a plurality of sets, the positioning when mounting the module substrate 2 becomes easy, and the trouble of cutting out the semiconductor wafer can be saved.

In FIG. 1, the bonding wires 5 are drawn almost symmetrically from the two memory bare chips 1 arranged on both sides of the pad on the module substrate 2 as shown in FIG. The bonding wires 5 may be alternately drawn from the memory bare chips 1 on both sides. When the bonding wires 5 are pulled out alternately, the interval between the adjacent memory bare chips 1 can be reduced, and the area of the memory module 10 can be further reduced. FIG. 8 shows an example in which pads 4 to which one bonding wire 5 is connected and pads 4 to which two bonding wires 5 are connected are mixed.

Although FIGS. 1 and 8 illustrate an example in which the memory module 10 is configured to include the four memory bare chips 1, the number of the memory bare chips 1 mounted on the memory module 10 is four. However, there is no particular limitation as long as it is two or more. However, if too many memory bare chips 1 are mounted, the failure rate of the memory module 10 may increase. Therefore, the type of the memory bare chip 1 to be mounted (for example,
The number of memory bare chips 1 to be mounted is desirably determined in consideration of the number of bits and the memory capacity) and the number of bits of the memory module 10 to be manufactured.
However, ordinary computer equipment often manages the memory capacity in multiples of four, and therefore it is desirable that the number of memory bare chips 1 mounted on the module substrate be an even number.

In FIG. 8, the bonding wires 5 are alternately drawn from the bare memory chips 1 mounted on both sides of the pads 4 of the module substrate 2. However, as shown in FIG. The bonding wire 5 may be drawn out alternately in units of. By performing such wire bonding, repair (replacement) of the defective memory bare chip 1 becomes easy.

FIG. 1 shows an example in which the pads 4 are formed in substantially one line on the module substrate 2.
May be formed in two or more rows. FIG. 10 shows an example in which pads 4 are formed in two rows on a module substrate 2 (hereinafter referred to as pad rows), and memory bare chips 1 are mounted on both sides of the pad rows. Each input / output pad 3 of each memory bare chip 1 jumps over a pad 4 in a row at a close distance and is connected to a pad 4 in a row at a distance by a bonding wire 5. By making such a connection, the distance between the memory bare chips 1 can be reduced, so that the memory module 1
The area of 0 can be further reduced.

FIGS. 11 to 17 show modified examples of the memory module. As shown in FIGS. 11 and 12, two rows of input / output pads 3 are formed along the long side of the memory bare chip 1, and the bonding wires 5 are drawn out on both sides of each memory bare chip 1 or as shown in FIGS. As shown in FIG. 16, the input / output pads 3 may be formed in two rows along the short side of the memory bare chip 1, and the bonding wires 5 may be drawn out on both sides of each memory bare chip 1. In addition, as shown in FIG.
May be used to configure a memory module.

When flip-chip mounting is performed using a memory bare chip as shown in FIG. 14, the mounting state may be unstable.
As shown in (a) or (b), it is desirable to form several pads near the short side of each bare chip for memory. When the input / output pads 3 are formed in a line on the memory bare chip, the input / output pads 3 may be formed in a line in a stepwise manner as shown in FIG.

In the above embodiment, the module substrate 2
Although an example in which a DRAM is mounted on the memory device is described above, it is also possible to mount another type of memory bare chip 1 such as an SRAM or a flash ROM.

[0040]

As described above in detail, according to the present invention, a plurality of conventional memory chips are mounted on a module substrate in a bare state, and a part of wiring between the memory chips is performed on the module substrate. Therefore, the internal wiring of the chip can be simplified as compared with the case where the total capacity obtained by summing the capacities of the memory chips is realized by a single memory chip. In addition, the memory module of the present invention achieves the same capacity as a large-capacity memory chip by using a plurality of small-capacity memory chips, and is much lower than mounting a single large-capacity memory chip. It is possible to realize a high packaging density, which is costly and equivalent to a case where a large-capacity memory chip is mounted. That is, since the mounting density of the main board can be increased by using an inexpensive memory chip, the memory capacity of the computer device can be significantly increased at low cost.

Further, when the memory module of the present invention is mounted on the main board, the mounting area can be reduced as compared with the case where a plurality of memory chips are individually mounted, so that the wiring length is shortened and the influence of wiring delay and noise is reduced. Hard to receive.
Furthermore, even when a memory chip having a different pin arrangement is mounted on a module board, it is not necessary to change the wiring pattern of the main board as long as the wiring on the module board is changed. Can be easily and inexpensively performed. Alternatively, memory modules having different terminal arrangements can be realized only by changing only the wiring in the module substrate using the same memory chip.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a memory module according to an embodiment.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a perspective view showing a part of a memory module.

FIG. 4 is a circuit diagram of a memory module.

FIG. 5 is a diagram showing a pattern layout of a module substrate.

FIG. 6 is a diagram illustrating a state where the memory module is mounted on an SO-DIMM board;

FIG. 7 is a pad formation view on a module substrate when a memory bare chip is flip-chip mounted.

FIG. 8 is a plan view of a memory module showing an example in which bonding wires are alternately drawn.

FIG. 9 is a diagram illustrating an example in which bonding wires are alternately drawn in units of a plurality of wires.

FIG. 10 is a diagram showing an example in which pads are formed in two rows on a module substrate.

FIG. 11 is a diagram showing another modified example of the memory module.

FIG. 12 is a diagram showing another modification of the memory module.

FIG. 13 is a diagram showing another modification of the memory module.

FIG. 14 is a diagram showing another modification of the memory module.

FIG. 15 is a diagram showing another modified example of the memory module.

FIG. 16 is a diagram showing another modification of the memory module.

FIG. 17 is a diagram showing another modified example of the memory module.

FIG. 18 is a view showing a modified example of a memory bare chip.

FIG. 19 is a view showing another modification of the memory bare chip.

[Explanation of symbols]

 Reference Signs List 1 bare chip for memory 2 module board 3 input / output pad 4 pad 5 bonding wire 6 resin 7 sealing frame 8 external connection terminal

Claims (3)

[Claims] 1. A module substrate having an even number of memory chips cut from a semiconductor wafer mounted thereon, wherein at least a part of wiring between the even number of memory chips is performed on the module substrate. Memory module. 2. The module board according to claim 1, wherein the module substrate has a plurality of external connection terminals for mounting on a main substrate, and the number of these external connection terminals is smaller than the total number of pads of the even number of memory chips. A memory module, wherein at least some of the external connection terminals are electrically connected to the plurality of pads on the module substrate. 3. The module board according to claim 2, wherein, of the pads of the even-numbered memory chips, at least a part of the control terminals and a pad corresponding to the address terminal have the same type of pad in the module substrate. A memory module characterized by conduction.