JPH1174449A - Memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module which can perform the noise countermeasure of each memory chip on a module substrate, and can achieve simplification of the mounting process including noise countermeasure parts when module substrates are mounted on various kinds of substrates. SOLUTION: On a module substrate 2, bare chips 1 for memory which are cut out from a semiconductor wafer, a dumping resistor 6 for noise countermeasure and a bypass capacitor 7 are mounted. The dumping resistor 6 is inserted into a signal line which connects chip pad 3 on the bare chip 1 for the memory and an external connection terminal 8 of the module substrate 2. Furthermore, the bypass capacitor 7 connects the signal line which connects the pad 3 for the chip in correspondence with a terminal imparting a power supply voltage and the external connecting terminal 8 in correspondence with a terminal imparting this power supply voltage, and the signal line which connects the pad 3 for the chip in correspondence with a terminal imparting a ground level and the external connecting terminal 8 in correspondence with a terminal imparting this ground level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory module used for a personal computer (personal computer) and the like.

[0002]

2. Description of the Related Art A memory bare chip or the like cut out from a semiconductor wafer is usually mounted on various substrates in a packaged state. However, since the external dimensions of the package are considerably larger than the size of various bare chips themselves, the number of memory packages that can be mounted on a printed circuit board or the like cannot be significantly increased.

On the other hand, recently, in order to process a large amount of data such as an image at a high speed, a memory system is required to have a large capacity and a high processing speed. For this reason, a multi-chip module (MCM) in which a plurality of bare chips are mounted on a substrate having substantially the same size as a packaging substrate is becoming widespread. By using this multi-chip module, it is possible to reduce the mounting area in size and weight, to achieve high-density wiring, to ensure high performance and high speed by bare chip mounting, and to ensure high reliability.

By the way, the packaged memory I
When C is mounted on various types of boards, noise such as overshoot in the signal waveform that rises or falls sharply and a rebound wave due to undershoot and undershoot occurs, or when the I / O signal rises or falls Noise sometimes occurs due to a drop in power supply voltage due to a large power supply current flowing sometimes. Since these noises may cause malfunctions, it is necessary to take measures to reduce the noises. In particular, since a DRAM performs a storage operation by charging and discharging a capacitor, a signal waveform at that time has a very steep rising and falling, and large noise is generated. Therefore, noise countermeasures are important.

As a countermeasure against noise of the memory IC, a method of mounting a damping resistor or a bypass capacitor (pass capacitor) on various substrates on which the memory IC is mounted has been widely used. However, considering the case where a memory chip is mounted on the above-described multi-chip module, it is necessary to prepare a damping resistor or decap for each memory chip and mount it on various substrates. It is necessary to mount a large number of damping resistors and decaps necessary for noise suppression together, which complicates the mounting process. In addition, noise suppression is performed on the board on which the module is mounted, but it is desirable to mount a decap at a position as close as possible to the memory chip with respect to a decrease in power supply voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a noise countermeasure for each memory chip on a module substrate, and to mount the module substrate on various substrates. An object of the present invention is to provide a memory module that can simplify a mounting process including a noise suppression component at the time.

[0007]

In order to solve the above-mentioned problems, a memory module according to the present invention is connected in series to a memory chip mounted on a module substrate and a chip pad formed on the memory chip. And a resistor mounted on the module substrate, and a signal is input / output to / from the memory chip via the resistor. Specifically, a resistor is inserted into a signal line connecting between an external connection terminal formed on the module substrate and a pad for a substrate formed on the module substrate for making an electrical connection with a memory chip. ing.

The above-described resistor functions as a damping resistor. By inserting such a resistor into a signal line, the rising and falling of the signal waveform becomes gentle.
The occurrence of noise such as a rebound wave due to overshoot or undershoot and undershoot is reduced. Further, the above-described resistor can be easily mounted on the module substrate by inserting it into a signal line between a substrate pad formed on the module substrate and an external connection terminal. In particular, when a DRAM is used for a memory chip, D
Since a RAM performs a storage operation by charging and discharging a capacitor, a signal waveform when reading and writing data has a steep rising and falling, but by inputting and outputting a signal through the above-described resistor, these signals are output. The signal waveform becomes gentle, and the occurrence of noise can be reduced.

Further, in the memory module of the present invention, a capacitor is connected between a chip pad corresponding to a power supply terminal formed on a memory chip and a chip pad corresponding to a ground terminal. With this capacitor, even when a large power supply current flows at the time of rising or falling of the input / output signal, a decrease in the power supply voltage can be suppressed, so that generation of noise is reduced. The above-mentioned capacitor includes a signal line such as a conductive pattern for connecting an external connection terminal corresponding to a power supply terminal formed on the module substrate and a board pad corresponding to the power supply terminal formed on the module substrate, and a signal line formed on the module substrate. By inserting it between the external connection terminal corresponding to the ground terminal and the signal line such as a conductive pattern for connecting the board pad corresponding to the ground terminal formed on the module substrate, the module can be easily mounted on the module substrate. Can be implemented.

In this way, noise countermeasures for each memory chip on the module substrate can be taken. In addition, since it is not necessary to mount a damping resistor or a bypass capacitor for noise suppression on various substrates on which the memory module is mounted, a process of mounting the memory module on various substrates can be simplified.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory module according to an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a diagram schematically showing one surface of a memory module according to one embodiment. As shown in FIG. 1, memory bare chips 1 as four memory chips individually cut out from a semiconductor wafer are COB (Chip On Chip) on one surface of a module substrate 2 by wire bonding.
Board) has been implemented. The memory bare chip 1 is, for example, a DRAM having a capacity of 4M × 4 bits.
Each of the memory bare chips 1 has a rectangular shape, and chip pads 3 are formed in a line at the center along a long side thereof.

The module substrate 2 is made of an SO-DIMM (Sm
all Outline Dual Inline Memory Module) It has an external dimension that can be mounted on a board or the like, and a plurality of board pads 4 are formed in the center substantially in a row substantially parallel to the long side. Also, two memory bare chips 1 are mounted on both sides of the plurality of substrate pads 4, and the direction in which the plurality of substrate pads 4 are arranged and the plurality of chip pads 3 formed in the memory bare chip 1 are arranged. The directions are almost parallel. In other words, the plurality of substrate pads 4 are provided on the module substrate 2 between the two memory bare chips 1 arranged such that the longer sides thereof are adjacent to each other so as to be parallel to the respective plurality of chip pads 3. Are formed.

The chip pads 3 and the substrate pads 4 are connected by bonding wires 5. The substrate pads 4 include ones connected to two bonding wires 5 and ones connected to the bonding wires 5. Terminals commonly connected to a plurality of memory bare chips 1, such as address terminals of the memory bare chip 1. Is the board pad 4
By connecting a plurality of bonding wires 5 to each other, the board pads 4 are shared.

Further, on the module substrate 2, a plurality of damping resistors 6 are mounted near the short side and four decaps 7 are mounted in order to take measures against noise described later. One bypass capacitor 7 is connected to each memory bare chip 1. A plurality of external connection terminals 8 formed in a concave shape are provided on the outer surface of the short side of the module substrate 2. By pouring solder into these external connection terminals 8, the memory module 10 uses the so-called LCC (Leadless Chip Carrier) method to
It is mounted on various substrates such as an O-DIMM substrate.

Next, measures against noise of the memory module 10 will be described. FIG. 2 is an enlarged perspective view of a portion of the module substrate 2 where the damping resistor 6 is formed.
As shown in FIG.
Are electrically connected to each other by bonding wires 5 and conductive patterns 9 via substrate pads 4, and the external connection terminals 8 are electrically connected to signal lines 11 of various substrates such as an SO-DIMM substrate. Connected.

Further, the memory module 10 of the present embodiment
In FIG. 2, as shown in FIG. 2, a conductive pattern 9 serving as a signal line connecting the substrate pad 4 and the external connection terminal 8 is formed.
, A damping resistor 6 is inserted. Since the rise and fall of the signal waveform can be moderated by the damping resistor 6, it is possible to reduce the occurrence of noise due to overshoot, a rebound wave due to undershoot and undershoot, and the like.

FIG. 3 is an enlarged perspective view of a portion of the module substrate 2 where the bypass capacitor 7 is formed. As shown in the figure, the chip pads 3 and the external connection terminals 8 include:
A terminal Vdd (power supply terminal) for providing a power supply voltage and a terminal Vss (ground terminal) for providing a ground level are included. Between the chip pad 3 corresponding to the power supply terminal Vdd and the external connection terminal 8 corresponding to the power supply terminal Vdd, or between the chip pad 3 corresponding to the ground terminal Vss and the external connection terminal 8 corresponding to the ground terminal Vss. Are connected by bonding wires 5 and conductive patterns 9 via substrate pads 4 respectively.

By the way, when the input / output signal rises or falls, a large power supply current flows due to charging / discharging of the through current and the parasitic capacitance inside and outside the memory bare chip 1, so that the power supply voltage decreases and noise occurs. I do.
When the power supply voltage decreases, the operation margin of the memory decreases, and therefore, it is necessary to take measures against this noise.

Therefore, the memory module 1 of the present embodiment
0, as shown in FIG. 3, a conductive pattern 9 as a signal line connecting the external connection terminal 8 corresponding to the power supply terminal Vdd and the substrate pad 4 corresponding to the power supply terminal Vdd,
The external connection terminal 8 corresponding to the ground terminal Vss and the ground terminal Vss
A decap 7 is inserted between the substrate and the conductive pattern 9 as a signal line for connecting to the substrate pad 4 corresponding to. By inserting the decap 7, even when a large power supply current flows at the time of rising or falling of the input / output signal, the decap 7 supplies electric charge,
Since a decrease in the power supply voltage can be suppressed, the occurrence of noise can be reduced. As a capacitor used for the bypass capacitor 7, a ceramic capacitor is used for relatively high frequency noise, and a solid tantalum capacitor is used for relatively low frequency noise.

A chip element is used for the damping resistor 6 and the bypass capacitor 7 described above, and an SMT (Surface Mo
unt Technology), and is mounted on the module substrate 2 via a solder paste or the like.

FIG. 4 shows a memory module 1 according to this embodiment.
0 is a circuit diagram of FIG. In this figure, some terminals are omitted for simplification. As shown in the figure, the connection between each terminal of each memory bare chip 1 and each terminal of the external connection terminal is such that each of the address terminals A0 to A10 is commonly connected to the external connection terminals ADR0 to ADR10, and the control terminal R
AS is connected to the external connection terminal RE, the control terminal WE is connected to the external connection terminal WE, and the control terminal OE is connected to the external connection terminal OE. On the other hand, each memory bare chip 1
, The data terminals I / O0 to I / O3 are separately connected to the external connection terminals D0 to D15, the power supply terminal Vdd is separately connected to the external connection terminal Vdd, and the ground terminal Vss is separately connected to the external connection terminal Vss. It is connected.

Each terminal of each memory bare chip 1
Except for the signal line between the power supply terminal Vdd and the external connection terminal Vdd and the signal line between the ground terminal Vss and the external connection terminal Vss, the damping resistor 6 is inserted in the signal line between the external connection terminals. The signal line between Vdd and the external connection terminal Vdd and the signal line between the ground terminal Vss terminal and the external connection terminal Vss
They are connected by a bypass capacitor 7. The above-described noise is reduced by the damping resistor 6 and the bypass capacitor 7.

As described above, in the memory module 10 of the present embodiment, the damping resistor 6 and the bypass capacitor 7 necessary for the noise countermeasure of the memory bare chip 1 are mounted on the module substrate 2 to reduce the noise of the memory bare chip 1. Is going. Also, since the damping resistance 6 and the bypass capacitor 7 are mounted on the module substrate 2 to take measures against noise, the damping resistance and the noise reduction for various measures such as SO-DIMM board on which the memory module 10 is mounted are mounted. There is no need to implement decaps, and memory module 1
The step of mounting the O. 0 on various substrates such as an SO-DIMM substrate can be simplified.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. In the above-described embodiment, one pass capacitor 7 is connected to each memory bare chip 1, but one pass capacitor 7 may be shared by a plurality of memory bare chips 1. However, since the role of the bypass capacitor 7 is to supply a charge and suppress a decrease in the power supply voltage, it is not desirable to share the bypass capacitor 7 with too many memory bare chips 1.

In the above embodiment, the damping resistors 6 are connected to all the terminals except the power supply terminal and the ground terminal. However, only the data terminals I / O0 to I / O3 of each memory bare chip 1 are connected. The damping resistor 6 may be connected correspondingly. In particular, when a DRAM is used for the memory bare chip 1, as described above,
Since the storage operation is performed by charging and discharging the capacitor, the signal waveform when reading and writing data has a sharp rise and fall. Therefore, noise countermeasures can also be taken by connecting the damping resistor 6 in correspondence with only the data terminal.

In the above-described embodiment, an example in which four memory bare chips 1 are mounted on the module substrate 2 has been described. However, the number of memory bare chips 1 mounted on the module substrate 2 is limited to four. Not done. However, in ordinary computer equipment, the memory capacity is often set to a multiple of 4, and therefore, it is desirable that the number of memory bare chips 1 mounted on the module substrate be an even number. Also in this case, as described above, it is desirable to connect one bypass capacitor 7 to each bare chip 1 for memory.

In the embodiment described above, the memory bare chip 1 is mounted on the module substrate 2 by COB mounting by wire bonding. However, flip-chip mounting may be performed. In this case, since the mounting density can be increased as compared with COB mounting by wire bonding, the outer dimensions of the memory module 10 can be reduced.

In the embodiment described above, the substrate pads 4 are formed so as to be sandwiched between the two memory bare chips 1, but the substrate pads 4 may be formed outside the memory bare chips 1. In the embodiment described above,
DRA as bare chip 1 for memory on module substrate 2
M has been described as an example, but SRAM or flash R
It is also possible to mount another type of memory bare chip 1 such as an OM or a bare chip other than a memory.

In the above-described embodiment, an example in which the memory bare chip 1 is mounted on the module substrate 2 by COB mounting has been described, but the memory bare chip 1 is mounted on a glass substrate.
In this case, so-called COG (Chip On Glass) mounting may be performed, and the material of the module substrate 2 may be appropriately changed.

FIGS. 5 to 14 show modified examples of the memory module. In these drawings, attention is paid to the arrangement state of the memory bare chip 1 and the wiring state by the bonding wires 5, and the damping resistor 6 and the bypass capacitor 7 are omitted. As shown in FIG. 5, the bonding wires 5 may be alternately drawn out from the memory bare chips 1 arranged on both sides with respect to the substrate pads 4 formed in a line in the center of the module substrate 2.
Alternatively, as shown in FIG. 6, the bonding wires 5 are alternately drawn in units of plural wires, or as shown in FIG. 7, two or more rows (two rows in FIG. 6) of substrate pads 4 formed on the module substrate 2. May be connected to the bonding wire 5.

As shown in FIGS. 8 and 9, chip pads 3 are formed in two rows along the long side of the memory bare chip 1, and the bonding wires 5 are drawn out on both sides of each memory bare chip 1. As shown in FIGS. 10 to 13, chip pads 3 may be formed in two rows along the short side of the bare memory chip 1, and the bonding wires 5 may be drawn out on both sides of each bare memory chip 1. . In addition, as shown in FIG.
May be used to configure a memory module.

As shown in FIG. 15, pads 4 'are formed on the module substrate 2 at the same intervals as the pads on the memory bare chip 1, and these pads 4' and the pads on the memory bare chip 1 are formed. The flip-chip mounting may be performed by arranging the pads to face each other. When flip-chip mounting is performed using a memory bare chip as shown in FIG. 11, the mounting state may be unstable.
Alternatively, as shown in (b), it is desirable to form several pads near the short side of each memory bare chip.

When the chip pads 3 are formed in a line on the memory bare chip, they are formed in a stepwise manner as shown in FIG. Is also good.

[0035]

As described above, according to the present invention, a resistor is connected in series to a chip pad formed on a memory chip, and a rising or falling edge of a signal waveform input / output via this resistor. Since the falling is gentle, the occurrence of noise such as a rebound wave due to overshoot, undershoot, and undershoot is reduced.

Further, according to the present invention, a capacitor is connected between a chip pad corresponding to a power supply terminal formed on a memory chip and a chip pad corresponding to a ground terminal, and a rise of an input / output signal is provided. Even when a large power supply current flows at the time of falling or at the time of falling, noise is reduced because the supply of electric charge by discharging by the capacitor suppresses a reduction in the power supply voltage.

In this way, noise countermeasures for each memory chip on the module substrate can be taken. In addition, since it is not necessary to mount a damping resistor or a bypass capacitor for noise suppression on various substrates on which the memory module is mounted, a process of mounting the memory module on various substrates can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a memory module according to an embodiment.

FIG. 2 is an enlarged perspective view of a portion of the memory module shown in FIG. 1 on which a damping resistor is mounted.

3 is an enlarged perspective view of a portion of the memory module shown in FIG. 1 on which a bypass capacitor is mounted.

FIG. 4 is a circuit diagram of the memory module shown in FIG. 1;

FIG. 5 is a diagram showing a modification of the memory module.

FIG. 6 is a diagram showing another modification of the memory module.

FIG. 7 is a diagram showing another modified example of the memory module.

FIG. 8 is a diagram showing another modification of the memory module.

FIG. 9 is a diagram showing another modified example of the memory module.

FIG. 10 is a diagram showing another modification of the memory module.

FIG. 11 is a diagram showing another modified example of the memory module.

FIG. 12 is a diagram showing another modification of the memory module.

FIG. 13 is a diagram showing another modification of the memory module.

FIG. 14 is a diagram showing another modification of the memory module.

FIG. 15 is a diagram showing another modified example of the memory module.

FIG. 16 is a diagram showing a modified example of a memory bare chip.

FIG. 17 is a diagram showing another modified example of the memory bare chip.

[Explanation of symbols]

 Reference Signs List 1 bare chip for memory 2 module board 3 pad for chip 4 pad for board 5 bonding wire 6 damping resistor 7 decap (bypass capacitor) 8 external connection terminal 9 conductive pattern 10 memory module 11 signal lines of various boards

Claims (5)

[Claims] 1. A memory chip cut out from a semiconductor wafer, a module substrate on which the memory chip is mounted, and mounted in series on the module substrate and connected in series to chip pads formed on the memory chip. A memory module, comprising: a resistor; 2. The substrate according to claim 1, wherein the resistor is formed on the module substrate to make an electrical connection between an external connection terminal formed on the module substrate and the chip pad. A memory module, which is inserted into a signal line connecting between the memory module and a pad. 3. The memory module according to claim 1, wherein a DRAM is used as the memory chip. 4. A memory chip cut out of a semiconductor wafer, a module substrate on which the memory chip is mounted, and a chip pad mounted on the module substrate and corresponding to a power supply terminal formed on the memory chip. A capacitor connected between the chip pad corresponding to the ground terminal and a chip pad. 5. The signal according to claim 4, wherein the capacitor connects an external connection terminal corresponding to a power supply terminal formed on the module substrate to a board pad corresponding to a power supply terminal formed on the module substrate. And a signal line connecting between an external connection terminal corresponding to a ground terminal formed on the module substrate and a board pad corresponding to a ground terminal formed on the module substrate. And a memory module.