JP2009134794A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of exactly evaluating a data rewriting property of a magnetoresistive element by a simple configuration. <P>SOLUTION: The semiconductor device 101 includes: a write-in current line DL having a first terminal and second terminal to be supplied with a first voltage, in which the write-in current for writing the data flows into the magnetoresistive element S when the data are written and the direction of this write-in current is independent of logic values of write-in data; a transistor TRD having a first continuity electrode combined to the second terminal of the write-in current line DL and a second continuity electrode to be supplied with a second voltage and generating a magnetic field to exert on magnetization of the magnetoresistive element S by bringing the write-in current flow into the write-in current line DL when the data are written; a first pad PD1 to be supplied with the first voltage; a second pad PD4 to be supplied with the second voltage; and third pads PD2, PD3 for supplying a third voltage to other circuits prepared in the semiconductor device 101. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a transistor that supplies a current for writing data to a magnetoresistive element through a write current line.

  MRAM (Magnetic Random Access Memory) is a general term for a solid-state memory that stores data using the magnetization direction of a ferromagnetic material. In the MRAM, “1” and “0” correspond to whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or antiparallel to a certain reference direction. In addition, a GMR element using a giant magnetoresistance effect (Giant Magneto Resistive effect) in reading data from a memory cell, and a magnetic tunnel effect (Tunneling Magneto effect: TMR) An MTJ (Magnetic Tunneling Junction) element or the like that utilizes the (resistive) effect) is used in the MRAM.

  The MTJ element is composed of a three-layer film of ferromagnetic layer / insulating layer / ferromagnetic layer, and a tunnel current flows through the insulating layer. The resistance value to the tunnel current changes according to the relationship between the magnetization directions of the two ferromagnetic layers.

  Here, as a method of reversing the magnetization direction of the ferromagnetic layer, there is known an external magnetization reversal method in which a current is passed in the vicinity of the memory cell to generate an external magnetic field and the magnetization direction of the ferromagnetic layer is reversed. . However, in the external magnetization reversal method, a memory cell that is located on one of a bit line and a digit line corresponding to the memory cell to be written and is not to be written (hereinafter also referred to as a half-selected memory cell). May malfunction due to the influence of an external magnetic field.

  A toggle method is known as a method for writing data to a memory cell to solve such a problem. In the toggle method, an MTJ element is composed of a fixed layer that is a ferromagnetic layer whose magnetization direction is fixed, a free layer that is a ferromagnetic layer capable of changing the magnetization direction, and an insulating layer. Has been. The free layer in the toggle system has a SAF (Synthetic Anti-Ferromagnetic coupling) structure. That is, the free layer includes a pair of ferromagnetic layers that are magnetized in opposite directions to each other and a nonmagnetic layer formed between the pair of ferromagnetic layers. Then, in order to change the magnetization direction of the free layer, two magnetic fields are generated by passing a current through the bit line and the digit line. By shifting the timing of current flow through the bit line and the digit line, the magnetization of the pair of ferromagnetic layers is rotated in the direction of the combined magnetization vector by the two magnetic fields, and the magnetization is reversed (toggling). In the toggle method, magnetization reversal (toggling) does not occur in principle only by the magnetic field generated by the current flowing through one wiring, so that the magnetization of the memory cell in the half-selected state is prevented from malfunctioning due to the magnetic field. Can do.

  For example, Non-Patent Document 1 discloses the following MRAM. That is, the MRAM includes an MTJ element, a bit line, a digit line, a bit line driver, and a digit line driver.

  The bit line is disposed above the MTJ element. The bit line is used as a current line for flowing a write current in a direction corresponding to the logical value of the write data when writing data. The MTJ element is arranged so that its easy axis is substantially perpendicular to the bit line.

  The bit line driver is disposed at both ends of the bit line and includes a P-channel MOS transistor and an N-channel MOS transistor, and at the time of data writing, a write current in a direction corresponding to the logical value of the write data is supplied to the bit line.

  The digit line is arranged below the MTJ element. The digit line is arranged substantially perpendicular to the hard axis of the MTJ element so that a magnetic field is applied in the direction of the hard axis of the MTJ element by a write current that flows during data writing.

The digit line driver passes a write current through the digit line when writing data. Here, the direction of the write current passed through the digit line at the time of data writing does not depend on the logical value of the write data, and therefore is one direction in normal use of the MRAM. For this reason, as shown in FIG. 5 of Non-Patent Document 1, a digit line driver is connected to one end of the digit line, and a power supply voltage VCC common to other circuits such as a bit line driver is supplied to the other end. Is done.
Takaharu Tsuji et al. "A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture", 2004 Symposium on VLSI Circuits Digest of Technical Papers pp.450-453

  By the way, the data rewriting characteristic of the MTJ element is evaluated using, for example, an asteroid curve indicating the magnitude of a magnetic field necessary for reversing the magnetization direction of the MTJ element. Based on the degree of inclination of the asteroid curve, the positional deviation of the MTJ element, bit line and digit line is measured. In order to accurately determine whether the inclination of the asteroid curve is caused by this positional deviation or due to magnetic field leakage from the fixed layer of the MTJ element, a digit line is used. Preferably, a bidirectional current is passed through and an asteroid curve corresponding to the bidirectional current is drawn.

  However, in the MRAM described in Non-Patent Document 1, since the current can flow only in one direction through the digit line due to the configuration as described above, the factor of the inclination of the asteroid curve cannot be accurately determined. Although the digit line driver has the same configuration as the bit line driver, bidirectional current can flow through the digit line, but the layout area increases due to the increase in the number of transistors.

  Therefore, an object of the present invention is to provide a semiconductor device capable of accurately evaluating the data rewriting characteristics of a magnetoresistive element with a simple configuration.

  In summary, a semiconductor device according to an embodiment of the present invention includes a write current line whose write current direction does not depend on a logic value of write data, and a first conductive electrode coupled to the second end of the write current line. And a transistor that generates a magnetic field that acts on the magnetization of the magnetoresistive element by flowing a write current through the write current line when writing data. The first end of the write current line and the second conduction electrode of the transistor are electrically separated from nodes connected to other circuits in the semiconductor device.

  According to the embodiment of the present invention, the write current can be set in both directions, and other circuits in the semiconductor device can be normally operated regardless of the direction of the write current.

  Therefore, the data rewriting characteristics of the magnetoresistive element can be accurately evaluated with a simple configuration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor device according to an embodiment of the present invention.

  Referring to FIG. 1, semiconductor device 101 is, for example, an MRAM, a control circuit 5 that controls the overall operation of semiconductor device 101 in response to a control signal CMD, and MTJ memory cells MC that are integrated and arranged in a matrix. (Hereinafter also simply referred to as memory cell MC), row selection circuits 20, 21, column decoder 25, read / write control circuits 30, 35, a plurality of word lines WL, and a plurality of digits. A line DL, a plurality of bit lines BL, and a plurality of source lines SL are provided.

  Hereinafter, the rows and columns of the plurality of memory cells MC that are integrated and arranged in a matrix included in the memory array 10 are also referred to as memory cell rows and memory cell columns, respectively.

  The row selection circuits 20 and 21 perform a memory cell row selection operation in the memory array 10 to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 performs a memory cell column selection operation in the memory array 10 to be accessed based on the column address CA included in the address signal ADD.

  The read / write control circuits 30 and 35 are provided on both sides of the memory array 10 and write data to the memory cell MC based on the input data DIN. The read / write control circuits 30 and 35 read data from the memory cell MC and output it as read data DOUT to the outside.

  Word line WL, digit line DL, and source line SL are provided corresponding to the memory cell rows, respectively. Bit line BL is provided corresponding to the memory cell column. FIG. 1 representatively shows one memory cell MC, and shows one word line WL and one digit line DL corresponding to the memory cell row of each memory cell MC. Further, one bit line BL is representatively shown corresponding to the memory cell column of the memory cells MC.

  FIG. 2 is a schematic configuration diagram of the memory array 10 and its peripheral circuits according to the embodiment of the present invention. In FIG. 2, the vertical direction on the paper corresponds to a memory cell row, and the horizontal direction on the paper corresponds to a memory cell column.

  Referring to FIG. 2, memory array 10 includes memory cells MC integrated and arranged in a matrix.

  In FIG. 2, representatively, memory cells MC0 to MC5, bit lines BL0 to BL2 provided corresponding to the memory cell columns, word lines WL0 to WL3 provided corresponding to the memory cell rows, and digit lines, respectively. DL0, DL1 and source line SL are shown.

  Memory cells MC0 to MC5 include MTJ elements (magnetoresistive elements) S0 to S5 and cell transistors TRS0 to TRS5, respectively.

  Row selection circuit 20 includes a digit line driver DLDV. Digit line driver DLDV includes N-channel MOS transistors TRD0 and TRD1. Row selection circuit 21 is connected to power supply node VCC to which power supply voltage VCC is supplied. Here, since the N channel MOS transistor has a larger current driving capability per gate width than the P channel MOS transistor, a relatively large amount of current can flow through the digit line DL with a small layout area. However, digit line driver DLDV may include a P channel MOS transistor instead of an N channel MOS transistor.

  The read / write control circuit 30 includes a bit line driver BLDV1. The read / write control circuit 35 includes a bit line driver BLDV2 and data read circuits RDC1 and RDC2. Bit line driver BLDV1 includes P channel MOS transistors TRB0, TRB4, TRB8 and N channel MOS transistors TRB1, TRB5, TRB9. Bit line driver BLDV2 includes P channel MOS transistors TRB2, TRB6, TRB10 and N channel MOS transistors TRB3, TRB7, TRB11.

  Hereinafter, each of MTJ elements S0 to S5 is referred to as MTJ element S, each of cell transistors TRS0 to TRS5 is referred to as cell transistor TRS, each of N channel MOS transistors TRD0 and TRD1 is referred to as N channel MOS transistor TRD, and N channel Each of MOS transistors TRB1, TRB3, TRB5, TRB7, TRB9, TRB11 is referred to as an N channel MOS transistor TRB, and each of P channel MOS transistors TRB0, TRB2, TRB4, TRB6, TRB8, TRB10 is referred to as a P channel MOS transistor TRB. There is.

  Digit lines DL0 and DL1 have a first end connected to power supply node VCC, and a second end. A write current IWDL for writing data to the memory cell MC flows through the digit lines DL0 and DL1 when data is written. Further, the direction of the write current IWDL does not depend on the logical value of the write data.

  In digit line driver DLDV, N channel MOS transistor TRD0 has a drain connected to the second end of digit line DL0 and a source connected to ground node DLVSS to which ground voltage DLVSS is supplied. N-channel MOS transistor TRD1 has a drain connected to the second end of digit line DL1, and a source connected to ground node DLVSS.

  N-channel MOS transistors TRD0 and TRD1 generate a data write magnetic field that acts on the magnetization of MTJ elements S0 to S5 by flowing write current IWDL through digit lines DL0 and DL1 during data write.

  In bit line driver BLDV1, P channel MOS transistor TRB0 has a source connected to power supply node VDD, a drain connected to bit line BL0, and a gate. N-channel MOS transistor TRB1 has a source connected to ground node VSS to which ground voltage VSS is supplied, a drain connected to bit line BL0, and a gate connected to the gate of P-channel MOS transistor TRB0. P-channel MOS transistor TRB4 has a source connected to power supply node VDD, a drain connected to bit line BL1, and a gate. N-channel MOS transistor TRB5 has a source connected to ground node VSS, a drain connected to bit line BL1, and a gate connected to the gate of P-channel MOS transistor TRB4. P-channel MOS transistor TRB8 has a source connected to power supply node VDD, a drain connected to bit line BL2, and a gate. N-channel MOS transistor TRB9 has a source connected to ground node VSS, a drain connected to bit line BL2, and a gate connected to the gate of P-channel MOS transistor TRB8.

  In bit line driver BLDV2, P channel MOS transistor TRB2 has a source connected to power supply node VDD, a drain connected to bit line BL0, and a gate. N channel MOS transistor TRB3 has a source connected to ground node VSS, a drain connected to bit line BL0, and a gate connected to the gate of P channel MOS transistor TRB2. P-channel MOS transistor TRB6 has a source connected to power supply node VDD, a drain connected to bit line BL1, and a gate. N-channel MOS transistor TRB7 has a source connected to ground node VSS, a drain connected to bit line BL1, and a gate connected to the gate of P-channel MOS transistor TRB6. P-channel MOS transistor TRB10 has a source connected to power supply node VDD, a drain connected to bit line BL2, and a gate. N-channel MOS transistor TRB11 has a source connected to ground node VSS, a drain connected to bit line BL2, and a gate connected to the gate of P-channel MOS transistor TRB10.

  In memory cell MC0, MTJ element S0 has a first end connected to bit line BL0, and a second end. Cell transistor TRS0 has a gate connected to word line WL0, a drain connected to the second end of MTJ element S0, and a source connected to source line SL. In memory cell MC1, MTJ element S1 has a first end connected to bit line BL0, and a second end. Cell transistor TRS1 has a gate connected to word line WL2, a drain connected to the second end of MTJ element S1, and a source connected to source line SL. In memory cell MC2, MTJ element S2 has a first end connected to bit line BL1, and a second end. Cell transistor TRS2 has a gate connected to word line WL1, a drain connected to the second end of MTJ element S2, and a source connected to source line SL. In memory cell MC3, MTJ element S3 has a first end connected to bit line BL1, and a second end. Cell transistor TRS3 has a gate connected to word line WL3, a drain connected to the second end of MTJ element S3, and a source connected to source line SL. In memory cell MC4, MTJ element S4 has a first end connected to bit line BL2, and a second end. Cell transistor TRS4 has a gate connected to word line WL0, a drain connected to the second end of MTJ element S4, and a source connected to source line SL. In memory cell MC5, MTJ element S5 has a first end connected to bit line BL2, and a second end. Cell transistor TRS5 has a gate connected to word line WL2, a drain connected to the second end of MTJ element S5, and a source connected to source line SL.

  The data read circuit RDC1 is connected to the bit lines BL0 and BL1. The data read circuit RDC2 is connected to the bit line BL2. Source line SL is connected to ground node VSS.

  The MTJ element S changes its electrical resistance value according to the magnetization direction corresponding to the logical value of the stored data.

  Digit line driver DLDV causes write current IWDL to flow through digit lines DL0 and DL1, respectively, based on row address RA included in address signal ADD during data writing.

  More specifically, when data is written, the N-channel MOS transistor TRD corresponding to the selected memory cell row is turned on by receiving a logic high level voltage at the gate, thereby supplying power through the digit line DL corresponding to the selected memory cell row. A write current IWDL flows from node VCC to ground node DLVSS.

  The bit line drivers BLDV1 and BLDV2 use the ground voltage VSS supplied from the ground node VSS and the power supply voltage VDD supplied from the power supply node VDD based on the column selection result by the column decoder 25 when writing data. A write current IWBL is supplied through .about.BL2. The bit line drivers BLDV1 and BLDV2 flow a write current IWBL for writing data to the memory cells MC0 to MC5 through the bit lines BL0 to BL2, and flow a write current IWBL in a direction corresponding to the logical value of the write data.

  More specifically, for example, when the logical value of the write data is “0”, in bit line driver BLDV1, N channel MOS transistor TRB corresponding to the selected memory cell column receives a logic high level voltage at its gate. Turn on. In the bit line driver BLDV2, the P-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic low level voltage. Then, the write current IWBL flows from the bit line driver BLDV2 to the bit line driver BLDV1 through the bit line BL.

  On the other hand, when the logical value of the write data is “1”, in the bit line driver BLDV1, the P-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic low level voltage. In the bit line driver BLDV2, the N-channel MOS transistor TRB corresponding to the selected memory cell column is turned on when the gate receives a logic high level voltage. Then, the write current IWBL flows in the direction from the bit line driver BLDV1 to the bit line driver BLDV2 through the bit line BL.

  The word lines WL0 to WL3 are driven to a logic high level based on the row selection results by the row selection circuits 20 and 21 when reading data. Then, the cell transistor TRS corresponding to the selected memory cell row is turned on when the gate receives a logic high level voltage. The data read circuit RDC reads the read current to the source line SL via the bit line BL corresponding to the selected memory cell column, the MTJ element S corresponding to the selected memory cell row and the selected memory cell column, and the cell transistor TRS in the on state. Run IR. The data read circuit RDC reads data stored in the memory cells MC corresponding to the selected memory cell row and the selected memory cell column based on the amount of the read current IR.

  FIG. 3 is a diagram showing a voltage supplied from the outside and a voltage supply pad at the time of evaluating data rewrite characteristics of the semiconductor device according to the embodiment of the present invention.

  Referring to FIG. 3, semiconductor device 101 includes pads PD1 to PD4 arranged on semiconductor chip CP.

  A voltage V1 from the external power source PSV1 is supplied to the pad PD1. Pad PD1 is connected to power supply node VCC.

  The voltage V2 from the external power supply PS is supplied to the pad PD2. Pad PD2 is connected to power supply node VDD.

  The ground voltage VSS is supplied to the pad PD3. Pad PD3 is connected to ground node VSS.

  A voltage V3 from the external power source PSV2 is supplied to the pad PD4. Pad PD4 is connected to ground node DLVSS.

  Next, evaluation using an asteroid curve in the semiconductor device according to the embodiment of the present invention will be described.

  FIG. 4 is a diagram showing an example of the positional relationship among MTJ elements, bit lines, and digit lines in the semiconductor device according to the embodiment of the present invention. FIG. 5 is a diagram showing an asteroid curve measured in the case of the positional relationship shown in FIG. FIG. 6 is a diagram showing an example of the positional relationship among MTJ elements, bit lines, and digit lines in the semiconductor device according to the embodiment of the present invention. FIG. 7 is a diagram showing an asteroid curve measured in the case of the positional relationship shown in FIG.

  First, when the curves LN1 and LN2 are obtained, similarly to the normal use of the semiconductor device 101, the power supply voltage VCC is supplied to the pad PD1, the power supply voltage VDD is supplied to the pad PD2, and the ground voltage is supplied to the pad PD3. VSS is supplied, and the ground voltage VSS is supplied to the pad PD4. In this case, write current IWDL flows from power supply node VCC to ground node DLVSS through digit line DL corresponding to the selected memory cell row.

  Next, when obtaining the curves LN3 and LN4, the ground voltage VSS is supplied to the pad PD1, the power supply voltage VDD is supplied to the pad PD2, the ground voltage VSS is supplied to the pad PD3, and the pad PD4 is supplied. A power supply voltage VCC is supplied. Here, the power supply voltage VCC is a positive voltage, and is set to a voltage value in consideration of the parasitic resistance of the digit line DL and the like. In this case, a write current IWDL flows from the ground node DLVSS to the power supply node VCC through the digit line DL corresponding to the selected memory cell row.

  As shown in FIG. 4, when the positional relationship among the MTJ element S, the bit line BL, and the digit line DL is normal, that is, the hard axis of magnetization of the MTJ element is substantially perpendicular to the digit line DL, and the bit line BL Are substantially parallel to each other with respect to the write current IWBL axis and the write current IWDL axis, as shown in FIG.

  On the other hand, as shown in FIG. 6, when the positional relationship among the MTJ element S, the bit line BL, and the digit line DL is shifted, that is, the hard axis of the MTJ element is not substantially perpendicular to the digit line DL. If the bit line BL is not substantially parallel to the bit line BL, as shown in FIG. 7, curves LN1 to LN4 that are asymmetric with respect to the axis of the write current IWBL and the axis of the write current IWDL are obtained.

  Here, although the positional relationship among the MTJ element S, the bit line BL, and the digit line DL is normal, when there is a magnetic field leakage from the fixed layer of the MTJ element, for example, among the curves LN1 to LN4, the curve LN1, Although LN2 is mutually targeted with respect to the axis of the write current IWDL, the curves LN1, LN2 and the curves LN3, LN4 are asymmetric with respect to the axis of the write current IWBL. In this case, with the curves LN1 and LN2 alone, the inclination of the asteroid curve is caused by the positional relationship between the MTJ element, the bit line BL, and the digit line DL, or the magnetic field leakage from the fixed layer of the MTJ element. It is difficult to determine whether it is caused by the problem.

  However, in the semiconductor device according to the embodiment of the present invention, the write current IWDL is caused to flow from the ground node DLVSS in the direction opposite to the normal use to the power supply node VCC through the digit line DL corresponding to the selected memory cell row. it can. With such a configuration, not only the curves LN1 and LN2 but also the curves LN3 and LN4 can be obtained. Therefore, the inclination of the asteroid curve is caused by the positional relationship between the MTJ element, the bit line BL, and the digit line DL. It is possible to accurately determine whether there is a magnetic field leakage from the fixed layer of the MTJ element or the like.

  In the semiconductor device according to the embodiment of the present invention, the power supply wiring connected to the source of the N-channel MOS transistor TRD in the digit line driver DLDV is a transistor included in another circuit in the semiconductor device 101 such as the bit line driver BLDV. Different from the power supply wiring connected to the conductive electrode. In other words, ground node DLVSS is electrically isolated from the power supply node connected to other circuits in semiconductor device 101, and the supply voltage to ground node DLVSS and other circuits other than N-channel MOS transistor TRD are connected. It can be set separately from the supply voltage. With such a configuration, circuits other than the digit line driver DLDV can be operated normally regardless of the setting of the voltage supplied to the digit line driver DLDV.

  In the semiconductor device according to the embodiment of the present invention, digit line driver DLDV is configured to include one N-channel MOS transistor for each digit line DL. Therefore, the digit line driver is the same as the bit line driver. There is no need for a configuration, and an increase in layout area can be prevented.

  Therefore, the semiconductor device according to the embodiment of the present invention can accurately evaluate the data rewriting characteristics of the magnetoresistive element with a simple configuration.

  FIG. 8 is a plan view showing a completed semiconductor package in the semiconductor device according to the embodiment of the present invention. FIG. 9 is a cross-sectional view showing a completed semiconductor package in the semiconductor device according to the embodiment of the present invention.

  8 and 9, semiconductor device 101 includes a semiconductor chip CP, an outer lead (external terminal) OR, an inner lead IR, and a die pad DP. The die pad DP also functions as an electrode for ground potential. The semiconductor chip CP is bonded (die bonding) on the die pad DP.

  A bonding wire WR is bonded to the bonding pad and the inner lead IR in the semiconductor chip CP, that is, wire bonding is performed. The inner lead IR and the outer lead OR may be bonded or integrated.

  The semiconductor chip CP is resin-sealed by, for example, a transfer molding method. The outer lead OR is plated by lead-free plating or the like mainly containing tin. The outer lead OR is bent.

  The bonding pad PD1 is connected to the external terminal EXT1. The bonding pad PD2 is connected to the external terminal EXT2. Bonding pads PD3 and PD4 are commonly connected to external terminal EXT3.

  Here, while the semiconductor chip is mounted on the silicon wafer, the MTJ element is evaluated, while the semiconductor chip on the silicon wafer is packaged by dicing or the like, as shown in FIGS. However, the MTJ element may not be evaluated.

  In this case, the pad PD4 needs to supply both the power supply voltage and the ground voltage when the MTJ element is evaluated. However, after the MTJ element is evaluated, the pad PD4 may be supplied with the same ground voltage as the pad PD3. Therefore, when the semiconductor package is manufactured, the external terminals of the semiconductor device can be reduced by connecting the pads PD3 and PD4 to the common external terminal EXT3.

  In the normal use of the semiconductor device 101, when the same power supply voltage as that of the pad PD2 may be supplied to the pad PD1, the pads PD1 and PD2 may be connected to a common external terminal.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of a semiconductor device according to an embodiment of the present invention. 1 is a schematic configuration diagram of a memory array 10 and peripheral circuits thereof according to an embodiment of the present invention. It is a figure which shows the voltage supplied from the outside and the pad for voltage supply at the time of evaluation of the data rewriting characteristic of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows an example of the positional relationship of an MTJ element, a bit line, and a digit line in the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the asteroid curve measured in the case of the positional relationship shown in FIG. It is a figure which shows an example of the positional relationship of an MTJ element, a bit line, and a digit line in the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the asteroid curve measured in the case of the positional relationship shown in FIG. In the semiconductor device concerning an embodiment of the invention, it is a top view showing a completed semiconductor package. In the semiconductor device concerning an embodiment of the invention, it is a sectional view showing a completed semiconductor package.

Explanation of symbols

  5 control circuit, 10 memory array, 20, 21 row selection circuit, 25 column decoder, 30, 35 read / write control circuit, 45, 50 row driver, 101 semiconductor device, WL, WL0 to WL3 word line, DL, DL0, DL1 digit line, BL, BL0 to BL2 bit line, SL source line, MC0 to MC5, MC memory cell, S0 to S5, S MTJ element (magnetoresistance element), TRS0 to TRS5, TRS cell transistor, DLDV digit line driver, TRD0, TRD1, TRD N channel MOS transistor, BLDV1, BLDV2 bit line driver, RDC data read circuit, TRB0, TRB4, TRB8, TRB2, TRB6, TRB10, TRB P channel MOS transistor, TRB1, TR 5, TRB9, TRB3, TRB7, TRB11, TRB N-channel MOS transistor.

Claims (3)

A semiconductor device,
A magnetoresistive element whose electrical resistance value changes according to the magnetization direction corresponding to the logical value of the stored data;
A first end to which a first voltage is supplied and a second end are provided. During data writing, a first write current for writing data into the magnetoresistive element flows, and the first write current A first write current line whose direction does not depend on the logical value of the write data;
A first conduction electrode coupled to the second end of the first write current line; and a second conduction electrode to which a second voltage is supplied. When writing data, the first write current line A transistor that generates a magnetic field acting on the magnetization of the magnetoresistive element by flowing the write current;
A first pad to which the first voltage is supplied;
A second pad to which the second voltage is supplied;
A semiconductor device comprising: a third pad for supplying a third voltage to another circuit provided in the semiconductor device. The semiconductor device further includes:
2. The semiconductor device according to claim 1, further comprising an external terminal to which one of the first pad and the second pad and the third pad are connected in common. The first write current line is disposed substantially perpendicular to the hard axis of magnetization of the magnetoresistive element;
The semiconductor device further includes:
A second write current line disposed substantially perpendicular to the first write current line;
Based on the supplied third voltage, a second write current for writing data to the magnetoresistive element is passed through the second write current line, and the second write current is applied in a direction corresponding to the logical value of the write data. A semiconductor device according to claim 1, further comprising a driver for passing a write current of 2.

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