JP2005050424A - Change in resistance type storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a variable resistance value storage device capable of exactly writing data and exactly reading the data irrespective of variation in memory cell characteristics. <P>SOLUTION: Data writing is carried out by changing writing conditions by a writing condition setting circuit (5) after reading written data under control of a writing control circuit (4) at the time of the data writing of a variable resistive element type memory cell (M) of a memory cell array (1). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a resistance-change memory device including a variable resistance element whose electrical resistance value is set according to stored data as a constituent element of a memory cell, and more particularly to a configuration for improving the write characteristics of a memory cell. About.

  In recent years, thin film magnetic memory and phase change memory have attracted attention as memories for storing data in a nonvolatile manner.

  The memory cell of the thin-film magnetic memory includes a free layer whose magnetization direction is determined by an applied magnetic field, a fixed magnetic layer having a constant magnetization direction independent of the applied magnetic field, A variable magnetoresistive element including a barrier insulating film between the free magnetic layer and the fixed magnetic layer is included.

  When the magnetization direction of the free magnetic layer and the fixed magnetic layer is the same, the electrical resistance value of the data storage unit is the lowest, and when the magnetization direction of the free magnetic layer and the fixed magnetic layer is different, the electrical resistance value is high. Become. By utilizing this magnetoresistance effect, data can be read from the memory cell by supplying current to the path of the free magnetic layer and the fixed magnetic layer of the memory cell and detecting the amount of current flowing therethrough.

  At the time of data writing, a current is passed through digit lines and write bit lines arranged orthogonal to each other corresponding to the memory cells, and a magnetic field induced by the currents flowing through these digit lines and write bit lines is induced. The magnetization direction of the free magnetic layer is set by the combined magnetic field. By setting the magnetization direction of the combined magnetic field according to the write data, the magnetization direction of the free magnetic layer can be set to a high resistance state and a low resistance state according to the write data.

  For the phase change memory, a phase change material whose crystal state is set to an amorphous (non-crystalline) state or a crystalline state according to the stored data is used for data storage. This phase change material exhibits a lower electrical resistance in the crystalline state than in the amorphous state. Therefore, an electric current is passed through a heater arranged in the vicinity of the phase change material, and the phase change material is rapidly heated and cooled by the Joule heat, or is rapidly heated and decooled. The state or the crystalline state can be set.

  Since the electrical resistance value varies depending on the crystal state, the electrical resistance value is made to correspond to the stored data.

  At the time of data reading, also in the phase change memory, data is read by passing a current through the memory cell and detecting the amount of the current.

The writing and reading of data in such a phase change memory are described in Patent Document 1 (Special Table 2003-502791) and Non-Patent Document 1 (ISSOC Digest of Technical Papers M. Jill et al., “Ovonic Unified Memory: It is shown in a paper entitled "High-Performance Non-Volatile Memory Technology for Standalone Memory and Embedded Applications".
Special table 2003-502791 2002 IEEE ISSCC Digest of Technical Papers February 2002 Session 12 Lecture Number 12.4

  In both the thin-film magnetic memory and the phase change memory, a write current is used when writing data. In a magnetic memory, a digit line write current is normally supplied to a digit line in a fixed direction, and a write bit line current is supplied to a write bit line in a direction corresponding to write data. The combined magnetic field strength of the magnetic field induced by each of these digit line write current and bit line write current is variable magnetic such as an MTJ (magnet-tunnel-junction) element or TMR (tunnel-magnet-resistance) element of the memory cell. When the threshold value of the resistance element is exceeded, magnetization reversal occurs and data can be rewritten.

  The bit line write current and the digit line write current are measured for each chip so that the magnetization state of the adjacent non-selected memory cell is not reversed by the leakage magnetic field and the magnetization reversal is surely generated in the selected memory cell. The size is adjusted and set.

  However, on the chip, the operating characteristics of the memory cells vary within a certain range in the memory cell array. Therefore, when the write current is set for each chip, the write current is set assuming the worst case, and therefore it is required to set the write current with a large margin. In this case, since the threshold value for magnetization reversal differs depending on the operating characteristics, an unnecessarily large write current flows to a memory cell having a small magnetization reversal threshold value, and the threshold for magnetization reversal In a memory cell having a large value, there is a case where magnetization reversal is not sufficiently caused. At the time of data reading, data is read by comparing the amount of current flowing through the memory cell in the high resistance state or the low resistance state with a reference value. Therefore, in the memory cell in which such insufficient magnetization reversal is caused, the difference from the reference value at the time of data reading is small, the reading margin is reduced, and data cannot be read accurately.

  In particular, when the number of data rewrites increases and the characteristics of the magnetic film of the memory cell deteriorate, in such a memory cell with a small read margin, reverse data may be read, and the number of memory cell rewrite cycles is reduced. However, there arises a problem that the lifetime of the entire memory is shortened.

  Also in the phase change memory, since Joule heat is used for the change in crystallinity of the phase change film, the problem of deterioration of film characteristics becomes more remarkable due to the thermal cycle of the phase change material.

  In the above-mentioned patent document 1, after applying a reset pulse for setting a high resistance state in accordance with the memory cell state and write data, a set pulse for setting the resistance state is applied, or the state of the memory cell is written. There is shown a method of applying a set pulse or a reset pulse only to a memory cell that requires a state change without applying a pulse when it corresponds to embedded data. It prevents the set pulse from being continuously applied to the memory cell, prevents the crystal nucleus of the phase change film of the memory cell from growing, and thereby prevents the deterioration of the characteristics of the phase change film. Plan.

  However, also in this Patent Document 1, the conditions of the set pulse and the reset pulse applied as the write pulse to the memory cell are fixed throughout the chip, and the characteristics of the phase change film of the memory cell vary. The problem of the decrease in the write margin and the decrease in the read margin due to the variation in resistance value due to the above is not considered.

  In the above-mentioned Non-Patent Document 1, voltage waveforms in the apparatus when data writing / reading / reverse data writing / reading operation cycles are repeatedly executed are shown. However, this non-patent document 1 only shows that data can be written / read internally at a low voltage, and variations in memory cell characteristics in the memory array and the lifetime of the memory cell are shown. The problem of characteristic deterioration such as is not considered.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a resistance value change type memory device capable of accurately writing and reading data.

  Another object of the present invention is to provide a variable resistance memory device capable of ensuring a sufficient data writing and reading margin.

  A variable resistance memory device according to a first aspect of the present invention includes a plurality of memory cells including a plurality of variable resistance elements whose electrical resistance values are set according to stored data, and a selection memory of the plurality of memory cells. Write circuit for writing data to selected memory cell when writing data to cell, program memory for storing data write condition, and write according to write condition stored in program memory for data write A circuit write condition is set, and data written by the write circuit is read from the selected memory cell to determine whether the read data corresponds to the write data. It includes a write control circuit that re-activates the write circuit by changing the condition, and stores the write condition at that time in the program memory when the determination result shows good.

  A variable resistance memory device according to a second aspect of the present invention includes a plurality of memory cells each including a variable resistance element in which an electrical resistance value is set according to stored data, an internal data bus, and a plurality of memories. A selection circuit that couples a selected memory cell of the cell to an internal data bus, a reference resistance element having a known resistance value, and an internal read that generates internal read data according to a current flowing through the selected memory cell and a current flowing through the reference resistance element Provide circuit.

  By storing the write condition in the program memory, data can be written under the optimum or close write condition according to the selected memory cell. Further, data can be accurately written by performing a write verify operation on the write data and selectively rewriting the data in accordance with the verify result. Further, by changing the write condition at this time, it is possible to prevent the write stress from being applied to the selected memory cell more than necessary.

  Further, when the internal resistance data is generated by comparing the current between the reference resistance element and the selected memory cell, the resistance value of the reference resistance element is set according to the resistance value distribution of the memory cells in the memory cell array. Thus, data can be read with a sufficient read margin.

  In addition, by changing the resistance value of the reference resistance element according to the selected memory cell, data can be accurately read during the write verify operation, and a sufficient read margin is ensured to accurately write data. The data can be verified.

[Embodiment 1]
FIG. 1 is a diagram schematically showing an overall configuration of a resistance value change memory device according to the present invention. In FIG. 1, the resistance value change type memory device is a memory cell array 1 having a plurality of normal memory cells M arranged in a matrix, and a write operation that performs operations related to data writing in selected memory cells of the memory cell array 1. And a read related circuit 2 that performs an operation related to reading data of a selected memory cell of memory cell array 1 at the time of data read.

  The normal memory cell M is a variable resistance element whose electrical resistance changes according to stored data, and a data storage unit is configured. The variable resistance element may be a variable magnetoresistive element such as a TMJ element or an MTR element, or may be a PC (phase change) element.

  Write system circuit 2 supplies a write current to a selected memory cell of memory cell array 1 in accordance with write data D and address signal AD. Write circuit 2 includes a circuit that selects a row and a column of the memory cell and supplies a write current to the memory cell in the selected row and the selected column, although the configuration differs depending on the configuration of normal memory cell M. .

  Read system circuit 3 includes a decode circuit for generating a signal for selecting a memory cell in accordance with address signal AD at the time of data reading, and a selection circuit for selecting a memory cell in accordance with a selection signal from this decode circuit and coupling it to the internal data bus. And a sense amplifier for detecting and amplifying data on the internal data bus.

  The memory device is further coupled to the read circuit 3 via the switch circuit (SW) 9 at the time of data writing, determines whether or not data is correctly written to the selected memory cell, and determines in accordance with the determination result. Under the control of the write control circuit 4, a write condition setting circuit 5 for resetting the write condition in the case of a data write failure, and data writing And a main control circuit 8 for executing operations necessary for reading.

  The write control circuit 4 determines that a write failure occurs when the expected value data (write data) and the data read from the read system circuit 3 via the switch circuit (SW) 9 do not match during data writing. The write condition in the write system circuit 2 is changed, and the changed write condition is set in the write condition setting circuit 5. After resetting the write condition, the write control circuit 4 controls the main control circuit 8 to execute the data write operation again.

  By changing the write condition according to the result of the notch verification, data can be written accurately even when the characteristics of the normal memory cell M in the memory cell array 1 vary. In particular, the regular memory cell M includes a variable resistance element in the storage unit, and by setting the electrical resistance value of the variable resistance element to a predetermined resistance value according to the write data, the memory cell characteristics vary. Regardless, the variable resistance element of the normal memory cell M can be set to a state having an electrical resistance value corresponding to the write data. Thus, accurate data reading can be performed even during data reading, and the reading margin is improved.

  Switch circuit (SW) 9 is also coupled to input / output circuit 7. Input / output circuit 7 generates external data Q (DQ) from data read from read system circuit 3 at the time of data reading, and generates internal write data D by receiving data from the outside at the time of data writing.

  FIG. 2 shows an example of the configuration of normal memory cell M used in the first embodiment of the present invention. In FIG. 2, normal memory cell M electrically connects variable magnetoresistive element VMR whose electrical resistance value is set according to stored data and variable magnetoresistive element VMR to source line SL according to a signal on (read) word line WL. Includes a read select transistor RTR coupled to.

  The variable magnetoresistive element VMR is composed of an MTJ element or a TMR element, and a combined magnetic field H of magnetic fields induced by a bit line write current IBL flowing through the bit line BL and a digit line write current IDL flowing through the digit line DL, respectively, The magnetization state is set. This variable magnetoresistive element has either a large tunnel current state or a small tunnel current state, that is, a large electrical resistance state or a small electrical resistance state, depending on the magnetization directions of the free magnetic layer and the fixed magnetic layer. It has the state of.

  In the variable magnetoresistive element VMR, the magnetization state is reversed when the applied magnetic field intensity exceeds the magnetization reversal threshold value. When the electric resistance value of variable magnetoresistive element VMR is different from the resistance value corresponding to the write data, that is, when the write verify result indicates failure, bit line write current IBL and digit line By changing the condition (current amount or current application time) of the write current IDL, the strength or application time of the combined magnetic field H is changed. By changing the write condition and performing rewriting, the variable magnetoresistive element VMR can be accurately set to a state corresponding to the write data.

  FIG. 3 is a diagram showing the configuration of the storage device shown in FIG. 1 in more detail. In FIG. 3, bit lines BL0-BLm are provided corresponding to each column of normal memory cells M in memory cell array 1, and word lines WL0-WLm and digit lines DL0- are provided corresponding to each row of normal memory cells M. DLm is disposed. Corresponding to each row of normal memory cells M, dummy memory cells DMC0 and DMC1 are alternately arranged. A dummy digit line DDL is commonly provided corresponding to the dummy memory cells DMC0 and DMC1, a dummy word line DWL0 is provided corresponding to the dummy memory cell DMC0, and a dummy word corresponding to the dummy memory cell DMC1. Line DWL1 is provided.

  The dummy memory cell DMC0 is selected when the dummy word line DWL0 is selected, and the dummy memory cell DMC1 is selected when the dummy word line DWL1 is selected. These normal memory cell M and dummy memory cells DMC0 and DMC1 have the same configuration as that of normal memory cell M shown in FIG. In FIG. 3, these normal memory cells M and dummy memory cells DMC0 and DMC1 are indicated by ellipses in order to avoid complexity of the drawing. These dummy memory cells DMC0 and DMC1 store logic level determination reference data when data is read from normal memory cell M.

  Write condition setting circuit 5 shown in FIG. 1 includes a write voltage generation circuit 15 that changes the voltage level of write voltage VPP in accordance with multi-bit voltage step control signal STEP from write control circuit 4. Write voltage VPP includes a digit line write voltage VPPD used for driving a digit line and a bit line write voltage VPPB used for driving a bit line.

  Write system circuit 2 is provided for digit lines DL0-DLm and dummy digit line DDL, receives write voltage VPPD from write voltage generation circuit 15 as an operating power supply voltage during data writing, and selects a digit line Digit line drive circuit 20 for supplying current to bit lines and bit lines BL0-BLn. When data is written, write voltage VPPB from write voltage generation circuit 15 is received as an operation power supply voltage, and selected bit line Includes a bit line driving circuit 22 for passing a current in a direction corresponding to the write data.

  Digit lines DL0-DLm and DDL are coupled to the ground node, and digit line drive circuit 20 supplies write voltage VPPD to the selected digit line to the selected digit line, thereby supplying write voltage VPPD supply node (digit line). The digit line write current flows from the operation power supply node of the drive circuit to the ground node. The wiring resistance of the digit line is constant, and the magnitude of the digit line writing current flowing through the selected digit line can be changed by changing the voltage level of the write voltage VPPD, and the digit line is induced accordingly. The strength of the magnetic field can be changed.

  Bit line drive circuit 22 causes a current to flow through the selected bit line in the direction corresponding to the write data between the write voltage VPPB supply node (the operation power supply node of the bit line drive circuit) and the ground node. The wiring resistance of the bit line is fixed, and the magnitude of the bit line write current can be changed by changing the voltage level of the write voltage VPPB, and accordingly, the strength of the magnetic field induced by the bit line Can be changed.

  Read circuit 3 selects one of word lines WL0 to WLm and one of dummy word lines DWL0 and DWL1 to a selected state, and selects a bit line forming a pair of bit lines BL0 to BLn. A read column selection circuit 32 coupled to the internal data bus 36 and a sense amplifier 34 for detecting and amplifying data on the internal data bus 36 are included.

  As will be described in detail later, internal data bus 36 is formed of complementary data lines, and word line driving circuit 30 makes a pair of normal memory cell M and dummy memory cell DMC0 or DMC1 at the time of data reading. The bit lines (simultaneously connected to the complementary internal data lines) are simultaneously selected to form a current path. Dummy memory cells DMC0 and DMC1 drive a current intermediate between currents driven by normal memory cells in the high resistance state and the low resistance state. The read column selection circuit 32 couples the paired bit lines to the complementary data line of the internal data bus 36, and the sense amplifier 34 sets the resistance state of the selected memory cell to the high resistance state according to the magnitude of the current. Or low resistance state.

  The dummy memory cells DMC0 and DMC1 are different in size (cross-sectional area) from the normal memory cells, and are set to a high resistance state or a low resistance state according to the cross-sectional area so as to drive an intermediate current (reference current). It may be configured.

  In the data write mode, the output data of the sense amplifier 34 is transmitted to the write control circuit 4 by the switch circuit (SW) 9. The write control circuit 4 compares the read data with the write data (expected value data), and generates a multi-bit voltage step control signal STEP based on the comparison result.

  When data writing, data writing, internal reading of write data, determination of coincidence / non-coincidence, and rewrite write sequence based on the determination result cause variations in memory cell characteristics In this case, data can be accurately written in the memory cell.

  At the time of normal data reading for reading stored data to the outside, the switch circuit (SW) 9 transmits the output data of the sense amplifier 34 to an output buffer included in the input / output circuit 7 shown in FIG.

Configuration of write voltage generation circuit 15 1:
FIG. 4 is a diagram showing an example of the configuration of write voltage generation circuit 15 shown in FIG. Write voltage generation circuit 15 includes a circuit for generating digit line write voltage VPPD and bit line write voltage VPPB. Since these circuits have the same configuration, in FIG. 4, a portion for generating write voltage VPP is provided. Is representatively shown.

  In FIG. 4, a write voltage generation circuit 15 compares a reference voltage generation circuit 15a that generates a reference voltage VREF with a reference voltage VREF and a write voltage VPP (VPPD, VPPB) on the write voltage line 15b. 15b and a current drive transistor 15c for supplying current from the power supply node to write voltage line 15d in accordance with the output signal of comparator 15b.

  In reference voltage generating circuit 15a, the voltage level of generated reference voltage VREF is set in accordance with voltage step control signal STEP from write control circuit 4 shown in FIG. As the configuration of the reference voltage generation circuit 15a, in the case of a circuit configuration in which a constant current is converted into a voltage by a resistance element, the resistance value of the current / voltage conversion resistance element is adjusted by a voltage step control signal STEP. A switching element that receives the step control signal STEP is provided together with the unit resistance element, and the resistance value is adjusted by selectively short-circuiting the unit resistance element. Alternatively, the constant current generating circuit may be configured by a current mirror circuit, and the voltage level of the reference voltage VREF may be changed by adjusting the mirror ratio with the voltage step control signal STEP.

  In the write voltage generation circuit 15 shown in FIG. 4, when the voltage level of the write voltage VPP becomes higher than the reference voltage VREF, the voltage level of the output signal of the comparator 15b increases, and the current drive transistor 15c is turned off. Thus, the current supply to the write voltage line 15d is stopped. On the other hand, when the write voltage VPP becomes a voltage level lower than the reference voltage VREF, the comparator 15b outputs a signal corresponding to the difference, increases the conductance of the current drive transistor 15c, and writes The current supplied from the current drive transistor 15c to the voltage line 15b increases. Therefore, the voltage level of write voltage VPP is maintained at the voltage level of reference voltage VREF. By changing the voltage level of the reference voltage VREF according to the voltage step control signal STEP, the voltage level of the write voltage VPP can be changed.

Configuration 2 of the write voltage generation circuit 15:
FIG. 5 is a diagram showing another configuration of write voltage generation circuit 15 shown in FIG. In FIG. 5, a write voltage generation circuit 15 includes a reference voltage generation circuit 15e that generates a reference voltage VREF0, a level shift circuit 15f that generates a shift voltage VPSF by level shifting the write voltages VPP (VPPD, VPPB), and the like. A comparator 15g that compares the reference voltage VREF0 and the level shift voltage VPSF, and a current drive transistor 15h that supplies a current to the write voltage line 15d according to the output signal of the comparator 15g.

  The voltage level of the reference voltage VREF0 generated by the reference voltage generation circuit 15e is fixed. The voltage level shift amount of level shift circuit 15f is set according to voltage step control signal STEP (STEP <k: 0>) from write control circuit 4 shown in FIG. The level shift circuit 15f includes a series body of resistance elements or diode elements, and selectively short-circuits these resistance elements or diode elements in accordance with the voltage step control signal STEP <k: 0>, whereby the voltage of the shift voltage VPSF is obtained. Set the level.

  In the configuration of write voltage generation circuit 15 shown in FIG. 5, comparator 15g controls conduction / non-conduction of current drive transistor 15h so that the voltage levels of shift voltage VPSF and reference voltage VREF0 are equal. . Therefore, the voltage level of the write voltage VPP can be changed by adjusting the level shift amount in the level shift circuit 15f by the voltage step control signal STEP <k: 0> (the write voltage VPP is the reference voltage VREF0). Is set to a voltage level higher than the shift voltage in the level shift circuit 15f).

Configuration 3 of the write voltage generation circuit 15:
FIG. 6 is a diagram showing still another configuration of write voltage generation circuit 15 shown in FIG. In FIG. 6, write voltage generation circuit 15 is activated when activation signal ENA is activated, and lowers power supply voltage VCC to generate write voltage VPP (VPPD, VPPB) on write voltage line 15d. The circuit 40a includes a booster circuit 40b that is activated when the activation signal ENB is activated and boosts the power supply voltage VCC to generate the write voltage VPP (VPPD, VPPB) on the write voltage line 15d.

  Voltage step-down circuit 40a is set to the voltage level of write voltage VPP generated in accordance with multi-bit voltage step control signal STEPA from write control circuit 4. As the configuration of the step-down circuit 40a, the circuit configurations shown in FIGS. 4 and 5 can be used.

  Booster circuit 40b detects a charge pump circuit 41 that generates a voltage higher than power supply voltage VCC by the charger pump operation of the capacitor when activated, and detects the level of the voltage generated by charger pump circuit 41, and the charge pump according to the detection result. A level detection circuit 42 for controlling the operation of the circuit 41 is included. The detection voltage level of level detection circuit 42 is set according to multi-bit voltage step control signal STEPB from write control circuit 4. Level detection circuit 42 performs a level detection operation when activation signal ENB is active, and maintains charger pump circuit 41 in an inactive state when activation signal ENB is inactive.

  Output nodes of step-down circuit 40a and step-up circuit 40b are commonly coupled to write voltage line 15d.

  In the write voltage generation circuit 15 shown in FIG. 6, when a write voltage VPP higher than the power supply voltage VCC is required, the write voltage is generated by the booster circuit 40b, and the write voltage lower than the power supply voltage VCC. Is required, the step-down circuit 40a is activated to generate the write voltage VPP. By selectively switching the circuit for generating the write voltage, the write conditions can be changed over a wide range, and accurate data writing can be ensured.

Configuration of digit line drive circuit 20 1:
FIG. 7 is a diagram showing an example of the configuration of digit line drive circuit 20 shown in FIG. FIG. 7 representatively shows the configuration of digit line drive 20a provided for digit line DL. Digit line driver 20a is formed of a P channel MOS transistor 20aa for supplying a current to digit line DL from a voltage supply node for supplying digit line write voltage VPPD in accordance with a decode signal from a decoder (not shown).

  The other end of digit line DL is coupled to a ground node. Therefore, the current determined by digit line write voltage VPPD and the wiring resistance of digit line DL is supplied by digit line driver 20a as the digit line write current due to the inherent wiring resistance of digit line DL. By changing the voltage level of digit line write voltage VPPD, it is therefore possible to change the magnitude of the current flowing through digit line DL.

  In the configuration of the digit line driver shown in FIG. 7, an N channel MOS transistor which is in a conductive state complementary to P channel MOS transistor 20aa is provided between digit line DL and the ground node in accordance with an output signal from the decoder. May be.

Configuration 2 of digit line drive circuit 20:
FIG. 8 is a diagram showing another configuration of digit line drive circuit 20 shown in FIG. FIG. 8 also representatively shows the configuration of digit line driver 20 b provided for digit line DL of digit line drive circuit 20. Digit line DL is coupled to a write voltage VPPD supply node (write voltage line 15d). Digit line driver 20b includes an N channel MOS transistor 20bb for coupling digit line DL to a ground node in accordance with a selection signal from a decoder (not shown).

  When selected, digit line driver 20b discharges current from digit node write voltage VPPD supply node to ground node via digit line DL. Therefore, when the voltage level of digit line write voltage VPPD is changed, the amount of current flowing through digit line DL is also changed accordingly.

Configuration of the bit line driving circuit 22:
FIG. 9 is a diagram more specifically showing the configuration of bit line drive circuit 22 shown in FIG. In the memory cell array 1, normal memory cells M and dummy memory cells DMCa and DMCb are arranged in a matrix. FIG. 9 representatively shows normal memory cells M and dummy memory cells DMC0 and DMC1 arranged in two columns.

  The bit line BL is formed in a hierarchical structure of the main bit line MBL and the sub bit line SBL. FIG. 9 shows sub bit lines SBL0 and SBL1, and main bit lines MBL0 and MBL1 arranged corresponding to these sub bit lines SBL0 and SBL1. A normal memory cell M and a dummy memory cell DMC0 aligned in the column direction are connected to the sub bit line SBL0. A normal memory cell M and a dummy memory cell DMC1 aligned in the column direction are connected to the sub bit line SBL1.

  Corresponding to each row of normal memory cells M, digit lines DL0-DLm and word lines WL0-WLm are arranged, respectively. The dummy memory cells DMC0 and DMC1 are commonly provided with a dummy digit line DDL, the dummy memory cell DMC0 is connected to the dummy word line DWL0, and the dummy memory cell DMC1 is connected to the dummy word line DWL1. In the normal memory cell and the dummy memory cell, each access transistor is commonly connected to the source line SL.

  Bit line drive circuit 22 designates main bit line drivers 50e and 50o transmitting bit line write voltage VPPB to main bit lines MBL0 and MBL1, and write data D and odd / even columns in accordance with a decode signal (not shown). Write subdecoder 52l for generating decode signals SD0L and SD1L according to address bit A0, write subdecoder 52r for generating subdecode signals SD0r and SD1r according to complementary write data / D and address bit A0, main The sub bit line driver 54le charges or discharges the sub bit line SBL0 in accordance with the voltage on the bit line MBL0 and the sub decode signal SD0L, and the sub bit line driver 54le in phase with the sub decode signal SD0r and the voltage on the main bit line MBL0. The sub bit line driver 54re for charging or discharging the sub bit line SBL0, the sub bit line driver 54lo for charging or discharging the sub bit line SBL according to the sub decode signal SD1l and the voltage on the main bit line MB1, and the main bit line MBL1 Sub-bit line driver 54ro for discharging or charging sub-bit line SBL1 complementarily to sub-bit line driver 54lo according to the voltage and sub-decode signal SD1r is included.

  Main bit line drivers 50e and 50o are simultaneously selected when data is written in accordance with a decode signal (not shown), and transmit bit line write voltage VPPB onto corresponding main bit lines MBL0 and MBL1 when selected.

  Write sub-decoders 52l and 52r select one of sub-bit lines SBL0 and SBL1 according to address bit A0 and perform sub-flow so that current flows through the sub-bit line in the direction defined by write data D according to write data D and / D. Decode signals SD01, SD11, SD1r, and SD0r are generated.

  When not selected, sub bit lines SBL0 and SBL1 are maintained at the ground voltage level, and main bit lines MBL0 and MBL1 are maintained in a high impedance state at the ground voltage level.

  In the configuration of bit line drive circuit 22 shown in FIG. 9, bit line write voltage VPPB is transmitted to selected sub-bit lines via main bit line drivers 50e and 50l. Sub-bit line drivers 54le, 54re, 54lo and 54ro drive current from the voltage source supplying bit line write voltage VPPB to the ground node in the selected sub-bit line. Therefore, the current in selected sub bit line SBL can be changed according to the voltage level of bit line write voltage VPPB, and the induced magnetic field strength in selected sub bit line can be changed accordingly.

Detailed configuration of bit line drive circuit:
FIG. 10 is a diagram more specifically showing the configuration of the main bit line driver, the sub bit line driver and the write sub decoder shown in FIG. 10 also shows configurations of read column selection circuit 32 and write control circuit 4 shown in FIG.

  In FIG. 10, main bit line driver 50e includes a P channel MOS transistor PQ1 that selectively transmits write voltage VPP onto main bit line MBL0 in accordance with an output signal of gate circuit G1, and a main bit in accordance with an output signal of gate circuit G2. N channel MOS transistor NQ1 discharging line MBL0 to the ground voltage level is included. Gate circuits G1 and G2 are output stage circuits of a decode circuit provided in the previous stage of main bit line driver 50e.

  Main bit line driver 50o couples main bit line MBL1 to the ground node according to the output signal of P channel MOS transistor PQ2 transmitting write voltage VPP to main bit line MBL1 according to the output signal of gate circuit G3 and gate circuit G4. N channel MOS transistor NQ2 to be included. Gate circuits G3 and G4 are output stage circuits of a decode circuit provided in the previous stage of main bit line driver 50o.

  Gate circuits G1 and G3 supply a bit line write current (write voltage) to the corresponding main bit line when selected according to the decode signal, and gate circuits G2 and G4 perform one-shot when the write operation is completed. A signal for driving the corresponding main bit line to the ground voltage level is generated. These gate circuits G2 and G4 may generate a signal so as to drive the corresponding main bit line to the ground voltage according to the timing signal, independently of the decode signal. Gate circuits G1-G4 generate a signal for setting the corresponding main bit line to a high impedance state during data writing.

  The same selection signal is applied to main bit line drivers 50e and 50o by gate circuits G1 to G4, and main bit lines MBL0 and MBL1 are simultaneously driven to a selected state during data writing. Main bit lines MBL0 and MBL1 are arranged for sub-bit lines SBL0 and SBL1, respectively, as described later. When data is read, these main bit lines MBL0 and MBL1 are complementary data lines of internal data bus 36. It is because it couple | bonds with 30a and 30b, respectively.

  Write subdecoder 52l receives address bit A0 and write data D and generates subdecode signal SD01, and receives sub-address signal / A0 and data D and generates subdecode signal SD11. Including a gate circuit GA1. Gate circuit GA0 drives subdecode signal SD01 to L level when address bit A0 is "0" (L level) and data D is "1" (H level). Gate circuit GA1 drives subdecode signal SD1l to L level when both address bit / A0 and data D are "1".

  Write subdecoder 52r receives complementary address bit / A0 and complementary write data / D to generate a gate circuit GB0 for generating subdecode signal SD0r, and receives address bit A0 and complementary write data / D. Includes a gate circuit GB1 for generating a subdecode signal SD1r. Gate circuit GB0 drives subdecode signal SD0r to L level when complementary address bit / A0 and complementary write data / D are both "1". Gate circuit GB1 drives subdecode signal SD1r to L level when both address bit A0 and complementary write data / D are "1".

  Sub-bit line driver 54le has a P-channel MOS transistor PQ3 coupling main bit line MBL0 to sub-bit line SBL0 when sub-decode signal SD01 is at L level, and sub-bit line SBL0 to ground node when sub-decode signal SD01 is at H level. And an N channel MOS transistor NQ3 coupled to.

  Sub-bit line driver 54lo has a P-channel MOS transistor PQ4 that couples main bit line MBL1 to sub-bit line SBL1 when sub-decode signal SD1l is at L level, and sub-bit line SBL1 to ground node when sub-decode signal SD1l is at H level. Includes an N channel MOS transistor NQ4 coupled to.

  Sub-bit line driver 54re includes P-channel MOS transistor PQ5 that couples main main bit line MBL0 to sub-bit line SBL0 according to sub-decode signal SD1r, and N-channel MOS transistor NQ5 that couples sub-bit line SBL0 to the ground node according to sub-decode signal SD1r. Including.

  Sub-bit line driver 54ro includes a P-channel MOS transistor PQ6 coupling main main bit line MBL1 to sub-bit line SBL1 according to sub-decode signal SD1r, and an N-channel MOS transistor NQ6 coupling sub-bit line SBL1 to the ground node according to sub-decode signal SD1r. Including.

  One of sub bit lines SBL0 and SBL1 is designated by address bit A0. Consider a state where both data D and address bit A0 are “1”. In this case, in write sub-decoder 52l, sub-decode signal SD1l from gate circuit GA1 is at L level, and sub-decode signal SD01 from gate circuit GA0 is at H level. Therefore, in sub bit line driver 54lo, P channel MOS transistor PQ4 is rendered conductive and transmits write voltage VPP from main bit line MBL1 to sub bit line SBL1. In sub bit line driver 54le, MOS transistor PQ3 is off and MOS transistor NQ3 is on, and sub bit line SBL0 is maintained at the ground voltage level.

  On the other hand, in write subdecoder 52r, complementary write data / D is "0", and subdecode signals SD0r and SD1r are both at the H level. Therefore, sub bit lines SBL0 and SBL1 are coupled to the ground node by sub bit line drivers 54re and 54ro. In sub bit line SBL1, write voltage VPP is supplied from main bit line MBL1 via P channel MOS transistor PQ4, and this supply voltage is discharged by N channel MOS transistor NQ6 of sub bit line driver 54ro to sub bit line SBL1. A bit line write current flows from the sub bit line driver 54L0 to the sub bit line driver 54r0.

  Conversely, when address bit A0 is “1” and data D is “0”, MOS transistors NQ3 and NQ4 are both turned on in sub bit line drivers 54le and 50lo (subdecode signals SD0l and SD1l are both in the same state). H level), sub-bit lines SBL0 and SBL1 are coupled to the ground node. For sub bit line drivers 54re and 54ro, complementary write data / D is "1", so that sub decode signal SD1r is at L level and sub decode signal SD0r is at H level. In sub bit line driver 54ro, P channel MOS transistor PQ6 is turned on, and write voltage VPP on main bit line MBL1 is transmitted to sub bit line SBL1. In sub bit line driver 54re, MOS transistor NQ5 is on, MOS transistor PQ5 is off, sub bit line SBL0 is maintained at the ground voltage level, and no write current flows. The sub bit line SBL1 is supplied with current from the sub bit line driver 54ro, and the supply current is discharged by the sub bit line driver 54lo, so that the bit line write current flows in the opposite direction from when the data D is "1". Can do.

  The magnitude of this sub bit line write current is determined by the voltage level of bit line write voltage VPPB transmitted on the selected main bit line, and the sub bit line is changed by changing the voltage level of bit line write voltage VPPB. The magnitude of the flowing write current can be changed, and the sub-bit line induced magnetic field native region can be changed accordingly.

  When main bit lines MBL0 and MBL1 are in a non-selected state and are at the ground voltage level, for example, even if sub decode signal SD01 is at L level, both the gate and source of P channel MOS transistor PQ3 are in sub bit line driver 54le. It becomes the ground voltage level and is turned off. At this time, sub decode signal SD0r is at the H level, and sub bit line SBR0 is maintained at the ground voltage level by N channel MOS transistor NQ5 in sub bit line driver 54re. The same applies to other sub-bit line drivers. Therefore, it is possible to prevent sub bit lines SBL0 and SBL1 from entering a floating state.

  Main bit line drivers 50e and 50o are set to the output high impedance state during data reading. At the time of data reading, subdecode signals SD1r, SD0r, SD0l and SD1l are all set to L level, and P channel MOS transistors PQ3, PQ5P, Q4 and PQ6 are turned on in sub bit line drivers 54le, 54re, 54lo and 54ro. Then, sub bit lines SBL0 and SBL1 are coupled to main bit lines MBL0 and MBL1, respectively.

  In main bit line drivers 50b and 50o, the output signals of gate circuits G1 and G3 are changed in accordance with the address signal. On the other hand, the output signals of gate circuits G2 and G4 are set to the H level in the form of one shot when the data write operation is completed. Set. The output signals of gate circuits G1 and G3 are at L level after completion of the data write cycle. Therefore, main bit lines MBL0 and MBL1 can be set in a floating state at the time of data reading including both the write verify operation and data access.

  At the time of data reading, write sub-decoder 52l forcibly sets both data D applied to gate circuit GA1 and address bit A0 to the H level, write data D applied to gate circuit GA0 and complementary data. Both address bits / A0 are forcibly set to H level. Similarly, in write subdecoder 52r, complementary address bit / A0 and complementary write data / D applied to gate circuit GB0 are set to the H level, and complementary data / D and gate circuit GB1 are set to H level. Both address bits A0 are set to H level. As a circuit that inverts address bit A0 and data D to generate complementary address bit / A0 and complementary write data / D, a data write control signal that is at L level in a mode other than the data write mode is set to the first level. This can be easily realized by using a NAND circuit that receives the input.

  After the data writing is completed, the write data is read to determine whether the data matches the expected value data. When the data does not match, the write is performed again by changing the write voltage VPPB. In the following, the configuration of the part for practicing this writing sequence will be described.

  Read column select circuit 32 is provided for main bit lines MBL0 and MBL1, respectively, and selectively conducts in accordance with read column select signals RSEL0 and RSEL1. When conducting, main bit lines MBL0 and MBL1 are connected to internal data lines 36a and 36b. Includes read column select gates CG0 and CG1.

  When data is written to normal memory cell M, read column select gates CG0 and CG1 are simultaneously turned on at the time of data reading during a verify operation and data reading for normal data access, and internal data lines 36a36b. A main memory cell is coupled to one of the two, and a dummy memory cell is coupled to the other. A dummy word line is selectively driven to a selected state based on whether the word line address at the time of data reading is an even number or an odd number. That is, when the even word line is selected, the odd dummy word line is driven to the selected state, and when the odd word line is selected, the even dummy word line is driven to the selected state. In the dummy memory cells DMC0 and DMC1, reference data (reference resistance value) of storage data (resistance value) of the normal memory cell M is set. Therefore, complementary current / voltage states appear on internal data lines 36a and 36b due to a read current from a read current supply circuit (not shown). Sense amplifier 34 differentially amplifies the current flowing through internal data lines 36a and 36b. The sense amplifier 34 may be composed of a current sense type differential amplifier circuit, or may be composed of a voltage detection type differential amplifier circuit.

  Switch circuit 9 provides the output signal of sense amplifier 34 to output buffer or write control circuit 4 in accordance with mode setting signal TM.

  The mode setting signal TM sets the switch circuit 9 to a state in which the output signal of the sense amplifier 34 is transmitted to the output buffer in the normal data read mode in which data access is performed, and in the data write mode including the write verify, It is set so that the output signal of the sense amplifier 34 is transmitted to the write control circuit 4.

  The write control circuit 4 compares the data supplied from the switch circuit 9 with the expected value data EXP, and determines whether the data is correctly written based on the output signal of the comparison circuit 50, A BIST (built-in self test) control circuit 52 for generating a voltage step control signal STEP for controlling the write condition according to the determination result, a test sequence for starting and board level tests, and fixed value data A read-only memory (ROM) 54 for storing (programmable) is included. Expected value data EXP applied to comparison circuit 50 is write data applied during data writing. The ROM 54 stores data indicating the step of changing the voltage step control signal STEP, and the write voltage condition is changed according to the stored data. The ROM 54 is programmable, and data can be written and rewritten by the BIST control circuit 52.

  By using this BIST control circuit 52 for a verify operation at the time of data writing, a test sequence for determining whether data writing / reading is accurately performed in a test process at the chip level is used. Thus, the write verify at the time of data writing in the normal operation mode can be performed.

  In this memory device, internal data lines 36a and 36b are further coupled to reference resistance elements RVRa and RVRb via switching elements TGa and TGb, respectively. The resistance values of these reference resistance elements RVRa and RVRb can be changed under the control of the write control circuit 4 (BIST control circuit 52). These reference resistance elements RVRa and RVRb are used when data is written in dummy memory cells DMC0 and DMC1. The reference resistance value of the dummy memory cell is stored in the ROM 54. Reference resistance elements RVRa and RVRb are selectively connected to internal data lines 36a and 36b to be used as reference resistances for the selected dummy memory cell. Data writing to the dummy memory cell will be described in detail later.

  FIG. 11 is a diagram showing magnetization characteristics of normal memory cells and dummy memory cells. In FIG. 11, the memory cells (regular memory cell and dummy memory cell) have a hard axis and an easy axis. The magnetic field H (DL) induced by the current flowing through the digit line DL and the dummy digit line DDL is set to the magnetic field H (E) in the easy axis direction. On the other hand, the magnetic field H (BL) induced by the current flowing through the bit line BL (sub-bit line SBL) is set to the magnetic field H (H) along the hard axis. The combined magnetic field H of the magnetic field H (BL) induced by the current flowing through the bit line BL and the magnetic field H (DL) induced by the current flowing through the digit line DL extends to the outside of the curve (asteroid characteristic line) in FIG. When present, the magnetization state of the memory cell is set to the magnetization direction of the applied magnetic field H. Therefore, when the magnetic field strength applied to the memory cell exists outside the asteroid characteristic line shown in FIG. 11, the magnetization state of the memory cell is reversed. When the applied combined magnetic field strength exists inside the asteroid characteristic line, the magnetization state is not reversed. This asteroid characteristic line thus represents the threshold for magnetization reversal.

  Even if the magnetization state is reversed, there is a case where the electrical resistance value does not become a sufficiently high resistance state or a low resistance state due to variations in the size or characteristics of the memory cell. When this writing failure exists, the low resistance state or the high resistance state can be reliably set by changing the phase difference with the magnetization direction of the fixed magnetic layer. In addition, when magnetization reversal has not occurred, it is possible to reliably cause magnetization reversal and set the magnetization state according to the write data. Hereinafter, a data write sequence of the memory cell will be described.

Write sequence for normal memory cell 1:
FIG. 12 is a flowchart showing a data write sequence according to the first embodiment of the present invention. A data write sequence of the storage device according to the first embodiment of the present invention will be described below with reference to FIG.

  First, the write control circuit 4 shown in FIG. 1 determines whether data writing has been instructed in accordance with an external command CMD (step S1). When data writing is not designated, write control circuit 4 waits for a data write instruction. In this case, when data reading is designated, main control circuit 8 shown in FIG. 1 performs operation control for reading data in accordance with the data reading instruction of command CMD.

  If it is determined in step S1 that data writing is designated, first, the write control circuit 4 shown in FIG. 1 latches the write data D supplied from the input / output circuit 7 (step S2), and then in FIG. Initially set voltage levels of voltages VPPD and VPPB generated by write voltage generation circuit 15 shown (step S3).

  After initial setting of digit line write voltage VPPD and bit line write voltage VPPB, write control circuit 4 shown in FIG. 1 activates main control circuit 8 shown in FIG. 1 to perform data writing. . At the time of data writing, main bit line drivers 50e and 50o shown in FIG. 9 transmit bit line write voltage VPPB to selected main bit lines (for example, MBL0 and MBL1) in accordance with write data d and an address signal. At this time, current flows in the direction corresponding to the write data D to the selected sub-bit line by the sub-bit line drivers 54le, 54re, 54lo, and 54ro. The bit line write current at this time is set by the bit line write voltage VPPB. In addition, a current corresponding to the digit line write voltage VPPD flows through the digit line DL by the digit line driving circuit 20 shown in FIG. By these sub-bit line write current and digit line write current, a synthetic magnetic field of induced magnetic field is applied to the selected memory cell, its magnetization state is set, and data writing is completed (step S4).

  After completion of the data writing, main bit line drivers 50e and 50o shown in FIG. 10 reset selected main bit lines MBL0 and MBL1 to the ground voltage level by MOS transistors NQ1 and NQ2 in accordance with the output signals of gate circuits G2 and G4. After that, the output high impedance state is obtained.

  Next, the write control circuit 4 sets the path of the switch circuit 9 shown in FIG. 9 as a path for transferring the output signal of the sense amplifier 34 to the comparison circuit 50, and write data D (latch) as expected value data EXP. Is supplied to the comparison circuit 50. In this state, read data is read from the selected memory cell (step S5). At the time of data reading, sub bit lines SBL0 and SBL1 are coupled to main bit lines MBL0 and MBL1 through a sub bit line driver. In this state, read column selection signals RSEL0 and RSEL1 are driven to the selected state, and main bit lines MBL0 and MBL1 are coupled to internal data lines 36a and 36b. At the time of data reading, word line WL and dummy word line DWL are selected, and a normal memory cell and a dummy memory cell in which data is written are connected to one and the other of main bit lines MBL0 and MBL1, respectively. . The sense amplifier 34 generates a signal corresponding to the resistance state of the normal memory cell and the dummy memory cell, and supplies the signal to the comparison circuit 50 via the switch circuit 9.

  The comparison circuit 50 compares the data from the sense amplifier 34 with the expected value data (latch data) EXP, and gives the match / mismatch determination result to the BIST control circuit 52 of the write control circuit 4 (step S6). .

  When the read data and the expected value data (latch data) do not match, the BIST control circuit 52 sets the digit line write voltage VPPD to a predetermined voltage width while keeping the bit line write voltage VPPB at the initial value. Increment step. Next, data is written into the same memory cell again under the control of main control circuit 8 (see FIG. 1), and the operations after step S2 are repeated.

  If it is determined in step S6 that the read data matches the latch data (expected value data), it is determined in step S8 whether there is next write data. If it exists, new write data is latched as expected value data, and the operations after step S3 are executed again. If it is determined in step S8 that the write data does not exist, the data write sequence is terminated to prepare for the next operation.

  In step S7 shown in FIG. 12, the bit line write voltage VPPB is fixed to the initial value and the digit line write data VPPD is incremented in units of steps for the following reason. The digit line induces a magnetic field in the easy axis direction by the digit line write current. When the distance between the digit line and the variable magnetoresistive element of the memory cell is larger than the distance between the bit line and the variable magnetoresistive element, the magnetic field induced by the digit line causes the variable magnetic resistance of the nearby memory cell. There is a possibility that a magnetic disturbance problem that affects the resistance element and reverses the magnetization state of the neighboring non-selected memory cell may occur. In this case, the magnetic field induced by the current flowing through the bit line is a magnetic field in the hard axis direction, and the bit line induced magnetic field (H (BL) in FIG. 11) in the hard axis direction is increased. The voltage of write voltage VPPB is initialized. The digit line write voltage VPPD is gradually increased so that the intensity of the magnetic field (H (DL) in FIG. 11) induced by the current flowing through the digit line gradually increases. As a result, data can be written to the selected memory cell while suppressing the influence of the digit line induced magnetic field on nearby non-selected memory cells.

  Further, in the configuration in which a magnetic shield is provided for the digit line by wiring and the problem of magnetic disturbance of the neighboring non-selected memory cells does not occur, the bit line write voltage VPPB and the digit write voltage VPPD are set as follows. Change as follows. That is, the bit line write voltage VPPB is initialized so that the bit line write current becomes the minimum value. In this state, digit line write voltage VPPD is sequentially incremented so as to increase the current flowing through the digit line so that writing is sufficiently performed.

  In step S8, the presence / absence of the next write data is determined. Here, when data is continuously written, for example, page write, for example, the write data is first latched in an internal register (not shown) and the register data is sequentially written.

  13 and 14 are diagrams showing changes in the induced magnetic field in the data write sequence. 13 and 14, the horizontal axis indicates the magnetic field in the easy axis direction, and the vertical axis indicates the magnetic field in the hard axis direction. In the curve shown in FIG. 13, a state where the asteroid characteristic line overlaps with the combined magnetic field intensity with an induced magnetic field of ± 0 is considered.

  As shown in FIGS. 13 and 14, the magnetic field intensity in the hard axis direction is increased in accordance with the digit line write voltage, so that the magnetic field in the easy axis direction induced by the bit line write current is increased. By writing data while maintaining a constant value, data can be rewritten (magnetization reversal) when the asteroid characteristic line is exceeded. Further, as shown in FIG. 14, even when this asteroid characteristic line has a characteristic different from the estimated asteroid characteristic line shown in FIG. By sequentially increasing the data, the data can be rewritten when the combined magnetic field intensity exceeds the asteroid characteristic line, and accurate data can be written regardless of the memory cell characteristics. The margin can be increased.

Write sequence 2 to normal memory cell:
FIG. 15 shows a modification of the data write sequence according to the first embodiment of the present invention. In the data write sequence shown in FIG. 15, the operation contents of step SP7 for changing the write voltage performed following step S6 for comparing the read data with the latch data (expected value data) are shown. This is different from the data writing sequence shown in FIG. In step SP7, when the write voltage is changed, the voltage levels of both the bit line write voltage VPPB and the digit line write voltage VPPD are raised. The remaining steps of the write data sequence shown in FIG. 15 are the same as the steps of the write sequence shown in FIG. 12, and corresponding portions are denoted by the same step numbers, and detailed description thereof is omitted.

  In the case of the data write sequence shown in FIG. 15, as shown in FIG. 16, the magnetic field H (E) in the easy axis direction and the magnetic field H (H) in the hard axis direction are determined in advance from the minimum initial setting value. The voltage step increases in steps. In the evaluation magnetization characteristic shown in FIG. 16, a state is considered in which the asteroid characteristic line and the combined magnetic field intensity overlap with each other with an induced magnetic field of ± 0. In this case, the bit line write current and the digit line write current are sequentially increased from the initial set value by incrementing the bit line write voltage VPPB and the digit line write voltage VPPD, respectively. When the combined magnetic field strength of the induced magnetic field exceeds the asteroid characteristic line, the magnetization state of the memory cell can be set.

  On the other hand, as shown in FIG. 17, even when the asteroid characteristic line deviates from the evaluation value, the digit line magnetic field in the easy axis direction and the bit line magnetic field in the hard axis direction are determined in advance from the minimum initial value. By incrementing the voltage width step by step, the data can be rewritten when the asteroid characteristic line is exceeded.

  In particular, in the case of an asteroid characteristic line, when both the easy axis direction and the hard axis direction are deviated from the evaluation characteristic line (characteristic line shown in FIG. 16) to the same extent, the bit line write voltage VPPB and the digital line write voltage By changing both the VPPD and changing the bit line write current and the digit line write current, accurate data writing can be performed. In particular, the magnetization directions of the data “0” and “1” can be set to a direction having a sufficiently large angle difference, and the resistance value margin can be sufficiently increased. Rewriting can be performed in a large state.

Dummy memory cell data write sequence:
FIG. 18 is a diagram showing a resistance state of the dummy memory cell. As an example, when the size of a dummy memory cell is larger than that of a normal memory cell and is set to a high resistance state, the resistance value is an intermediate value between the resistance values of the high resistance state and the low resistance state of the normal memory cell. Consider the case where the state is set to give. That is, as shown in FIG. 18, when a normal memory cell has a resistance value Rhn in a high resistance state and has an electrical resistance value Rln in a low resistance state, the dummy memory cell is electrically connected in a high resistance state. The resistance value Rhd is shown. The electrical resistance value Rhd is an intermediate value between the electrical resistance values Rhn and Rln. When the dummy memory cell is set in the low resistance state, the electrical resistance value Rld at that time is a resistance value lower than the electrical resistance value Rln in the low resistance state of the normal memory cell. In this case, for example, by setting the size of the dummy memory cell to 2 · Rh / (Rhn + Rln) times the size of the normal memory cell, the area of the current path of the dummy memory cell becomes larger than that of the normal memory cell, The resistance value can be set to a predetermined value.

  FIG. 19 is a flowchart showing a data write sequence of the dummy memory cell according to the first embodiment of the present invention. A data write sequence to the dummy memory cell will be described below with reference to FIGS.

  The data writing of the dummy memory cell may be executed by using the BIST control circuit 52 (see FIG. 10) in a test sequence before product shipment. A write sequence may be performed.

  Write data for setting the high resistance state is set for dummy memory cells DMC0 and DMC1 shown in FIG. 10 (step S10). In this case, it is not necessary to initialize all the dummy memory cells to the low resistance state. For a dummy memory cell that is in a high resistance state and has a predetermined intermediate resistance value, a write completion determination is made by a verify operation after data writing, so that only subsequent rewriting is not performed. .

  The dummy digit line DDL shown in FIG. 9 is driven to the selected state, and then the dummy memory cells DMC0 and DMC1 are sequentially set to the low resistance state using the bit line drive circuit 22 shown in FIG.

  Next, the resistance values of the reference resistance elements RVRa and RVRb shown in FIG. 10 are set to resistance values corresponding to the resistance value Rln of the normal memory cell in the low resistance state (step S11), and then the address AD is set to the initial address “0”. (Step S12). These operations are executed by the BIST control circuit 52 shown in FIG. The resistance values of the reference resistance elements RVRa and RVRb may be set to a value slightly smaller than the target resistance value of the dummy memory cell using a code stored in the ROM 54 in the write control circuit 4.

  Thereafter, data is written into dummy memory cells DMC0 and DMC1 under the control of BIST control circuit 52 shown in FIG. 10 (step S13).

  When this writing is completed, BIST control circuit 52 shown in FIG. 10 connects one of reference resistance elements RVRa and RVRb to the internal data line of internal data bus 36 in accordance with the address signal to read data. At this time, the dummy memory cell is connected to one of the internal data lines 36a and 36b, and the reference resistance element RVRa or RVRb is connected to the other (step S14). Thereafter, data is read using the sense amplifier 34 and an output signal of the sense amplifier 34 is given to the comparison circuit 50 via the switch circuit 9.

  Data corresponding to the state where the dummy memory cell is in the high resistance state is applied to comparison circuit 50 as expected value EXP. In this case, as shown in FIG. 10, dummy memory cells DMC0 and DMC1 are connected to internal data lines 36a and 36b, respectively, and these internal data lines 36a and 36b are connected to sense amplifier 34, respectively. Therefore, the logic level of expected value data EXP is selectively inverted depending on which of dummy memory cells DMC0 and DMC1 is selected. This is easily realized by using the address bit A0.

  If it is determined that the selected dummy memory cell is not yet set in the high resistance state, and it is determined that the electrical resistance value is lower than the resistance value Rln in the low resistance state of the normal memory cell, the write condition is changed. After changing (step S16), the data writing sequence starting from step S13 is executed again.

  On the other hand, if it is determined in step S15 that the dummy memory cell is set to the high resistance state and the electrical resistance is determined to be higher than the resistance value Rln, then the reference resistance elements RVRa and RVRb One resistance value is set to the lower limit value of the resistance value Rhn in the high resistance state of the normal memory cell (step S17). In this state, data is read again and compared with the expected value EXP in the comparison circuit 50 in accordance with the output signal of the sense amplifier 34. The electric resistance of the dummy memory cell is lower than the lower limit resistance value of the high resistance state of the normal memory cell. It is determined whether it has a value (step S19).

  In step S19, if it is determined that the electrical resistance value of the dummy memory cell is higher than the lower limit value of the electrical resistance value Rhl in the high resistance state of the normal memory cell, the reverse operation for setting the dummy memory cell in the low resistance state is performed. Data is written (step S20). At the time of this reverse data writing, the data writing condition of the initialization sequence may be used, or a rewriting condition different from the writing condition at the time of initialization may be used. Thereafter, the process returns to step S13 again, and the sequence after step S13 for setting the dummy memory cell to the high resistance state is executed.

  In step S19, when the output signal of the comparison circuit 50 determines that the dummy memory cell is in the low resistance state, it is determined that the electrical resistance value Rhd of the dummy memory cell is set to a predetermined value, and the dummy memory cell Data writing is completed.

  Next, it is determined whether or not the last dummy memory cell is designated for the address AD (step S21). If there is a dummy memory cell to be written, the address is incremented by 1 (S22), and the data write sequence from step S13 is executed again. On the other hand, when it is determined in step S21 that address AD is the final address, the data write sequence for all dummy memory cells is completed.

  By using the data write sequence shown in FIG. 19, the dummy memory cell can be reliably set to the high resistance state.

  Note that the resistance values of the reference resistance elements RVRa and RVRb are encoded and stored in the ROM 54 shown in FIG. 10, and the BIST control circuit 52 reads out the resistance values of the reference resistance elements RVRa and RVRb in each operation step. Set. Further, since the BIST control circuit 52 generates an address signal when selecting a dummy memory cell, the logic level of the expected value data EXP is inverted according to the address.

  In addition, the size of dummy memory cells DMC0 and DMC1 is made smaller than the size of normal memory cells. In a configuration in which a reference electric resistance value is given in the low resistance state, after all dummy memory cells are initially set to a high resistance, a data write sequence for setting these dummy memory cells to a low resistance state is executed. Just do it. In this case, the operation flow can be obtained by replacing the high resistance state and the low resistance state in the flowchart shown in FIG.

  Further, before the data is written, first, the dummy memory cell and the reference resistance element may be compared. It is not necessary to write data to the dummy memory cell already set to a predetermined resistance state, and the time and current consumption required for writing can be reduced.

  Further, when it is detected in advance in a test process or the like that the characteristic of the dummy memory cell is deviated from the design value due to variations in manufacturing parameters, the resistance value of the reference resistance element is determined according to the variation in characteristics. (ROM storage data is changed).

Dummy memory cell resistance detection sequence (reference resistance element resistance value determination sequence):
FIG. 20 shows a sequence for detecting the resistance value distribution after data writing in dummy memory cells DMC0 and DMC1 shown in FIG. In the detection sequence shown in FIG. 20, the write data to the dummy memory cell may be either data set to the high resistance state or data set to the low resistance state. The resistance value distribution of the dummy memory cell is reflected in the resistance values of the reference resistance elements RVRa and RVRb. The resistance distribution detection sequence for the dummy memory cell will be described below with reference to FIGS.

  First, write data is set in dummy memory cells DMC0 and DMC1 (step S30). The setting of the write data is determined depending on whether dummy memory cells DMC0 and DMC1 are set to a high resistance state or a low resistance state.

  Note that an initialization sequence for initializing all dummy memory cells to the high resistance state is not particularly required.

  Next, the head address (AD = 0) is set (step S31), the resistance values of the reference resistors RVRa and RVRb are set (step S32), and the set data is written to the selected dummy memory cell. (Step S33).

  One of reference resistance elements RVRa and RVRb shown in FIG. 10 is selected in accordance with an address signal and a dummy memory cell is selected and connected to an internal data line to read data (step S34). In step S34, dummy memory cell DMC0 or DMC1 is connected to one of internal data lines 36a and 36b, and reference resistance element RVRb or RVRa is connected to the other. The sense amplifier 34 detects this data and supplies it to the write control circuit 4. In write control circuit 4, data from sense amplifier 34 in the previous cycle is latched as expected value data EXP by a latch circuit (not shown). The comparison circuit 50 compares the data from the sense amplifier 34 with the read data (expected value data) of the previous cycle (step S36). In the first comparison step, the resistance values of reference resistance elements RVRa and RVRb are initialized so that expected value data and internal read data do not match. Alternatively, data read in the first cycle is used as expected value data that is initialized. In the first cycle, the comparison operation may not be performed.

  When the logical levels of the read data in the previous cycle and the current cycle match, it is determined that the reference resistance elements RVRa and RVRb are not set to the resistance values corresponding to the dummy memory cell electrical resistance state. The resistance values of resistance elements RVRa and RVRb are changed, and the process returns to step S34 to read out data. On the other hand, if the logic levels of the data read in the previous cycle and the current cycle do not match in step S36, the resistance values of reference resistance elements RVRa and RVRb are set to the electrical resistance of the selected dummy memory cell in this current cycle. Since it is determined that the value has been exceeded, the average value of the resistance values of the reference resistance elements RVRa and RVRb in the previous cycle and the current cycle is registered in the ROM 52 shown in FIG. Here, the ROM 54 is electrically programmable.

  Next, in step S39, it is determined whether or not the electrical resistance value of the final dummy memory cell has been measured. If the electrical resistance of the final dummy memory cell has not been measured, the address is set to 1 in step S40. Increment and return to step S32.

  Therefore, in this case, data is written to the dummy memory cell, and the resistance value of the reference resistance element RVRa or RVRb is changed with respect to the electrical resistance value of the dummy memory cell set by the write data, thereby the dummy memory cell. The existence range of the electrical resistance value is detected. For example, after setting the resistance values of the reference resistance elements RVRa and RVRb to a value smaller than the lower limit value of the electrical resistance value of the dummy memory cell, the resistance value is sequentially incremented to read data, and the logic level By detecting the time of change, the electrical resistance of the dummy memory cell can be measured.

  The resistance value of the reference resistance element stored in the ROM 54 may be stored in sector units, word line units, bit line units, or block units of a predetermined size of the memory array. Further, it is not particularly required to store the resistance values of the reference resistance elements for all dummy memory cells. By storing the resistance value of the reference resistive element with respect to a typical dummy memory cell in the ROM 54, the resistance value data storage area is reduced.

  When data is written in the dummy memory cell at the time of system initialization, the data can be written in the dummy memory cell accurately by using the resistance value registered in the ROM 54. When the system is restarted or the like, the state of the dummy memory cell can be accurately determined by setting an electrical resistance value smaller than the registered resistance value by a predetermined value or an electrical resistance value larger by a predetermined value.

  In the operation shown in the flowchart of FIG. 20, the output applied to sense amplifier 34 is also provided when data is read from dummy memory cells connected to even columns (even bit lines) and odd columns (odd bit lines). The logic level of the data is reversed. However, by changing the resistance value of the reference resistance element RVRa or RVRb in one direction, for one dummy memory cell, the logic level of the output signal of the sense amplifier is such that the electrical resistance value of the reference resistance element is the dummy memory cell. Therefore, the electrical resistance of the dummy memory cell can be accurately measured.

  The operation flow shown in FIG. 20 is executed under the control of BIST control circuit 52 shown in FIG. 10, and address generation and write data setting are executed by BIST control circuit 52. Reading is performed by the main control circuit 8 shown in FIG. 1 in accordance with a control signal from the BIST control circuit.

[Modification 1]
FIG. 21 is a flowchart showing the operation of the modification of the first embodiment of the present invention. In the first modification, the distribution of the electrical resistance value of the normal memory cell is detected, and the resistance value of the reference resistance element is set according to the detection result. The operation of the modification of the first embodiment of the present invention will be described below with reference to FIGS. 10 and 21.

  First, write data is set to H level or L level (step S40), and then the set data is written to all normal memory cells (step S41). The resistance values of the reference resistance elements RVRa and RVRb are set according to the set data (step S42). Next, the start address AD is set by the BIST control circuit 52 (step S43), and the reference resistance element RVRa or RVRb is connected to the internal data line to read data (step S44).

  At the time of this data reading, switch circuit 9 shown in FIG. 10 provides the output signal of sense amplifier 34 to comparison circuit 50. In this comparison circuit 50, it is determined whether the data supplied from the sense amplifier 34 matches the expected value data EXP (step S45). This expected value EXP is set according to which of the internal data lines 36a and 36b the normal memory cell is connected to. If the expected value data EXP and the read data from the sense amplifier 34 do not match, the resistance value of the reference resistance element RVRa or RVRb is changed (step S46). For example, when the normal memory cell is set to the high resistance state, the resistance value of the reference resistance element RVRa or RVRb is set lower than the initial setting value. Next, steps S44 and S45 are executed again.

  When the coincidence between the expected value data and the read data from the sense amplifier 35 is detected in step S45, the resistance value of the reference resistance element RVRa or RVRb is not changed and the state is maintained. Next, in step S47, it is determined whether the address AD of the selected normal memory cell is the final address. If it is different from the final address, the address is incremented by 1 (step S49), and the operation from step S44 is executed again. To do.

  If it is determined in step S47 that the address AD is the final address, the values of the reference resistance elements RVRa and RVRb are latched and registered in the ROM 54.

  The sequence shown in FIG. 21 is executed for each of data corresponding to the high resistance state and data corresponding to the low resistance state of the normal memory cell. Finally, as the values of the reference resistance elements RVRa and RVRb latched in step S48, the lower limit value of the resistance distribution of the electrical resistance value in the high resistance state and the upper limit value of the electrical resistance value in the low resistance state of the normal memory cell. Is latched. Therefore, as shown in FIG. 22, the resistance value of the average value of the lower limit value Rhmin of the electrical resistance value in the high resistance resistance state and the upper limit value Rlmax of the electrical resistance value in the low resistance state is represented by the reference resistance element RVRa and By setting the resistance value of RVRb, a read reference value having a sufficient margin can be generated for the memory cell in the high resistance state and the memory cell in the low resistance state at the time of data reading.

  In this case, it is not necessary to use a dummy memory cell at the time of data reading, and it is not necessary to select a word line and a dummy word line at the time of data reading, so that current consumption can be reduced.

  FIG. 23 is a diagram showing an example of the configuration of the data reading unit in the first modification. In FIG. 23, the even main bit line MBLe is coupled to the internal data line 36a via the even column selection gate CGe, and the odd main bit line MBLo is coupled to the internal data line 36b via the odd column selection gate CGo. Are combined. Column selection gates CGe and CGo are selectively set to a conductive state in accordance with read column selection signals RSELe and RSELo, respectively. The read column selection signal RSELe is activated based on the remaining address signal when the address bit A0 is “0”, and the read column selection signal RSELo is activated when the address bit A0 is “1”. Activated based on bit.

  Reference resistance elements RVRa and RVRb are coupled to internal data lines 36a and 36b via transfer gates TGa and TGb. Reference resistance elements RVRa and RVRb have the other ends connected to the ground node. Transfer gate TGa is selectively rendered conductive according to gate circuit AG0 receiving address bit A0 and read instruction signal RAED, and transfer gate TGb is selectively selected according to gate circuit AG1 receiving read instruction signal READ and complementary address bit / A0. It becomes a conductive state. Gate circuits AG0 and AG1 output an H level signal when both signals applied to both inputs thereof are at an H level, and set corresponding transfer gates TGa and TGb to a conductive state. Read instruction signal READ is activated when sense amplifier 34 shown in FIG. 10 operates.

  When the even main bit line MBLe is selected and connected to the internal data line 36a, since the address bit A0 is "0", the output signal of the gate circuit AG1 becomes H level, the transfer gate TGB becomes conductive, and the internal data Reference resistance element RVRb is connected to line 36b.

  When odd main bit line MBLo is connected to internal data line 36b, address bit A0 is "1", so that transfer gate TGa is turned on according to the output signal of gate circuit AG0, and reference resistance element RVRa is connected to internal data line 36b. 36a.

  Therefore, data of normal memory cells can be read using the resistance values of reference resistance elements RVRa and RVRb as reference resistance values.

  The other configuration of the first modification is the same as the configuration illustrated in FIG.

  As described above, according to the first embodiment of the present invention, at the time of data writing, it is determined whether or not the data has been correctly read by reading the write data, and the correct data writing can be performed. This can be done and the write margin can be increased. In particular, by rewriting data by changing the write condition, data can be accurately written regardless of variations in memory cell characteristics.

  Further, by using a reference resistance element having a resistance value reflecting the characteristics of the memory cell at the time of data reading, the read margin can be increased and data can be read accurately.

  Note that when data is written, the data in the selected memory cell is read before the data is written, and if the stored data matches the expected value, the data writing to the selected memory cell is stopped and the next data A step of performing writing or completing writing of data may be added. Data can be written only to memory cells that require data rewriting with write data, writing time can be shortened, and current consumption can be reduced.

[Embodiment 2]
FIG. 24 is a diagram showing an electrical equivalent circuit of a resistance-change memory cell used in the second embodiment of the present invention. In FIG. 24, the memory cell is selectively turned on in accordance with a signal on the word line WL and a phase change element CPE whose crystal state changes according to stored data, and from the bit line BL to the column line via the phase change element PCE. And an access transistor ATR that forms a path for current to flow through CL.

  Phase change element PCE includes a heater HET that generates Joule heat according to a supplied current, and a chalcogenide layer that is heated by the heat from heater HET and whose crystal state is set to either an amorphous state or a crystalline state. Includes CALCH.

  Access transistor ATR is formed of a PNP bipolar transistor whose emitter is connected to the heater, and causes a current to flow from heater HET to collector line CL in accordance with base-emitter voltage Vbe.

  In the phase change memory using the phase change element PCE for data storage, a current is supplied to the heater HET at the time of data writing, and the crystal state of the phase change element PCE is applied by applying heat to the heater HET. Set according to the mode. If the phase change element PCE has characteristic variations, the electric resistance value is different even if the same heat application cycle is performed. Also at the time of data writing, as in the first embodiment, the write verify operation is performed, the write condition is changed, the data is rewritten, and the data is written accurately.

  FIG. 25 schematically shows a structure of a main portion of the resistance variable memory apparatus according to the second embodiment of the present invention. 25, in memory cell array 1, normal memory cells MC and dummy memory cells DMX and DMC are arranged in a matrix. Normal memory cell and dummy memory cell DMX and DMC include phase change element PCE and access transistor ATR, as in the configuration shown in FIG. Regarding the constituent elements of this memory cell, reference numerals of phase change element PCE and access transistor ATR are attached to only one normal memory cell MC.

  The dummy memory cell DMX is set to the high resistance state Rmax, and the dummy memory cell DMC is set to the low resistance state Rmin. These dummy memory cells DMX and DMC are arranged in alignment with each row of normal memory cells MC.

  Corresponding to each row of normal memory cells MC and dummy memory cells DMX and DMC, word lines WL0 to WLm and collector lines CL0 to CLm are arranged. Word lines WL0-WLm are each coupled to the base of access transistor ATR in the corresponding row. Collector lines CL0-CLm are coupled to the collector of access transistor ATR in the corresponding row, respectively, and are coupled to the ground node.

  Bit lines BL0, BL1,... Are arranged corresponding to each column of normal memory cells MC, dummy bit lines DBL0 are arranged corresponding to dummy memory cells DMX, and corresponding to columns of dummy memory cells DMC. A dummy bit line DBL1 is provided. These bit lines BL0, BL1,... And dummy bit lines DBL0 and DBL1 are connected to normal memory cell MC or phase change element PCE of the dummy memory cell in the corresponding column.

  Corresponding to each of word lines WL0-WLm, word line drivers WD0-WDm for driving the corresponding word lines to a selected state according to the output signal of word line decoder 108 are provided, and bit lines BL0, BL1,. Bit line drivers BDR0, BDR1,... Are arranged correspondingly, and dummy bit line drivers DBDR0 and DBDR1 are arranged corresponding to dummy bit lines DB0 and DBL1, respectively. Word line drivers WD0 to WDm drive corresponding word lines to L level when selected, maintain corresponding word lines to H level when not selected, and maintain access transistor ATR in a non-selected state.

  Bit line drivers BDR0, BDR1,... And dummy bit line drivers DBDR0 and DBDR1 transmit voltage VPP from voltage generation circuit 104 to the corresponding bit line when selected in accordance with the output signal of write driver decoder 106.

  In order to control the voltage level at the time of data writing of voltage VPP generated by voltage generation circuit 104, the level of write voltage VPP is controlled in accordance with voltage step control signal STEP from write control circuit 4, as in the first embodiment. Is provided. The voltage setting circuit 102 is included in the write condition setting circuit 5 shown in FIG. Write voltage VPP is transmitted to the bit line at the time of data writing and corresponds to bit line write voltage VPPB in the first embodiment. In the second embodiment, the voltage level is adjusted at the time of data writing. In order to indicate that the voltage is a voltage, a write voltage transmitted to the bit line driver is indicated by a symbol VPP.

  Corresponding to bit lines BL0 and BL1, read column select gates CSG0 and CSG1 are provided for connecting corresponding bit lines BL0 and BL1 to internal data lines 136a and 136b according to read column select signals RSEL0 and RSEL1, respectively. These read column selection signals RSEL0 and RSEL1 are simultaneously driven to a selected state during data reading.

  Corresponding to dummy bit lines DBL0 and DBL1, dummy column selection gates DSG0 and DSG1 are provided for connecting dummy bit lines DBL0 and DBL1 to internal data lines 140b and 140a, respectively, in accordance with dummy read column selection signals DRSELx and DRSELn. . Dummy read column selection signals DRSELx and DRSELn are driven to a selected state regardless of the selected memory cell column during normal data read for data access. At the time of internal data reading at the time of write verification, these dummy column selection signals DRSELx and DRSELn are set to a non-selected state regardless of the selected column. At the time of verifying data writing to dummy memory cells DMX and DMC, dummy column selection signals DRSELx and DRSELn are individually driven to a selected state in accordance with the selected dummy memory cell.

  Between dummy bit lines DBL0 and DBL1, an equalize transistor 146 that is turned on in accordance with an equalize instruction signal EQ is provided. Equalize instruction signal EQ is activated in the normal data read mode, and dummy bit lines DBL0 and DBL1 are electrically short-circuited. By short-circuiting the dummy bit lines connected to the dummy memory cells in the high resistance state Rmax and the low resistance state Rmin, the current flowing through the dummy memory cells in the high resistance state Rmax and the low resistance state Rmin is averaged during data reading. The elements in the intermediate resistance state of the high resistance state and the low resistance state are equivalently formed.

  Internal data lines 136a and 136b are respectively connected with current source transistors 142a and 142b formed of diode-connected N-channel MOS transistors, and dummy internal data lines 140a and 140b are similarly diode-connected N-channels. Current source transistors 144a and 144b formed of MOS transistors are provided.

  Internal data lines 136a and 140a are coupled to sense amplifier 110, and internal data lines 136b and 140b are coupled to sense amplifier 112. Output signals of these sense amplifiers 110 and 112 are transmitted to a latch 116 via an interleave amplifier 114. The interleave amplifier 114 sequentially amplifies the output signals of the sense amplifiers 110 and 112 and transfers them to the latch 116. The latch data of the latch 116 is applied to the output buffer 120 or the write control circuit 4 via the switch circuit 118. Therefore, in the normal data read mode, 2-bit memory cells are selected in parallel internally, converted into serial data by the interleave amplifier 114, and sequentially output.

  Furthermore, the internal data line 136a has a resistance value set according to a resistance value control signal from the write control circuit 4, and a variable high resistance element RHa and a variable low resistance element RLa, and a resistance selection signal LSa and HSa. Resistance selection transistors 124al and 124ah are provided for selectively coupling resistance elements RLa and RHa to 124al and 124ah to internal data line 136a.

  For internal data line 136b, resistance selection transistors 124bh and 124bl for selectively coupling resistance elements RHb and RLb to internal data line 136b in accordance with variable high resistance element RHb and variable low resistance element RLb, and resistance selection signals HSb and LSb Is provided. These variable resistance elements RHa, RHb, RLa and RLb are used at the time of data writing to dummy memory cells DMX and DMC.

  Between internal data lines 136a and 140b and between internal data lines 136b and 140a, transfer gates 145a and 145b which are selectively turned on according to verify instruction signal VRFY are provided. In the write verify operation, internal data is read using the variable resistance element as a reference resistance element.

  In the memory cell having the phase change element PCE, as shown in FIG. 24, a chalcogenide layer whose crystal state changes according to the heating state and a heater formed immediately below the chalcogenide layer are provided. The chalcogenide layer, the heater and the access transistor are connected in series. At the time of data writing, the bit line and word line potentials are adjusted so that the base-emitter voltage Vbe of the access transistor ATR is increased, and a large current is supplied from the bit line to cause the heater to generate heat. If it is cooled rapidly after this, the chalcogenide layer becomes an amorphous state, while it becomes a crystalline state by slow cooling. Since the electrical resistance is different between the amorphous state and the crystalline state, data is read by detecting the current flowing through the memory cell during data reading.

Normal data read operation:
When reading data to the outside, switch circuit 118 is set to a state of transmitting the output signal of latch circuit 116 to output buffer 120. Write driver decoder 106 sets its output signal to L level, and bit line drivers BDR0, BDR1,... And dummy bit line drivers DBDR0 and DBDR1 MOS transistors NT0 and NT1 are in an off state.

  In this state, word line decoder 108 performs a decoding operation according to the address signal, and drives any of word line drivers WD0 to WDm to the selected state. In accordance with the output signals of word line drivers WD0-WDm, the word line of the selected row is driven to L level. Consider a state where the word line WL0 is selected. In this case, access transistor ATR is turned on in normal memory cell MC and dummy memory cells DMX and DMC.

  On the other hand, paired column selection signals (RSEL0, RSEL1) are driven to a selected state in accordance with a decode signal from a column selection decoder (not shown), and at the same time, column selection signals DRSELx and DRSELn for dummy memory cells are driven to a selected state. Is done. Bit lines BL0 and BL1 are coupled to internal data lines 136a and 136b via read column selection gates CSG0 and CSG1, and dummy bit lines DBL0 and DBL1 are connected to dummy internal data lines 140b and 140a, respectively, as dummy column selection gates. Coupled through DSG0 and DSG1.

  Internal data lines 136a and 136b are supplied with current from current source transistors 142a and 142b, and dummy internal data lines 140a and 140b are supplied with current from current source transistors 144a and 144b. At the time of data reading, equalize instruction signal EQ is turned on, and dummy bit lines DBL0 and DBL1 are electrically short-circuited. Therefore, dummy internal data lines 140a and 140b are connected to dummy memory cell DMX in a high resistance state and dummy memory cell DMC in a low resistance state in parallel, and a read current is supplied from current source transistors 144a and 144b. Then, a current corresponding to the resistance value in the intermediate state between the high resistance state Rmax and the low resistance state Rmin flows through the dummy internal data lines 140a and 140b.

  On the other hand, the normal memory cell drives currents supplied from current source transistors 142a and 142b via bit lines BL0 and BL1, respectively, according to the resistance state of phase change element PCE. The sense amplifier 110 amplifies the current difference between the internal data line 136a and the dummy internal data line 140a, and the sense amplifier 112 amplifies the current difference between the internal data line 136b and the dummy internal data line 140b. The output signals of these sense amplifiers 110 and 112 are sequentially amplified by an interleave amplifier 114 and transferred to the latch circuit 116, and 2-bit data simultaneously read through the output buffer 120 is sequentially output bit by bit.

  The sense amplifiers 111 and 112 may be current detection type differential amplifier circuits or voltage detection type differential amplifier circuits.

Data write sequence to normal memory cell:
FIG. 26 is a flowchart showing a data write sequence to the normal memory cell of the memory device according to the second embodiment of the present invention. Hereinafter, a data write sequence of the storage device shown in FIG. 25 will be described with reference to FIG.

  First, it is determined whether or not a data write instruction has been given (step S50). The determination of the application of the data write instruction is performed in the write control circuit 4. If no data write instruction is given in step S50, it waits for a data write instruction to be given.

  If it is determined in step S50 that data writing has been instructed, the write data is latched (step S51), and then it is determined whether the latch data is data corresponding to the high resistance state Rmax (step S51). S52). If it is determined that the data corresponds to the high resistance state Rmax, the write current (write voltage VPP) is initialized to set the selected memory cell in the high resistance state, and the high resistance element RHa and The resistance value of RHb is set by the write control circuit 4. The resistance values of the high resistance elements RHa and RHb are set to the lower limit value of the high resistance state (step S53).

  After this initial setting, the latch data is written to the selected memory cell (step S54). When setting the selected memory cell to the high resistance state, write voltage VPP from voltage generation circuit 104 is transmitted onto the selected bit line via the bit line driver. In the selected memory cell, the corresponding word line is in the selected state, and access transistor ATR is in the on state. According to the voltage level of write voltage VPP, base-emitter voltage Vbe of access transistor ATR can be set, and accordingly, the amount of current flowing through the heater in the selected normal memory cell can be adjusted. it can.

  After completing the writing of data to the normal memory cell, one of the high resistance elements RHa and RHb is selected according to the bit line to which the selected memory cell is connected. At the time of internal data reading (data reading for verify operation), normal memory cells and high resistance elements RHa or RHb are connected to internal data bus 136. In internal data bus 136, a normal memory cell is coupled to one of internal data lines 136a and 136b, and a high resistance element is coupled to the other.

  Short-circuit transistors 145a and 145b are rendered conductive in accordance with verify instruction signal VRFY during the verify operation, coupling dummy internal data line 140a to internal data line 136b and connecting internal data line 136a to dummy internal data line 140b. . Therefore, sense amplifiers 110 and 112 detect the current of internal data lines 136a and 136b, and indicate a result of comparing the resistance value of the selected normal memory cell with the resistance value of selected high-resistance element RHa or RHb. Is output. Interleave amplifier 114 also sequentially amplifies the output signals of sense amplifiers 110 and 112 and transfers them to latch circuit 116 during the verify operation.

  Switch circuit 118 transfers latch data LATD of latch circuit 116 to write control circuit 4 in the write mode. In accordance with the transferred latch data LATD, the write control circuit 4 determines whether the resistance value of the selected normal memory cell is higher than the resistance values of the set high resistance elements RHa and RHb. When the latch data LATD indicates a state in which the selected normal memory cell is in the high resistance state, it is determined that the normal selection memory cell is in a higher resistance state than the high resistance elements RHa and RHb (step). S57). Also in the determination of the resistance state, since the connection of the normal memory cell and the high resistance element to the sense amplifiers 111 and 112 is reversed, the determination operation for the output signal of the sense amplifier is adjusted according to the selected column (even column and Invert the expected value in odd columns).

  If it is determined in step S57 that the normally selected memory cell has not yet been set to the high resistance state, the write control circuit 4 determines that the write current (write voltage VPP) is incremented by a predetermined width. Voltage step control signal SETP is applied to voltage setting circuit 102. In response, voltage generation circuit 104 increments the voltage level of write voltage VPP by a step of a predetermined width.

  Then, the process returns to step D51, and data is written again by changing the write condition, and the write data is read to determine whether the selected normal memory cell is in the high resistance state. .

  If it is determined in step S57 that the selected normal memory cell is set to the high resistance state, it is determined whether there is next write data (step S59), and if there is no next write data. Completes the write sequence.

  On the other hand, if it is determined in step S52 that the latch data is data corresponding to the low resistance state Rmin, initial setting of the write current and the slow cooling period is performed in step S60. The resistance values of RLa and RLb are set (set to the upper limit value of the resistance value in the low resistance state).

  Next, data is written according to the initially set write current and slow cooling period (step S61).

  After writing the data, the low resistance elements RLa and RLb are then selected (step S62), and the data of the selected normal memory cell is read (step S63). In the selection of the low resistance element and the data reading in step S62, the selected normal memory cell is coupled to one of internal data lines 136a and 136b in accordance with the address signal, and the low resistance element is coupled to the other.

  In internal data lines 136a and 136b, by reading data, a potential difference corresponding to the difference between the resistance value of the selected normal memory cell and the resistance value of low resistance elements RLa and RLb is generated. These are detected and amplified (when the sense amplifier is a voltage detection type differential amplifier circuit). In write control circuit 4, in accordance with latch data LATD transferred from switch circuit 118, it is determined whether or not the selected normal memory cell is in a lower resistance state than low resistance elements RLa and RLb (step S64). . If it is determined that the selected normal memory cell is not yet set in a resistance state lower than the resistance value of the low resistance element, the write condition is changed in step S65. That is, the write current amount is decremented by a step of a predetermined width, and the slow cooling period for bringing the phase change element PCE into the crystalline state is incremented by a step of a predetermined time width.

  When the write condition is changed in step S65, the process returns to step S61 again, and the data write and the data internal read and determination operation verify sequence are executed.

  If it is determined in step S64 that the selected normal memory cell is set to a state indicating a resistance value lower than the resistance values of the low resistance elements RLa and RLb, the process proceeds to step S59 again to determine whether there is next write data. Is determined. If there is next write data, the process returns to step S51 again to write new data. If the next write data does not exist, the data write sequence ends.

  FIG. 27 is a diagram showing an aspect of changing the write condition at the time of data writing corresponding to the high resistance state of the flowchart shown in FIG. In FIG. 27, the horizontal axis represents time, and the vertical axis represents current. As shown in FIG. 27, by executing step S58 shown in FIG. 26, the voltage level of the write voltage VPP from the voltage generation circuit 104 shown in FIG. 25 is incremented by a step of a predetermined width. In accordance with the increment of the write voltage VPP, the base-emitter voltage Vbe of the access transistor ATR is changed, and accordingly, the current flowing from the bit line through the selected memory cell can be incremented by a predetermined step. As a result, the memory cell into which data in the high resistance state is written can be surely set in the amorphous high resistance state. Further, by sequentially increasing the write current, it is possible to prevent an excessive write current from being supplied to the memory cell and to prevent deterioration of the film characteristics of the phase change element.

  FIG. 28 shows how the write current is changed in step S65 shown in FIG. In FIG. 28, the horizontal axis represents time and the vertical axis represents current. As shown in FIG. 28, when data corresponding to the low resistance state is written, the write current is sequentially incremented in the amount of current, and the slow cooling time is also incremented sequentially. By increasing the write current and gradually increasing the slow cooling time, the phase change element PCE of the memory cell can be set to a highly regular crystalline state (crystalline state).

  Note that when the writing condition is changed in step S65, the slow cooling time is sequentially increased. By sequentially incrementing the slow cooling time, the data writing time is prevented from becoming unnecessarily long. However, a reverse write current changing sequence may be used. For example, the slow cooling time may be shortened sequentially.

  As the configuration for changing the slow cooling period, the drop time of the write voltage VPP from the voltage generation circuit 104 shown in FIG. 25 is lengthened, the gate potential of the bit line driver BDR is gradually lowered, and the selection memory A configuration in which the gate potential of the access transistor ATR of the cell, that is, the potential of the selected word line is gradually increased can be used. This configuration can be easily realized by changing the current driving capability of the drive transistor that drives these gate potentials to the non-selected state at the end of writing by a control signal from the voltage setting circuit 102 (in parallel). The provided unit drive transistor is selectively set to an enabled state in accordance with the voltage step control signal).

  In the data write sequence shown in FIG. 26, the data stored in the selected normal memory cell is read before data writing, the read data is compared with the data latched in step S51, and the logic level is the same. The step of omitting data writing may be added. Unnecessary data writing can be omitted, and the time and power consumption required for data writing can be reduced.

Data write sequence to dummy memory cell:
FIG. 29 is a timing chart showing a data write sequence to the dummy memory cell of the memory device according to the second embodiment of the present invention. Hereinafter, with reference to FIG. 29, a data write operation to dummy memory cells DMX and DMC in the memory device shown in FIG. 25 will be described.

  Data writing to dummy memory cells DMX and DMC is executed in an initialization sequence after power-on under the control of a BIST control circuit included in write control circuit 4. In FIG. 29, when the power supply voltage VCC is turned on and the voltage level reaches a predetermined voltage level or higher, the power-on detection signal POR becomes H level, the operation of the internal circuit is prohibited, and the internal node is initialized (reset). ) Is executed. When the power supply voltage VCC is stabilized, the power-on detection signal POR becomes L level, and the internal circuit operation becomes possible.

  Write control circuit 4 generates a dummy write start instruction indicating writing to the dummy memory cell in response to the fall of power-on detection signal POR, and dummy write mode instruction signal DMMY is activated. Data writing and verification are executed in accordance with the clock cycle of clock signal CLK to dummy memory cells DMX and DMC. When data writing to all dummy memory cells DMX and DMC is completed, dummy write mode instruction signal DMMY is deactivated. Accordingly, a dummy write end instruction is generated, the chip enable signal CE is activated, and a normal data access operation is permitted.

  When normal data access is performed, a chip select signal CS, a write command indicating data writing, and a read command indicating data reading are applied, and data access is executed according to the given command. In FIG. 29, when chip select signal CS is applied and data reading is designated, a read cycle starts in synchronization with clock signal CLK, the word line is driven to the selected state internally, and the selected memory is connected to the bit line. The cell data is read out. A difference between the potential of the bit line and the reference potential is generated according to the crystal state of the selected memory cell, and this difference is detected by the sense amplifier to generate internal read data. The memory cell data is externally transmitted through the output buffer. Is read out.

  In the next cycle, when a write command is given together with the chip select signal CS, a write cycle starts and a data write operation is executed. In this case, the word line is driven to the selected state, and write power is supplied to the bit line (see FIG. 26).

  Next, in the cycle, when this data writing is performed, a write verify operation is performed as to whether the written data has been correctly written, internal reading of the data is performed, and comparison with the expected value is performed. . At the time of the write verify, FIG. 29 shows an example of a state where the selected memory cell is set to the high resistance state. If the write data is data set to the high resistance state, it is determined that the data has been correctly written by this write verify, and the next data access is received. If it is determined that the data write is not correctly performed by the write verify, the data write is executed again by changing the write condition.

  By accurately setting the data in the dummy memory cell to the high resistance state and the low resistance state in this initialization sequence after power-on, the data can be correctly written and read in the normal data access mode. it can.

  FIG. 30 is a flowchart showing a data write operation to the dummy memory cell in the dummy write mode shown in FIG. Hereinafter, a data write operation to dummy memory cells DMX and DMC of the memory device shown in FIG. 25 will be described with reference to FIG.

  Further, after the power is turned on, a power-on detection signal POR is generated, and it is determined whether the signal has fallen from H level to L level (step S70). When the power-on detection signal POR is not generated or is maintained at the H level, it waits for generation or falling of the power-on detection signal POR.

  When the power-on detection signal POR is generated and falls to the L level, a dummy write start instruction is generated in the write control circuit 4 (step S71). In response to the dummy write start instruction, the BIST control circuit included in the write control circuit 4 performs an operation of writing data to the dummy memory cells DMX and DMC in a predetermined sequence. This dummy write start instruction may be generated by a dedicated circuit that receives the power-on detection signal POR and given to the BIST control circuit. The BIST control circuit monitors the power-on detection signal POR and starts dummy write internally. An indication may be generated.

  When the dummy write mode instruction signal is activated in accordance with the dummy write start instruction, data and address AD are first set in write control circuit 4 (step S72). Dummy memory cells DMX and DMC are in a high resistance state and a low resistance state, respectively, and the processing sequence differs depending on the set data, as in the flowchart shown in FIG. First, in step S73, it is determined whether the setting data is data corresponding to the high resistance state Rmax.

  If the setting data is data corresponding to the high resistance state Rmax, and it is determined that data is written to the dummy memory cell DMX shown in FIG. 25, the write voltage is initially set and the high resistance is set. The resistance value of the element RHb is set (step S74). As shown in FIG. 25, the dummy memory cell DMX written in the high resistance state is coupled to the sense amplifier 112 via the dummy internal data line 140b. Therefore, at the time of reading internal data, it is required to connect resistance element RHb corresponding to the high resistance state to internal data line 136b, and the resistance value of resistance element RHb is set. After this initial setting, data writing is executed (step S75).

  Next, resistance element RHb is selected, and the data stored in dummy memory cell DMX is read (step S77). After performing a sensing operation in the sense amplifier 112, the latch data LATD is transferred to the write control circuit 4 via the interleave amplifier 114 and the latch circuit 116. In write control circuit 4 (BIST control circuit), it is determined whether or not the transferred latch data LATD is data corresponding to a state in which the dummy memory cell is set to a resistance value higher than that of resistance element RHb. (Step S78). The resistance value of resistance element RHb is set to the lower limit allowable value of the electrical resistance value in the high resistance state, as in the case of the flow shown in FIG.

  If it is determined in step S78 that the dummy memory cell is not set in the high resistance state, the write control circuit 4 sends a voltage step control signal to the voltage setting circuit 102 so as to increment the write current. STEP is given (step S79). In accordance with the incremented write current (write voltage), the processes after step S75 are executed again.

  If it is determined in step S78 that the dummy memory cell is set to a higher resistance state than the resistance element RHb, it is determined that data has been correctly written in the dummy memory cell, and then the address AD is final. It is determined whether it is an address (step S86). If the address AD is different from the final address, the address AD is incremented by 1 (step S87), and the processing from step S73 is executed again.

  On the other hand, when it is determined in step S73 that the setting data is data corresponding to the low resistance state, initial setting of the write current and the slow cooling period is performed, and the resistance value of the low resistance resistance element RLa is set. It is set (step S80). Since dummy memory cell DMC is set in a low resistance state, data must be verified using sense amplifier 110 when writing to dummy memory cell DMC. Therefore, low resistance element RLa is coupled to internal data line 136a. The resistance value of the resistance element RLa is set to an allowable upper limit value of the resistance value in the low resistance state.

  Next, data is written (step S81), the low resistance element RLa is selected, and the resistance element RLa and the selected dummy memory cell DMC are respectively connected to the sense amplifier 110 via the internal data line 136a and the dummy internal data line 140a. Combined and internal reading of data is executed (steps S82 and S83).

  The output signal of sense amplifier 110 is transmitted again as data LATD to write control circuit 4 via interleave amplifier 114 and latch circuit 116. The write control circuit 4 determines whether the resistance value of the dummy memory cell DMC is set lower than that of the low resistance element RLa according to the transfer data LATD (step S84). If it is determined in step S84 that the electrical resistance value of the dummy memory cell DMC is higher than the resistance value of the resistance element RLa, the write current is decremented and the slow cooling period is increased (step S85). After changing the write condition in step S85, the data write sequence from step S81 is executed again.

  If it is determined in step S84 that the electrical resistance value of dummy memory cell DMC is lower than resistance element RLa, it is subsequently determined in step S86 whether writing has been performed on the memory cell at the final address. If data is written to a dummy memory cell different from the final address, the address AD is incremented by 1 (step S87), and the process returns to step S73 again.

  On the other hand, when it is determined in step S86 that the address is the final address, it is determined whether or not the next write dummy data exists (step S88). If there is write data to the next dummy memory cell, the process returns to step S72 again, and a write operation for setting the high resistance state or the low resistance state is executed.

  On the other hand, when it is determined in step S88 that data writing to all dummy memory cells DMX and DMC has been completed, dummy writing for writing data to the dummy memory cells is completed.

  By using the resistance values of resistance elements RLa and RHb, dummy memory cells DMX and DMC can be reliably set to a high resistance state and a low resistance state.

  The resistance values of the resistance elements RHa, RHb, RLb, and RLa are the lower limit value and upper limit value of the dummy memory cell that are actually written in the test sequence. (See the flow of FIG. 21), the resistance value may be set or may be set to a value on the specification.

  FIG. 31 is a diagram showing an example of a configuration of a portion for generating dummy bit line selection signals DRSELx and DRSELn shown in FIG. In the configuration shown in FIG. 31, it is assumed that the memory cell is set to high resistance state Rmax in accordance with data D of “1” (H level).

  In FIG. 31, a dummy bit line selection signal generation unit includes an AND gate AG10 receiving read instruction signal READ and data D, an AND gate AG11 receiving read instruction signal READ and complementary data / D, and a dummy write mode instruction signal DMMY. AND gate AD12 receiving the output signal of AND gate AG10, dummy write mode instruction signal DMMY, AND gate AG13 receiving the output signal of AND gate AG11, inverter IV1 inverting dummy write mode instruction signal DMMY, and inverter IV1 An AND gate AG14 that receives the output signal and the read instruction signal READ, an OR gate OG10 that receives the output signal of the AND gate AG14 and the output signal of the AND gate AG12, and generates a dummy bit line selection signal DRSELx, and an AND gate Receiving an output signal and an output signal of the AND gate AG13 of AG14 and an OR gate OG11 for generating a dummy bit line selection signal DRSELn with.

  At the time of data writing to the dummy memory cell, dummy write mode instruction signal DMMY is set to the H level, and AND gates AG12 and AG13 operate as a buffer circuit, while AND gate AG14 follows the output signal of inverter IV1. The output signal is fixed at the L level. Therefore, when write data D is “1” (H level) and indicates a state of setting to a high resistance state, dummy bit line selection signal DRSELx of OR circuit OG10 is selected in accordance with the output signal of AND gate AG10. , Dummy bit line DBL0 is coupled to dummy internal data line 140a.

  On the other hand, when data D is “0” (L level), complementary write data / D is at H level, and dummy bit line selection signal DRSELn from OR circuit OG11 is driven to the selected state.

  Read instruction signal READ is activated when a sense operation is performed in sense amplifiers 110 and 112, and determines a column selection period.

  On the other hand, in the normal operation cycle, dummy write mode instruction signal DMMY is at L level, and the output signal of inverter IV1 is at H level. In this case, the output signals of AND gates AG12 and AG13 are at the L level, and dummy bit line selection signals DRSELx and DRSELn are driven to the selected state in accordance with read instruction signal READ.

  Note that equalize instruction signal EQ shown in FIG. 25 is fixed to L level when data is written to the dummy memory cell, and verify instruction signal VRFY is also maintained in an inactive state when data is written to dummy memory cell. The Generation of these equalize instruction signal EQ and verify instruction signal VRFI is controlled in accordance with dummy write mode instruction signal DMMY.

  FIG. 32 is a diagram showing an example of a configuration of a portion that generates resistance element selection signals LSa, HSa, HSb, and LSb shown in FIG. Also in the configuration shown in FIG. 32, it is assumed that the memory cell is set in the high resistance state when the write data D is at the H level (“1”).

  In FIG. 32, the resistance element selection signal generation unit receives an AND gate AG20 receiving dummy write mode instruction signal DMMY and read instruction signal READ, an output signal of AND gate AG20 and complementary write data / D, and selects a resistance element. AND gate AG21 for generating signal LSa, AND gate AG22 for generating resistance element selection signal HSa in response to the output signal and ground voltage of AND gate AG20, and the output signal and write data D of AND gate AG20 An AND gate AG23 that generates a resistance element selection signal HSb, and an AND gate AG24 that receives the output signal of the AND gate AG20 and the ground voltage and generates a resistance element selection signal LSb.

  When writing data to the dummy memory cell, when the write data D is at the H level and the dummy memory cell is written in the high resistance state Rmax, the resistance element selection signal HSb from the AND gate AG23 is selected. Driven to state. A high resistance element is connected to internal data line 136b, and data of dummy memory cell DMX written in a high resistance state on dummy internal data line 140b can be read and sensed by sense amplifier 112.

  When data D is at L level and a low resistance state is designated, data writing to dummy memory cell DMC is executed. In this case, at the time of data reading, resistance element selection signal LSa from AND gate AG21 is driven to the selected state.

  In the configuration shown in FIG. 32, resistance element selection signals HSa and LSb from AND gates AG22 and AG24 are not particularly used. These four resistance elements are provided in order to allow the dummy bit lines DBL0 and DBL1 to be connected to either of the high resistance state and the low resistance state dummy memory cells. When the dummy memory cells of dummy bit lines DBL0 and DBL1 are allowed to be in either a high resistance state or a low resistance state, in the configuration shown in FIG. 32, address bits specifying dummy bit lines DBL0 and DBL1 are set. This is applied to AND gates AG21-AG24. Data D and complementary write data / D are applied to AND gates AG22 and AG24, respectively. A low resistance resistance element is coupled to the internal data line corresponding to the dummy bit line set to the low resistance state, and a high resistance resistance element is coupled to the internal data line corresponding to the dummy bit line coupled to the high resistance state. Can be connected.

[Modification 1]
FIG. 33 shows a structure of a resistance element selection signal generating portion according to a modification of the second embodiment of the present invention. 33, in addition to the configuration of the resistance element selection signal generator shown in FIG. 32, inverter IV2 receiving dummy write mode instruction signal DMMY, and the output signal of inverter IV2 and reading AND gate AG25 receiving instruction signal READ and address bit A0, AND gate AG26 receiving output signal of inverter IV2, read instruction signal READ and complementary address bit / A0, and output signals of AND gates AG21 and AG25. OR circuit OG15 for generating resistance element selection signal LSa, OR gate OG16 for generating resistance element selection signal HSa in response to the output signals of AND gates AG22 and AG25, and resistors for receiving the output signals of AND gates AG23 and AG26 Generate element selection signal HSb And R gate OG17, and an OR gate OG18 for generating a resistive element select signal LSb receives the output signal of the AND gate AG24 and AG26.

  In the configuration of the resistance element selection signal generating portion shown in FIG. 33, the resistance element selection signal is generated in accordance with the output signals of AND gates AG20 to AG24 when data is written to the dummy memory cell. At the time of data writing to the dummy memory cell, resistance element selection signal HSb for selecting a high resistance element is activated at the time of writing “H” level data D corresponding to the high resistance state. In addition, when data in the low resistance state is written to the dummy memory cell, the resistance element selection signal LSa is generated according to the output signal of the AND gate AG21.

  On the other hand, in the normal operation mode, a resistance element selection signal is generated based on the output signals of AND gates AG25 and AG26 in accordance with address bits A0 and / A0 and read instruction signal READ. In this case, address bit A0 designates an even number column, and complementary address bit / A0 designates an odd number column (when "1"). In this case, when even columns are selected, resistance element selection signals HSb and LSb are driven to a selected state, and a high resistance element and a low resistance element are coupled in parallel to the internal data line shown in FIG. At this time, the dummy memory cell is not used, and the dummy bit line selection signal is in a non-selected state.

  On the other hand, when the odd column is selected, the address bit A0 is driven by the internal data line (136a) in which the resistance element selection signals LSa and HSa are driven to the selected state and the high resistance element and the low resistance element supply the reference potential in parallel. ).

  A high resistance element and a low resistance element are coupled in parallel between a corresponding internal data line and a ground node to equivalently generate a resistance element having an intermediate resistance value and use it as a reference resistance value. In this case, since data is read bit by bit, sense amplifiers 110 and 112 shown in FIG. 25 are also selectively activated according to address bit A0. When the resistance values of resistance elements RHa, RHb, RLa, and RLb shown in FIG. 25 have resistance values that take into account the characteristics of the memory cells (set during the test process), the reference resistance values according to the characteristics of the memory cells Can be read out and verified accurately.

[Modification 2]
FIG. 34 shows a resistance value setting sequence according to the second modification of the second embodiment of the present invention. The resistance value of the reference resistance element is set in consideration of the resistance value of the memory cell.

  As a circuit configuration, a storage device shown in FIG. 25 is used. Hereinafter, an operation sequence for optimizing the resistance value of the resistance element of the memory device shown in FIG. 25 will be described with reference to FIG.

  First, data is written into a predetermined regular memory cell (step S90). In this case, the correspondence relationship between the write data and the address is set in the BIST control circuit of the write control circuit 4.

  After writing data, a data read mode using resistance elements RHa, RHb, RLa, and RLb is set (step S91). At this time, the resistance values of the resistance elements RHa, RHb, RLa, and RLb are also initialized. At the time of this initial setting, the median value of the estimated distributions of the resistance values of the memory cells in the high resistance state and the low resistance state may be set as the initial resistance value. In order to obtain the lower limit value of the resistance value in the high resistance state and the upper limit resistance value in the low resistance state, the resistance value is initially set to an appropriate value in consideration of the search time and the like.

  Next, it is determined whether the target data as read data is data in the high resistance state Rmax (step S92).

  When reading the data of the memory cell in the high resistance state, the high resistance elements RHa and RHb are selected (step S93). Data reading is performed using resistance elements RHa and RHb having high resistance (step S94). In this case, the resistance element is selected based on the address bit so that the selected bit line and the internal data line to which the high resistance resistance element is connected do not collide. In the internal data read mode, verify instruction signal VRFY shown in FIG. 25 is set to an active state, and dummy internal data lines 140a and 140b are connected to internal data lines 136b and 136a, respectively. During the sensing operation by sense amplifiers 110 and 112, the sensing operation can be accurately performed using the sense amplifier coupled to the internal data line to which the selected bit line is connected regardless of the position of the selected bit line (address bit). The selected sense amplifier is determined by A0).

  A determination as to whether or not the expected value is satisfied is made based on the read data of the sense amplifier (step S95). When it is determined that the read memory cell data has a resistance value lower than the resistance value of the high resistance element, the resistance value of the high resistance element is decremented. Is changed (step S96). Next, the data read operation from step S94 is performed again. By these operations, the resistance value is repeatedly decremented until the memory cell data is accurately read.

  If it is determined in step S95 that it matches the expected value, it is determined whether the address AD is final (step S97). If it is not the final address, the address is incremented by 1 (step S98). The operation from step S94 is executed again. At this time, the resistance value of the high resistance element is not changed, and is maintained in the decremented state in step S96.

  If it is determined in step S97 that the address AD is final, the resistance value of the high resistance resistance element is registered in the ROM in the write control circuit (step S99). Thereby, the lower limit value of the electrical resistance value of the memory cell in the high resistance resistance state can be detected.

  On the other hand, if it is determined in step S92 that the target data is data corresponding to the low resistance state Rmin, a low resistance element is selected (step S100). Next, the low resistance element is selected and data is read (step S101), and a determination is made as to whether it matches the expected value (step S102). If it is determined in step S102 that the memory cell data is higher than the resistance value of the low-resistance resistance element, the resistance value is incremented (step S103), and the operation from step S101 is repeated again. By incrementing the resistance value until the memory cell data is correctly read, the upper limit value of the electrical resistance of the memory cell in the low resistance state can be detected.

  If it is determined in step S102 that it exactly matches the expected value, it is determined whether the address AD is final. If the memory cell still remains and is not the final address, the address 1 is incremented (step S102). (S105), the operation from step S101 is executed again.

  If it is determined in step S104 that the address AD is final, the resistance value of the low resistance element at this time is registered in the ROM in the write control circuit 4 (step S99).

  By this series of operations, it is possible to detect the lower limit value of the electrical resistance value in the high resistance state and the upper limit value of the electrical resistance value in the low resistance state in the resistance value distribution of the memory cell. At the time of normal data reading (including verify operation), the high resistance element and the low resistance element are coupled in parallel to the internal data line, thereby providing a sufficient margin for H level data and L level data. An accurate reference resistance value having the above can be set according to the memory cell characteristics.

  Therefore, as shown in FIG. 35, by connecting the high resistance element RH and the low resistance element RL set to the measured high resistance lower limit value and the measured low resistance upper limit value in parallel to the internal data line, the average of these values is obtained. The value can be used as a reference resistance value, and accurate data reading and verification with a sufficient margin can be performed for memory cells in a high resistance state and a low resistance state.

  Note that it is not particularly required to measure the resistance values of all the memory cells when measuring the resistance value distribution of the memory cells. The memory cell region set to the high resistance state Rmax and the low resistance state Rmin is limited to a part of the region, and the memory cells in this region are selected as a population representative of the memory cells in the memory cell array, The resistance value distribution may be measured. Alternatively, the resistance distribution may be measured only for the dummy memory cell, assuming that the dummy memory cell represents the characteristic of the normal memory cell of the memory cell array.

  By executing the setting of the resistance value of the resistance element in the initialization sequence, the characteristic of the electric resistance value varies for each chip even when the characteristic varies for each memory cell, and is set in advance. Even if the resistance value of the reference resistance element does not provide a sufficient read margin, the resistance value of the reference resistance element can be set according to the actual resistance distribution of the memory cell, and a sufficient read margin is ensured. be able to.

  For each memory cell, the resistance value is stored for each address in the BIST control circuit, and the actual high resistance lower limit value and low resistance upper limit value are detected based on the distribution of resistance values for each memory cell. Also good. In this case, it is always necessary to change the resistance value from the initial setting value in each measurement cycle, and although it takes a little time, an accurate distribution of the resistance value can be obtained.

  As described above, according to the second embodiment of the present invention, even in the phase change memory, after the data writing, the verify operation for verifying whether the write data is correctly written is performed, and based on this verify operation. Thus, the data is rewritten by changing the write condition, so that accurate data can be written.

  In addition, the resistance value of the reference resistance element is set according to the actual characteristics of the memory cell, and data can be read with a sufficient margin for data reading (including verify operation).

  Also, by connecting a high-resistance resistor element and a low-resistance resistor element in parallel and using it as a reference resistor, data reading can be performed accurately using a resistor having an intermediate value between high resistance and low resistance as a reference resistor. Can be done.

[Embodiment 3]
FIG. 36 schematically shows a structure of a main portion of the resistance value change storage element according to the third embodiment of the present invention. The storage device shown in FIG. 36 differs from the storage device according to the second embodiment shown in FIG. 25 in the following points. That is, the write control circuit 140 is provided with a current write condition storage circuit 142 for storing a write condition when a write verify operation is performed. Write control circuit 140 that controls the write operation at the time of data writing corresponds to write control circuit 4 shown in FIG. 25, and sets write conditions for write condition setting circuit 5 as current write condition storage circuit 142. Is initialized based on the writing conditions stored in the. The other configuration of the storage device shown in FIG. 36 is the same as that of the storage device shown in FIG. 25, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 37 is a flowchart showing an operation at the time of data writing of the storage device shown in FIG. The processing operation flow at the time of data writing shown in FIG. 37 is different from the processing operation flow shown in FIG. 26 in the following processing steps. After step S52 for determining whether the write data is in the high resistance state Rmax, the write condition is initially set. In the initial setting of the write condition, if the write data corresponds to the high resistance state, the initial setting of the write current is performed in accordance with the write condition stored in the current write condition storage circuit 142 in step S110. In addition, the resistance values of the high resistance resistance elements RHa and RHb are set. On the other hand, in the case of the write data corresponding to the low resistance state, in step S112, initial setting of the write current and the slow cooling period is performed according to the write condition stored in the current write condition storage circuit 142. The resistance value of resistance element RLa or RLb is initialized.

  After the initial setting of the write conditions, the processing steps for writing data and verifying the data are the same as the processing steps shown in FIG. 26, and the corresponding steps are denoted by the same step numbers and will be described in detail. Is omitted.

  If it is determined in the determination step S57 or S64 that data has been correctly written in the memory cell, in addition to the resistance value of the resistance element at that time, the write condition, the write current value gradual cooling period width Is stored in the current write condition storage circuit 142 (step S114). Thereafter, the process of step S59 for determining whether the next data is write data is executed.

  In the phase change memory, when data is written, a current is supplied to the heater, and the phase change material is melted by Joule heat generated by the heater. Thereafter, the phase change material is set to an amorphous state by rapid cooling, and the phase change material is set to a crystalline state by slow cooling, and resistance values of these amorphous state and crystalline state are set. Use the difference to store the data. Therefore, when the verify operation is performed in setting the current at the time of data writing and the data writing operation is repeatedly executed, the endurance (life) characteristic of the phase change material is impaired, and the deterioration of the phase change element is accelerated.

  When the write condition is changed, after the data writing is completed, the write condition at that time is stored in the current write condition storage circuit 142, and the next data write is stored in the current write condition storage circuit 142. Data is written by setting the write current condition according to the written condition.

  Therefore, every time, when the initial value is set irrespective of the previous writing condition, it is necessary to rewrite data M times, when data writing is executed N times, M · N times, Loss of endurance characteristics of the phase change material occurs. When variation in memory cell characteristics is small, first, it is only required to rewrite data M times in order to set a write condition. When data is written N times, M + N times. Only the endurance characteristic is damaged, and the limit of the number of data rewrites can be greatly increased.

  Under this write condition, the write current is incremented when writing data in the high resistance state. However, the supply time of the write current may be changed. Further, even when data corresponding to the low resistance state is written, the write current may be constant and incremented only during the slow cooling period.

  As described above, according to the third embodiment of the present invention, the data write and verify operations are performed using the data write condition as the starting write condition when the previous data write is completed. The number of times of rewriting in data writing can be reduced, deterioration of element characteristics can be prevented, and time required for data writing can be shortened.

  The resistance value change memory device can be used for various data storage applications, and the present invention can be applied to a data writing system and a data reading system of such a resistance value change memory device.

1 is a diagram schematically showing an overall configuration of a resistance value change storage device according to the present invention; FIG. 1 is a diagram schematically showing a configuration of a memory cell used in Embodiment 1 of the present invention. FIG. It is a figure which shows roughly the structure of the principal part of the memory | storage device according to Embodiment 1 of this invention. FIG. 4 is a diagram showing an example of a configuration of a write voltage generation circuit shown in FIG. 3. FIG. 4 is a diagram showing a modification of the write voltage generation circuit shown in FIG. 3. FIG. 4 is a diagram showing another configuration of the write voltage generation circuit shown in FIG. 3. FIG. 4 is a diagram showing an example of a configuration of a digit line driving circuit shown in FIG. 3. FIG. 4 is a diagram showing another configuration of the digit line drive circuit shown in FIG. 3. FIG. 4 is a diagram more specifically showing the configuration of the memory cell array 1 shown in FIG. 3. FIG. 10 is a diagram more specifically showing the configuration of a digit line peripheral circuit section shown in FIG. 9. It is a figure which shows the magnetization characteristic of a memory cell. It is a flowchart which shows the data writing sequence in Embodiment 1 of this invention. It is a figure which shows the change of the write conditions at the time of the data writing in Embodiment 1 of this invention. It is a figure which shows the other example of the example of a change of the data writing condition in Embodiment 1 of this invention. It is a figure which shows the data write sequence of the example of a change of Embodiment 1 of this invention. FIG. 16 is a diagram showing how data write conditions are changed in the operation flow shown in FIG. 15. FIG. 17 is a diagram showing a write condition changing sequence in the operation sequence shown in FIG. 16. It is a figure which shows the relationship between the electrical resistance value of the dummy memory cell of Embodiment 1 of this invention, and the electrical resistance value of a normal memory cell. It is a flowchart which shows the data write sequence to the dummy memory cell in Embodiment 1 of this invention. It is a flowchart which shows the other example of the data write sequence to the dummy memory cell in Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the example 1 of a change of Embodiment 1 of this invention. It is a figure which shows the relationship between the electrical resistance value distribution of the memory cell and the resistance value of a reference resistive element in the modification 1 of Embodiment 1 of this invention. It is a figure which shows an example of the structure at the time of the resistance element selection in the modification 1 of Embodiment 1 of this invention. It is a figure which shows schematically the structure of the memory | storage device in Embodiment 2 of this invention. It is a figure which shows roughly the structure of the principal part of the memory | storage device according to Embodiment 2 of this invention. It is a flowchart which shows the data writing sequence in Embodiment 2 of this invention. FIG. 27 is a diagram showing a change sequence when a write current is incremented in FIG. 26. FIG. 27 is a diagram showing a change sequence at the time of increment of the write current decreasing and slow cooling period shown in FIG. 26. It is a figure which shows the data write cycle to the dummy memory cell in Embodiment 2 of this invention. It is a flowchart which shows the data write sequence to the dummy memory cell in Embodiment 2 of this invention. It is a figure which shows an example of a structure of the part which generate | occur | produces the dummy bit line selection signal in Embodiment 2 of this invention. It is a figure which shows the structure of the part which generate | occur | produces the resistive element selection signal in Embodiment 2 of this invention. It is a figure which shows an example of a structure of the part which generate | occur | produces the resistance element selection signal in the modification 1 of Embodiment 2 of this invention. It is a flowchart which shows the reference resistance value measurement operation | movement of Embodiment 2 of this invention. FIG. 35 is a diagram showing a relationship between an electrical resistance value of a memory cell and a reference resistance value in the flowchart shown in FIG. 34. It is a figure which shows roughly the structure of the principal part of the memory | storage device according to Embodiment 3 of this invention. It is a flowchart which shows the data rewriting sequence of the memory | storage device of Embodiment 3 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Memory cell array, 2 Write system circuit, 3 Read system circuit, 4 Write control circuit, 5 Write condition setting circuit, 8 Main control circuit, 15 Write voltage generation circuit, 20 Digit line drive circuit, 22 Bit line drive Circuit, 30 word line drive circuit, 52 BIST control circuit, 54 ROM, RVRa, RVRb reference resistance element, 50 comparison circuit, M normal memory cell, DMC0, DMC1 dummy memory cell, 102 voltage setting circuit, 104 voltage generation circuit, RHa , RHb, RLa, RLb Reference resistance element, 140 write control circuit, 142 current write condition storage circuit, DMX, DMC dummy memory cell.

Claims (11)

A plurality of memory cells including a plurality of variable resistance elements whose electrical resistance values are set according to stored data;
A writing circuit for writing data to the selected memory cell when writing data to the selected memory cell of the plurality of memory cells;
Program memory for storing data write conditions, and data written by the write circuit by setting the write conditions for the write circuit according to the write conditions stored in the program memory when the data is written Is read from the selected memory cell, it is determined whether the read data corresponds to the write data, and when the determination result indicates a failure, the write condition is changed to reactivate the write circuit, A resistance value change storage device comprising: a write control circuit for storing the write condition in the program memory when the determination result indicates good. The memory cell has its electrical resistance value set according to a write current supplied from the write circuit during data write,
The resistance value change storage device according to claim 1, wherein the write control circuit changes the write current amount. The memory cell has its electrical resistance value set according to a write current supplied from the write circuit during data write,
The resistance value change memory device according to claim 1, wherein the write control circuit changes a time for applying a write current to the selected memory cell by the write circuit. A plurality of memory cells each including a variable resistance element whose electrical resistance value is set according to stored data;
Internal data bus,
A selection circuit for coupling selected memory cells of the plurality of memory cells to the internal data bus;
A resistance variable memory device comprising: a reference resistance element having a known resistance value; and an internal read circuit that generates internal read data by comparing a current flowing through the selected memory cell with a current flowing through the reference resistance element. The reference resistance element is
A first resistance element having a first resistance value;
A second resistance element having a second resistance value higher than the first resistance value,
The resistance value change storage device further includes:
5. The resistance value change storage device according to claim 4, further comprising a circuit that selects one of the first and second resistance elements in accordance with write data of the selected memory cell in a data write mode. The internal data bus includes first and second internal data lines,
The plurality of memory cells include a plurality of normal memory cells that store data, and a plurality of dummy cells that store data serving as data determination criteria when reading data from the normal memory cells,
The selection circuit includes:
5. When reading data, a normal memory cell and a dummy cell are selected as the selected memory cell and coupled to the first and second internal data lines, respectively, and the reference resistance is separated from the internal data line. Resistance value change type storage device.   5. The resistance value change storage device according to claim 4, further comprising a control circuit that changes a resistance value of the resistance element in accordance with a comparison result between the internal read data and expected value data. The plurality of memory cells include a normal memory cell that stores data, and a dummy cell that stores determination reference data at the time of data reading of the normal memory cell,
The resistance value change storage device further includes:
Write control for determining whether data is correctly written to the dummy cell according to a comparison result of resistance values of the dummy cell and the resistance element after writing data to the dummy cell at the time of data writing to the dummy cell The resistance value change storage device according to claim 4, further comprising a circuit.   The resistance value change type according to claim 8, wherein when the write control circuit determines that the data is not correctly written, the write control circuit changes the write condition to the dummy cell and writes the data again. Storage device.   The resistance value change type according to claim 4, further comprising a circuit that reads data of the plurality of memory cells and sets a resistance value of the resistance element according to a distribution of resistance values corresponding to storage states of data of different logic levels. Storage device. The plurality of memory cells are set to at least one of a low resistance state and a high resistance state according to stored data,
The reference resistance element is
A high resistance element having a resistance value corresponding to a resistance value of the plurality of memory cells in a high resistance state;
A low resistance element having a resistance value corresponding to a resistance value in a low resistance state of the plurality of memory cells,
5. The resistance variable memory device according to claim 4, wherein the high resistance element and the low resistance element are coupled to the internal read circuit in parallel in a data read mode.

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