KR100934853B1 - Phase change memory device - Google Patents

Abstract

The present invention relates to a phase change memory device, and discloses a technique for stably writing data to a cell by performing a write verification operation. To this end, the present invention provides a cell array unit including a phase change resistance cell disposed at an area where word lines and bit lines intersect, a sense amplifier for sensing and amplifying data of the phase change resistance cell, and an enable signal. A write driver for supplying a write voltage corresponding to the data to be written to the cell array unit, and a write verification controller which is controlled by an activation control signal and compares the data read through the sense amplifier with the data to be written and outputs an enable signal. It includes.

Phase Change Resistor, Light Verification

Description

Phase change memory device {PHASE CHANGE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device, and more particularly, to a technique for stably writing data to a cell by performing a write verification operation in a write operation mode.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM), and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for describing a conventional phase change resistor (PCR) device.

The phase change resistance element 4 inserts a phase change material (PCM) 2 between the upper electrode 1 and the lower electrode 3 to apply a voltage and a current to the phase change layer 2. The high temperature is induced to change the state of electrical conduction due to the change in resistance.

Here, AglnSbTe is mainly used as the material of the phase change layer 2. As a material of the phase change layer 2, a compound containing chalcogen element (S, Se, Te) as a main component may also be used. Specifically, germanium antimony tellurium composed of Ge-Sb-Te may be used. An alloy material (Ge 2 Sb 2 Te 5) is used.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current below a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 becomes a crystalline phase and becomes a material of a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, when the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the upper electrode 1 and the lower electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the upper electrode 1 and the lower electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the SET state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

The present invention has the following object.

First, in a phase change memory device, a write verification operation can be performed to stably write data to a cell.

Second, in the phase change memory device, the write operation mode in the set state and the write operation mode in the reset state can be controlled separately.

Third, in the phase change memory device, the set write driver may be shared in the write operation mode of the reset state to reduce power consumption in the write operation.

A phase change memory device according to the present invention includes a cell array unit including a phase change resistance cell disposed in an area where a word line and a bit line cross each other; A sense amplifier for sensing and amplifying data of the phase change resistance cell; A write verification control unit controlled by the activation control signal and outputting a set enable signal or a reset enable signal by comparing data read through the sense amplifier with data to be written to the phase change resistance cell; A set write driver supplying a write voltage corresponding to the set data to the cell array unit according to the set enable signal; And a reset write driver supplying a write voltage corresponding to the reset data to the cell array unit according to the reset enable signal.

The present invention provides the following effects.

First, in a phase change memory device, a write verification operation is performed to provide an effect of stably writing data to a cell.

Second, in the phase change memory device, the write operation mode in the set state and the write operation mode in the reset state are separately controlled.

Third, in the phase change memory device, the set write driver may be shared in the write operation mode of the reset state to reduce power consumption in the write operation.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a circuit diagram of a phase change memory device according to the present invention.

The present invention includes a cell array unit 10, a column selector 20 and a sense amplifier S / A, a write driver W / D, and a write verification controller WVC.

In the cell array unit 10, a plurality of bit lines BL0 to BL2 are arranged in a column direction, and a plurality of word lines WL0 to WL3 are arranged in a row direction. The cell array unit 10 includes a unit phase change resistance cell C disposed in an area where a plurality of bit lines BL0 to BL2 and a plurality of word lines WL0 to WL3 cross each other. Here, the unit phase change resistance cell C includes a phase change resistance element PCR and a PN diode D.

One side of the phase conversion resistance element PCR is connected to the word line WL, and the other side is connected to the N-type region of the PN diode. The P-type region of the PN diode D is connected to the bit line BL, and the N-type region is connected to the word line WL. The phase of the phase change resistance element PCR is changed in accordance with the set current Iset and the reset current Ireset flowing in each bit line BL to write data.

The column selector 20 is connected between the bit lines BL0 to BL2 of the cell array unit 10 and the input / output line I / 0_0 to receive a plurality of switching elements receiving a plurality of column select signals CS_0 to CS_2 through the gate terminal. Include. Here, it is preferable that the some switching element consists of NMOS transistors N1-N3.

The sense amplifier S / A distinguishes reset data from set data by comparing the cell data applied through the input / output line I / O_0 with the reference current Iref. The write driver W / D supplies the write voltage corresponding to the write data to the input / output line I / O_0 when writing data to the cell. The write verification controller WVC controls the write driver W / D according to whether the data written to the cell and the data applied to the input / output line I / O_0 are the same.

5 is a circuit block diagram of a phase change memory device according to the present invention.

The present invention includes a cell array unit 10, a column selector 20, a sense amplifier S / A, a write driver W / D, and a write verification controller WVC.

Here, one end of the column selector 20_1 is connected in a one-to-one correspondence with the bit lines BL0 to BLn of the cell array unit 10, and the other end is commonly connected to the input / output line I / O_0. One end of the column selector 20_2 is connected in a one-to-one correspondence with the bit lines BL0 to BLn of the cell array unit 10, and the other end is commonly connected to the input / output line I / O_m.

The sense amplifiers S / A_0 and the write driver W / D_0 are connected to the input / output line I / O_0, respectively, and the sense amplifiers S / A_m and the write driver W / D_m are connected to the input / output line I / O_m.

The write verification control unit WVC_0 is controlled by the reset activation control signal Reset_con and the set activation control signal Set_con to compare the data on the global input / output line GI / O_O with the output signal Saout of the sense amplifier S / A to reset the reset enable signals Reset_en and Output the set enable signal Set_en.

The write verification control unit WVC_m is controlled by the reset enable control signal Reset_con and the set enable control signal Set_con to compare the data on the global input / output line GI / O_m with the output signal Saout of the sense amplifier S / A to reset the reset signal Reset_en and set in. Outputs the enable signal Set_en.

Here, terms for the set data and reset data and the signal level of the global input / output line GI / O used in the present invention are defined as shown in Table 1 below.

TABLE 1

Terms Set data Reset data Data definition Data "0" Data "1" Global I / O Line GI / O Signal Levels  0  One

That is, the set data is defined as data "0" and means logic state "0". The reset data is then defined as data "1", meaning logic state "1".

6 is a detailed circuit diagram of the sense amplifier S / A, the write driver W / D, and the write verification controller WVC according to the first embodiment of the present invention.

The sense amplifier S / A compares the cell data applied through the input / output line I / O_m with the reference current Iref and outputs the output signal Saout.

The write driver W / D includes an NMOS transistor N4, a PMOS transistor P1, a set write driver 30, and a reset write driver 40.

Here, the NMOS transistor N4 is connected between the input / output line I / O and the set write driver 30 to receive the set enable signal Set_en through the gate terminal. The PMOS transistor P1 is connected between the input / output line I / O and the reset write driver 40 to receive the reset enable signal Reset_en through the gate terminal.

The set write driver 30 supplies a write voltage corresponding to the set data to the input / output line I / O in the write operation mode. The reset write driver 40 supplies a write voltage corresponding to the reset data to the input / output line I / O in the write operation mode.

The write verification controller WVC includes a sense amplifier switching unit 50, a flag register 60, a comparator 70, an enable signal generator 80, and a data latch unit 90.

The sense amplifier switching unit 50 includes an NMOS transistor N5. The NMOS transistor N5 is connected between the output signal Saout of the sense amplifier S / A and the global input / output line GI / O to receive the read switching signal RSW through the gate terminal.

The flag register 60 includes a transfer unit 62 and a latch 64. The transfer unit 62 includes an NMOS transistor N6. The NMOS transistor N6 is connected between the output signal Saout applying end of the sense amplifier S / A and the latch 64 to receive the latch enable signal Len through the gate terminal.

In addition, the latch 64 includes inverters IV2 and IV3. The inverter IV2 receives the output of the transfer unit 62 and inverts the output, and the inverter IV3 receives the output of the inverter IV2 and inverts it to output the flag signal Flag. Here, the flag signal Flag preferably has the same polarity as that of the data output from the sense amplifier S / A.

The comparator 70 includes an exclusive ora gate XOR1. The exclusive OR gate XOR1 receives the flag signal Flag and data contained in the latch global I / O line LGI / O, and performs an exclusive OR operation to output the comparison signal Comp.

The enable signal generator 80 includes NAND gates ND1 and ND2 and inverters IV1 and IV4. The NAND gate ND1 receives a set activation control signal Set_con, an output signal of the inverter IV4, a write enable signal We, and a comparison signal Comp, and outputs a NAND operation.

The NAND gate ND2 receives the reset enable control signal Reset_con, the data loaded on the latch global input / output line LGI / O, the write enable signal We, and the comparison signal Comp, and then performs a NAND operation to output the reset enable signal Reset_en.

The inverter IV1 receives the output of the NAND gate ND1 and inverts it to output the set enable signal Set_en. Inverter IV4 receives the data loaded on the latch global input / output line LGI / 0, and inverts the output.

The data latch unit 90 includes a transfer unit 92 and a latch 94. The transfer unit 92 includes an NMOS transistor N7. The NMOS transistor N7 is connected between the latch 94 and the global input / output line GI / O to receive the write latch enable signal WLen through the gate terminal.

Latch 94 includes inverters IV5 and IV6. Inverter IV5 receives the output of inverter IV6 and inverts it to output to the latch global I / O line LGI / O. The inverter IV6 receives the output of the transfer unit 92 and inverts the output.

The operation of the sense amplifier S / A, the write driver W / D, and the write verification controller WVC according to the first embodiment of the present invention having the above configuration will be described with reference to Table 2 below.

TABLE 2

Global I / O Line GI / O Flag signal Flag Comparison Signal Comp Set Enable Signal Set_en Reset Enable Signal Reset_en Set data Set data 0 Disabled Disabled Reset data Reset data 0 Disabled Disabled Set data Reset data One Activation Disabled Reset data Set data One Disabled Activation

First, when the data of the selected cell C is loaded on the input / output line I / O, the sense amplifier S / A senses and amplifies the data of the selected cell C and outputs it to the output signal Saout. At this time, the read switching signal RSW remains in an inactive state at a low level. As a result, the NMOS transistor N5 maintains the turn-off state.

The latch enable signal Len is then activated to a high level. Then, the NMOS transistor N6 is turned on so that the output signal Saout of the sense amplifier S / A is transferred to the latch 64. The latch 64 receives the output signal Saout of the sense amplifier S / A and latches it to output the flag signal Flag.

The write latch enable signal WLen is activated at a high level. Then, the NMOS transistor N7 is turned on and data loaded on the global input / output line GI / O is transferred to the latch 94. The latch 94 latches data loaded on the global input / output line GI / O and outputs the latched data to the global input / output line LGI / O.

The exclusive OR gate XOR1 then performs an exclusive OR operation on the flag signal Flag and the data carried on the latch global I / O line LGI / O to output the comparison signal Comp. At this time, if the data on the flag global I / O line LGI / O and the flag signal Flag are the same, the comparison signal Comp is output at a low level. If the data on the latch global I / O line LGI / O and the flag signal Flag signal are different, the comparison signal Comp is Output is at high level.

If the comparison signal Comp is output at a low level, the set enable signal Set_en is deactivated at a low level, and the reset enable signal Reset_en is deactivated at a high level. Accordingly, the write voltage output through the set write driver 30 and the reset write driver 40 is no longer applied to the input / output line I / O. That is, if the data stored in the selected cell C and the data to be written are the same, the write cycle is terminated without performing a new write operation. As a result, the number of reset and set write operations can be reduced.

On the other hand, when the comparison signal Comp is output at a high level, the set write mode operation and the reset write mode operation are independently performed. In the set write mode, the set activation control signal Set_con becomes active at a high level. At this time, the write enable signal We maintains an active state at a high level, and the reset enable control signal Reset_con maintains an inactive state at a low level.

When the data loaded on the global input / output line GI / O is set data, the set enable signal Set_en is activated to a high level. Accordingly, the NMOS transistor N4 is turned on and the write voltage output through the set write driver 30 is applied to the input / output line I / O. Then, the set data is written to the selected cell C.

During the reset write mode operation, the reset activation control signal Reset_con becomes active at a high level. At this time, the write enable signal We maintains the activation state at the high level, and the set activation control signal Set_con maintains the deactivation state at the low level.

When the data loaded on the global input / output line GI / O is reset data, the reset enable signal Reset_en is activated to a low level. Accordingly, the PMOS transistor P1 is turned on and the write voltage output through the reset write driver 40 is loaded on the input / output line I / O. Then, the reset data is written to the selected cell C.

7 is a detailed circuit diagram of a sense amplifier S / A, a write driver W / D, and a write verification controller WVC according to a second embodiment of the present invention.

The sense amplifier S / A compares the cell data applied through the input / output line I / O_m with the reference current Iref and outputs the output signal Saout.

The write driver W / D includes an NMOS transistor N8, a PMOS transistor P2, a set write driver 200, and a reset write driver 210.

Here, the NMOS transistor N8 is connected between the input / output line I / O and the set write driver 200 to receive the set enable signal Set_en through the gate terminal. The PMOS transistor P2 is connected between the input / output line I / O and the reset write driver 210 to receive the reset enable signal Reset_en through the gate terminal.

The set write driver 200 supplies a write voltage corresponding to the set data to the input / output line I / O in the write operation mode. The reset write driver 210 supplies a write voltage corresponding to the reset data to the input / output line I / O in the write operation mode.

The write verification controller WVC includes a sense amplifier switching unit 220, a flag register 230, a comparator 240, an enable signal generator 250, and a data latch unit 260.

The sense amplifier switching unit 220 includes an NMOS transistor N9. The NMOS transistor N9 is connected between the output signal Saout of the sense amplifier S / A and the global input / output line GIO to receive the read switching signal RSW through the gate terminal.

The flag register 230 includes a transfer unit 232 and a latch 234. The transfer unit 232 includes an NMOS transistor N10. The NMOS transistor N10 is connected between the output signal Saout applying end of the sense amplifier S / A and the latch 234 to receive the latch enable signal Len through the gate terminal.

The latch 234 includes inverters IV8 and IV9. The inverter IV8 receives the output of the transfer unit 232 and inverts the output, and the inverter IV9 receives the output of the inverter IV8 and inverts and outputs the flag signal Flag.

The comparison unit 240 includes an exclusive ora gate XOR2. The exclusive OR gate XOR2 receives the flag signal Flag and the data contained in the latch global I / O line LGI / O, and performs an exclusive OR operation to output the comparison signal Comp.

The enable signal generator 250 includes NAND gates ND3, ND4, and inverter IV7. The NAND gate ND3 receives the set activation control signal Set_con, the write enable signal We, and the comparison signal Comp, and outputs a NAND operation.

The NAND gate ND2 receives a reset enable control signal Reset_con, data loaded on the global input / output line GI / O, a write enable signal We, and a comparison signal Comp, and performs a NAND operation to output a reset enable signal Reset_en.

Inverter IV7 receives the output of NAND gate ND3 and inverts it to output set enable signal Set_en.

The data latch unit 260 includes a transfer unit 262 and a latch 264. The transfer unit 262 includes an NMOS transistor N11. The NMOS transistor N11 is connected between the latch unit 264 and the global input / output line GI / O to receive the write latch enable signal WLen through the gate terminal.

Latch 264 includes inverters IV10 and IV11. Inverter IV10 receives the output of inverter IV11 and inverts it to output to the latch global I / O line LGI / O. The inverter IV11 receives the output of the transfer unit 262 and inverts the output.

The operations of the sense amplifier S / A, the write driver W / D, and the write verification controller WVC according to the second embodiment of the present invention having the above configuration will be described with reference to Table 3 below.

TABLE 3

Global I / O Line GI / O Flag signal Flag Comparison Signal Comp Set Enable Signal Set_en Reset Enable Signal Reset_en Set data Set data 0 Disabled Disabled Reset data Reset data 0 Disabled Disabled Set data Reset data One Activation Disabled Reset data Set data One Activation Activation

First, when the data of the selected cell C is loaded on the input / output line I / O, the sense amplifier S / A senses and amplifies the data of the selected cell C and outputs it to the output signal Saout. At this time, the read switching signal RSW remains in an inactive state at a low level. As a result, the NMOS transistor N8 maintains a turn-off state.

The latch enable signal Len is then activated to a high level. Then, the NMOS transistor N9 is turned on to transmit the output signal Saout of the sense amplifier S / A to the latch 234. The latch 234 receives the output signal Saout of the sense amplifier S / A and latches it to output the flag signal Flag.

The write latch enable signal WLen is activated at a high level. Then, the NMOS transistor N11 is turned on, and data loaded on the global input / output line GI / O is transferred to the latch 264. The latch 264 latches data loaded on the global input / output line GI / O and outputs the latched data to the global input / output line LGI / O.

The exclusive OR gate XOR2 then performs an exclusive OR operation on the flag signal Flag and the data carried on the latch global I / O line LGI / O to output the comparison signal Comp. At this time, if the data on the flag global I / O line LGI / O and the flag signal Flag are the same, the comparison signal Comp is output at a low level. If the data on the latch global I / O line LGI / O and the flag signal Flag signal are different, the comparison signal Comp is Output is at high level.

If the comparison signal Comp is output at a low level, the set enable signal Set_en is deactivated at a low level, and the reset enable signal Reset_en is deactivated at a high level. Accordingly, the write voltage output through the set write driver 200 and the reset write driver 210 is no longer applied to the input / output line I / O. That is, if the data stored in the selected cell C and the data to be written are the same, the write cycle is terminated without performing a new write operation. As a result, the number of reset and set write operations can be reduced.

On the other hand, when the comparison signal Comp is output at a high level, the set write mode operation and the reset write mode operation are performed together. That is, the set activation control signal Set_con and the reset activation control signal Reset_con are activated to a high level. At this time, the write enable signal We remains active at a high level.

Next, when set data is loaded on the global input / output line GI / O, the set enable signal Set_en is activated at a high level, and the reset enable signal Reset_en is deactivated at a high level. Accordingly, the NMOS transistor N8 is turned on and the write voltage output through the set write driver 200 is applied to the input / output line I / O. Then, the set data is written to the selected cell C.

On the other hand, when reset data is loaded on the global input / output line GI / O, the reset enable signal Reset_en is activated at a low level. At this time, the set enable signal Set_en is also activated to a high level. Accordingly, the NMOS transistor N8 and the PMOS transistor P2 are turned on so that the write voltage output through the set write driver 200 and the reset write driver 210 is loaded on the input / output line I / O. Then, the reset data is written to the selected cell C.

8 is an operation timing diagram in a set write operation mode according to the first embodiment of the present invention.

The data of the selected cell C is read in the period t1. That is, the sense amplifier S / A senses and amplifies the data of the selected cell C and outputs it to the output signal Saout. The flag register 60 latches the output signal Saout of the sense amplifier S / A and outputs it as the flag signal Flag. At this time, the write enable signal We maintains a deactivation state at a low level, and the set activation control signal Set_con maintains a deactivation state at a low level.

When the write cycle starts in the t2 section, the write enable signal We is activated to a high level. The set data is loaded on the global input / output line GI / O. At this time, the write latch enable signal WLen is activated to a high level so that the set data is latched through the data latch unit 90 and loaded on the latch global input / output line LGI / O.

Then, the comparing unit 70 compares the flag data Flag with the set data carried on the latch global input / output line LGI / O.

Here, when the set data loaded on the latch global I / O line LGI / O and the flag signal Flag are the same, the comparison signal Comp is inactivated to a low level and the set enable signal Set_en is inactivated to a low level.

On the other hand, when the set data carried on the latch global I / O line LGI / O and the flag signal Flag are different, the comparison signal Comp is activated to a high level. In this case, in the first case where the comparison signal Comp is activated during the period t2 and t3 (Case 1), the set enable signal Set_en is activated to the high level only during the period t2. Accordingly, the write voltage is applied to the selected unit cell C through the set write driver 30 for the period t2.

Then, it is verified whether or not set data is normally written to the selected unit cell C in the period t3. That is, the data of the selected unit cell C is read back through the sense amplifier S / A. The data Saout read in the selected unit cell C is latched through the flag register 60 and output as a flag signal Flag.

The comparison unit 70 then compares the flag signal Flag with the set data carried on the latch global I / O line LGI / O. At this time, the set activation control signal Set_con maintains an inactive state.

Accordingly, when the flag signal Flag and the set data loaded on the latch global input / output line LGI / O are the same, the set enable signal Set_en is deactivated. That is, in the first case (Case 1), if the set data is a pass condition, the write cycle is terminated.

On the other hand, when the flag signal Flag and the set data loaded on the latch global I / O line LGI / O are different, the set data is written by applying the second case (Case 2). That is, the comparison signal Comp is kept active for the period t2, t3, t4, and t5. Then, the set enable signal Set_en is activated to a high level in the periods t2 and t4.

Accordingly, the write voltage is applied to the selected cell C through the set write driver 30 for the period t2 and t4.

The set data is normally written to the selected unit cell C in the t5 section. As a result of the verification, in the second case (Case 2), the write cycle is terminated when the set data becomes a pass condition. On the other hand, when the set data is a fail condition, the third case (Case 3) is applied.

In this manner, in the write operation mode, the activation period of the set enable signal Set_en is changed to write the set data to the selected cell C, and the operation of verifying whether the set data is normally written is repeated. Here, in the write and verify operation, it is preferable to increase the activation period of the set enable signal Set_en until the set data is normally written.

9 is an operation timing diagram in the reset write operation mode according to the first embodiment of the present invention.

The data of the selected cell C is read in the period t11. That is, the sense amplifier S / A senses and amplifies the data of the selected cell C and outputs it to the output signal Saout. The flag register 60 latches the output signal Saout of the sense amplifier S / A and outputs it as the flag signal Flag. At this time, the write enable signal We maintains a deactivation state at a low level, and the reset enable control signal Reset_con maintains a deactivation state at a low level.

When the write cycle is started in the t12 period, the write enable signal We is activated to a high level. The reset data is loaded on the global input / output line GI / O. At this time, the write latch enable signal WLen is activated to a high level so that the reset data is latched through the data latch unit 90 and loaded on the latch global input / output line LGI / O.

Next, the comparator 70 compares the reset data loaded on the latch global input / output line LGI / O with the flag signal Flag.

Here, when the reset data loaded on the latch global I / O line LGI / O and the flag signal Flag are the same, the comparison signal Comp is inactivated to a low level and the reset enable signal Reset_en is inactivated to a low level.

On the other hand, when the reset data on the latch global I / O line LGI / O and the flag signal Flag are different, the comparison signal Comp is activated to a high level. In this case, in the first case in which the comparison signal Comp is activated during the period t12 and t13 (Case 1), the reset enable signal Reset_en is activated to the high level only during the period t2. Accordingly, the write voltage is applied to the selected unit cell C through the reset write driver 40 for the period t2.

Then, it is verified whether reset data is normally written to the selected unit cell C in the period t13. That is, the data of the selected unit cell C is read back through the sense amplifier S / A. The data Saout read in the selected unit cell C is latched through the flag register 60 and output as a flag signal Flag.

Next, the comparison unit 70 compares the flag signal Flag with the reset data loaded on the latch global input / output line LGI / O. At this time, the reset activation control signal Reset_con is in an inactive state.

Accordingly, when the flag signal Flag and the reset data loaded on the global input / output line GI / O are the same, the reset enable signal Reset_en is deactivated. That is, in the first case (Case 1), if the reset data is a pass condition, the write cycle ends.

On the other hand, when the flag signal Flag and the reset data loaded on the latch global I / O line LGI / O are different, the reset data is written by applying the second case (Case 2). That is, the comparison signal Comp is kept active for the period t12, t13, t14, and t15. Then, the reset enable signal Reset_en is activated to a high level in the period t12 and t14.

Accordingly, the write voltage is applied to the selected cell C through the reset write driver 40 for the period t12 and t14.

The reset data is normally written to the selected unit cell C in the t15 period. As a result of verification, in the second case (Case 2), the write cycle is terminated when the reset data is a pass condition. On the other hand, if the reset data is a fail condition (Case 3) is applied.

In this manner, in the write operation mode, the activation period of the reset enable signal Reset_en is changed to write the reset data to the selected cell C, and the operation of verifying whether the reset data is normally written is repeated. Here, the write and verify operations preferably increase the activation period of the reset enable signal Reset_en until the reset data is normally written.

10 is an operation timing diagram in the reset write operation mode according to the second embodiment of the present invention.

The data of the selected cell C is read in the period t21. That is, the sense amplifier S / A senses and amplifies the data of the selected cell C and outputs it to the output signal Saout. The flag register 230 latches the output signal Saout of the sense amplifier S / A and outputs the flag signal Flag. At this time, the write enable signal We remains inactive at the low level, and the set activation control signal Set_con and the reset activation control signal Reset_con remain in the inactive state at the low level.

When the write cycle starts in the t22 period, the write enable signal We is activated to a high level. The reset data is loaded on the global input / output line GI / O. At this time, the write latch enable signal WLen is activated to a high level so that the reset data is latched through the data latch unit 260 to be loaded on the latch global input / output line LGI / O.

Next, the comparator 240 compares the reset data loaded on the latch global input / output line LGI / O with the flag signal Flag.

Here, when the reset data loaded on the latch global I / O line LGI / O and the flag signal Flag are the same, the comparison signal Comp is inactivated to a low level and the reset enable signal Reset_en is inactivated to a low level.

On the other hand, when the reset data on the latch global I / O line LGI / O and the flag signal Flag are different, the comparison signal Comp is activated to a high level. In this case, in the first case in which the comparison signal Comp is activated during the period t22 and t23 (Case 1), the set enable signal Set_en is activated to the high level only during the period t22. Then, the reset enable signal Reset_en is activated, and the set enable signal Set_en is activated, and becomes activated at a low level after a predetermined time.

Accordingly, the write voltage is applied to the selected unit cell C during the t22 period through the set write driver 200 and the reset write driver 210. Here, the write voltage is doubled in the voltage level in a section in which the set enable signal Set_en and the reset enable signal Reset_en are simultaneously activated.

Next, it is verified whether reset data is normally written to the selected unit cell C in the t23 period. That is, the data of the selected unit cell C is read back through the sense amplifier S / A. The data Saout read in the selected unit cell C is latched through the flag register 230 and output as a flag signal Flag.

Next, the comparison unit 240 compares the flag signal Flag with the reset data loaded on the latch global input / output line LGI / O. At this time, the reset activation control signal Reset_con is in an inactive state.

Accordingly, when the flag signal Flag and the reset data loaded on the global input / output line GI / O are the same, the reset enable signal Reset_en is deactivated. That is, in the first case (Case 1), if the reset data is a pass condition, the write cycle ends.

On the other hand, when the flag signal Flag and the reset data loaded on the latch global I / O line LGI / O are different, the reset data is written by applying the second case (Case 2). That is, the comparison signal Comp is kept active for the period t22, t23, t24, and t25.

Then, the set enable signal Set_en is activated at a high level only during the periods t22 and t24. The set enable signal Reset_en is activated, and the reset enable signal Reset_en is activated at a low level after a predetermined time.

Accordingly, the write voltage is applied to the selected unit cell C through the set write driver 200 and the reset write driver 210 during the t22 and t24 periods.

The reset data is normally written to the selected unit cell C in the t25 period. As a result of verification, in the second case (Case 2), the write cycle is terminated when the reset data is a pass condition. On the other hand, if the reset data is a fail condition (Case 3) is applied.

In this manner, in the write operation mode, the activation period of the reset enable signal Reset_en is changed to write the reset data to the selected cell C, and the operation of verifying whether the reset data is normally written is repeated. Here, the write and verify operations preferably increase the activation period of the set enable signal Set_en and the reset enable signal Reset_en until the reset data is normally written.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a circuit diagram of a phase change memory device according to the present invention.

5 is a circuit block diagram of a phase change memory device according to the present invention;

6 is a detailed circuit diagram of a sense amplifier S / A, a write driver W / D and a write verification controller WVC according to the first embodiment of the present invention.

7 is a detailed circuit diagram of a sense amplifier S / A, a write driver W / D, and a write verify controller WVC according to a second embodiment of the present invention.

8 is an operation timing diagram in a set write operation mode according to the first embodiment of the present invention;

9 is an operation timing diagram in a reset write operation mode according to the first embodiment of the present invention;

10 is an operation timing diagram in a reset write operation mode according to a second embodiment of the present invention;

Claims (20)

A cell array unit including a phase change resistance cell disposed in an area where a word line and a bit line cross each other; A sense amplifier for sensing and amplifying data of the phase change resistance cell; A write verification control unit controlled by an activation control signal and outputting a set enable signal or a reset enable signal by comparing data read through the sense amplifier with data to be written to the phase change resistance cell; A set write driver configured to supply a write voltage corresponding to set data to the cell array unit according to the set enable signal; And And a reset write driver configured to supply a write voltage corresponding to reset data to the cell array unit according to the reset enable signal. The method of claim 1, The write verify controller outputs the set enable signal and the reset enable signal in an inactive state when the data read through the sense amplifier and the data to be written to the phase change resistor cell are the same. Device. The method of claim 1, The write verification controller changes the activation period of the set enable signal and the reset enable signal when data read through the sense amplifier and data to be written to the phase change resistor cell are different. Device. The method of claim 3, wherein The write verification controller sequentially increases an activation interval of the set enable signal and the reset enable signal when data read through the sense amplifier and data to be written to the phase change resistance cell are different from each other. Change memory device. The method of claim 1, And a first switching device connected between the cell array unit and the set write driver to receive the set enable signal through a gate terminal. The method of claim 5, wherein And a second switching element connected between the cell array unit and the reset write driver to receive the reset enable signal through a gate terminal. The method of claim 1, The light verification control unit A flag register for latching and outputting data read through the sense amplifier; A comparison unit comparing the output of the flag register with data to be written to the phase change resistance cell; And An enable signal generator configured to logically combine the activation control signal, the output of the comparator, and the data to be written to the phase change resistance cell and output the set enable signal or the reset enable signal Phase change memory device comprising a. The method of claim 7, wherein The flag register is A transfer unit configured to transfer data read through the sense amplifier according to a latch enable signal; And A latch for receiving and outputting the output of the transfer unit Phase change memory device comprising a. The method of claim 8, And the transfer unit includes an MOS transistor connected between the sense amplifier and the latch to receive the latch enable signal through a gate terminal. The method of claim 7, wherein The comparison unit deactivates and outputs a comparison signal when the output of the flag register and the data to be written in the phase change resistance cell are the same, and outputs the comparison signal when the output of the flag register and the data to be written in the phase change resistance cell are different. And a first logical combination means for activating and outputting the phase change memory device. The method of claim 10, And said first logical combining means is an exclusive or gate. The method of claim 7, wherein The enable signal generator Second logic combining means for receiving a set activation control signal, an output of the comparator, data to be written to the phase change resistance cell, and a write enable signal to perform a logical combination to output the set enable signal; And Third logic combining means for receiving a reset activation control signal, an output of the comparator, data to be written to the phase change resistance cell, and the write enable signal to perform a logical combination to output the reset enable signal; Phase change memory device comprising a. The method of claim 12, The second logical combining means A first NAND gate applied to NAND by receiving the set activation control signal, an output of the comparator, data to be written to the phase change resistance cell, and the write enable signal; And A first inverter that receives the output of the first NAND gate and inverts the output; Phase change memory device comprising a. The method of claim 12, The third logical combining means A second NAND gate receiving the reset activation control signal, an output of the comparator, data to be written to the phase change resistance cell, and a NAND operation by outputting the write enable signal; And A second inverter that receives the output of the second NAND gate and inverts the output; Phase change memory device comprising a. The method of claim 7, wherein The enable signal generator Fourth logic combining means for receiving a set activation control signal, an output of the comparator, and a write enable signal to perform a logical combination to output the set enable signal; And Fifth logic combining means for receiving a reset activation control signal, an output of the comparator, data to be written to the phase change resistance cell, and the write enable signal to perform a logical combination to output the reset enable signal; Phase change memory device comprising a The method of claim 15, The fourth logical combining means A third NAND gate receiving the set activation control signal, the output of the comparator, and the write enable signal by performing a NAND operation; And A third inverter that receives the output of the third NAND gate and inverts the output; Phase change memory device comprising a. The method of claim 15, The fifth logical combining means A fourth NAND gate receiving the reset activation control signal, the output of the comparator, the data to be written to the phase change resistance cell, and the NAND operation of the write enable signal; And A fourth inverter that receives the output of the fourth NAND gate and inverts the output; Phase change memory device comprising a. The method of claim 7, wherein The write verification control unit may further include a sense amplifier switching unit configured to transfer an output of the sense amplifier to a global input / output line according to a read switching signal. The method of claim 7, wherein The light verification control unit A transfer unit configured to transfer data carried on the global input / output line according to the write latch enable signal; And A latch for latching and outputting the output of the transfer unit. The phase change memory device further comprises. The method of claim 1, The phase change resistance cell A phase change resistance element configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to the magnitude of the current; And Diode element connected between the phase change resistance element and the word line Phase change memory device comprising a.

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