KR100895389B1 - Phase change memory device - Google Patents

Abstract

The present invention relates to a phase change memory device, and discloses a technique for generating reference and bit line precharge voltages reflecting characteristics of a main cell using a reference cell array that forms the same condition as a cell array. The present invention is formed in a region where a reference global bit line shared by a plurality of reference bit lines, a global bit line shared by a plurality of bit lines, and a plurality of reference bit lines and a word line cross each other to obtain a reference current. A main cell array including an output reference cell array, a phase change resistance cell disposed at an intersection of a plurality of bit lines and a word line, and a cell data current and a reference current of the main cell array connected to the plurality of bit lines And a write driver to supply a driving voltage corresponding to the write data to the plurality of bit lines.

Description

Phase change memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device, and is a technique for generating reference and bit line precharge voltages reflecting characteristics of a main cell using a reference cell array that forms the same condition as a cell array.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a chalcogenide composed mainly of chalcogen elements (S, Se, Te), specifically, a germanium antimony tellurium alloy material composed of Ge-Sb-Te ( Ge2Sb2Te5) is used.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

However, when the phase change memory device using the phase change resistance device does not effectively control the reference voltage, the sensing efficiency of the sense amplifier decreases. As a result, the reference current becomes unstable, the accuracy is lowered, and the offset characteristic of the sense amplifier is lowered. Accordingly, there is a problem in that the data sensing margin and yield of the entire chip are reduced.

The present invention has the following object.

First, the purpose of the present invention is to improve the stability and accuracy of a reference current by using a reference cell array that forms the same condition as a cell array in a memory device using a phase change resistance element.

Secondly, in the memory device using the phase change resistance element, a stable bit line precharge voltage can be generated by using a reference cell array having the same conditions as the cell array in response to changes in the device such as process change. .

Third, the purpose of the present invention is to improve the sensing efficiency of the sense amplifier by using a reference cell array having the same timing delay element in a memory device using a phase change resistor.

Fourth, the purpose of the present invention is to improve the offset characteristics of the sense amplifier by improving the structure of the sense amplifier in the memory device using the phase change resistance element.

A phase change memory device of the present invention for achieving the above object is a reference global bit line shared by a plurality of reference bit lines; A global bit line shared by a plurality of bit lines; A reference cell array formed in an area where a plurality of reference bit lines and word lines cross each other and output a reference current; A main cell array including a phase change resistance cell disposed in an area where a plurality of bit lines and word lines cross each other; A sense amplifier connected to a plurality of bit lines and configured to receive a cell data current and a reference current of a main cell array; And a write driver supplying a driving voltage corresponding to write data to the plurality of bit lines.

The present invention provides the following effects.

First, in a memory device using a phase change resistance device, a reference cell array that forms the same condition as a cell array may be used to improve stability and accuracy of a reference current.

Second, in a memory device using a phase change resistance device, a stable bit line precharge voltage may be generated in response to a change in a device such as a process change by using a reference cell array having the same conditions as a cell array.

Third, in the memory device using the phase change resistance device, the sensing efficiency of the sense amplifier may be improved by using a reference cell array having the same timing delay element.

Fourthly, in the memory device using the phase change resistance element, the structure of the sense amplifier is improved to provide an effect of improving the offset characteristic of the sense amplifier.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a circuit diagram of a phase change memory device according to the present invention.

The present invention provides a cell array CA, a bit line precharge unit 100, a global column switching unit 200, a read voltage control unit 300, a read voltage generator 400, a reference voltage generator 500 ), A reference resistor Rref, a sense amplifier S / A, and a write driver W / D.

Here, the cell array CA includes one reference global bit line REF_GBL and a plurality of global bit lines GBL <0> to GBL <n>.

The bit line precharge unit 100 includes a plurality of pull-up switching elements. Here, the plurality of pull-up switching elements are preferably made of NMOS transistors N1 to N3. The NMOS transistor N1 is connected between the supply voltage VDD applying stage and the reference global bitline REF_GBL and controlled by the bitline precharge control signal BLPRE_CON. The NMOS transistors N2 and N3 are connected between the power supply voltage VDD terminal and the global bit lines GBL <0> and GBL <n>, respectively, and are controlled by the bit line precharge control signal BLPRE_CON.

The global column switching unit 200 includes a plurality of PMOS transistors P1 and P2. Here, the plurality of PMOS transistors P1 and P2 are respectively connected between the plurality of global bit lines GBL <0>, GBL <n> and the node NBL, and the global column selection signals GY1 to GYn are applied through the gate terminal. The data of the global bit line GBL is transferred to the sense amplifier S / A and the write driver W / D through the global column switching unit 200.

The read voltage controller 300 includes PMOS transistors P3 and P4. Here, the PMOS transistor P3 is connected between the reference global bit line REF_GBL and the bit line read voltage VBLREAD applying terminal, and the read control signal BLREAD_CON is applied through the gate terminal. The PMOS transistor P4 is connected between the global column switching unit 200 and the bit line read voltage VBLREAD applying terminal, and the read control signal BLREAD_CON is applied through the gate terminal. The read voltage generator 400 generates the bit line read voltage VBLREAD according to the clamp voltage VCLMP.

The reference resistor Rref is connected between the reference global bitline REF_GBL and the node refblin to flow the reference current Iref. Here, the reference resistor Rref is for adjusting the offset reference value.

Accordingly, the value of the reference resistor Rref is defined as the average value of the set resistance and the reset resistor of the main cell C, and is obtained by subtracting the set resistance from the average resistance value.

Rref = {(Rreset + Rset) / 2} -Rset

That is, since the reference cell RC is in the set state, when the offset reference resistor is added to the set state resistor, the intermediate value of the reference resistor Rref is obtained. Therefore, the current of the reference bit line RSBL becomes an intermediate value between the set current of the main cell C and the reset current.

The reference voltage generator 500 is connected to the reference resistor Rref through the node refblin. The reference voltage generator 500 outputs the clamp voltage VCLMP to the node Nref according to the clamp voltage VCLMP. The clamp voltage generator 600 supplies the clamp voltage VCLMP to the read voltage generator 400, the reference voltage generator 500, and the write driver W / D.

The sense amplifier S / A distinguishes data "1" and data "0" according to the cell data applied through the node NBL and the reference voltage applied through the reference node Nref. The reference node Nref is shared by the plurality of sense amplifiers S / A, and supplies one reference voltage to the plurality of sense amplifiers S / A. The write driver W / D supplies a driving voltage corresponding to the write data to the node NBL when writing data to the cell.

5 is a detailed circuit diagram illustrating the read voltage generator 400 of FIG. 4.

The read voltage generator 400 includes NMOS transistors N4 and N5 and an amplifier A1. Here, the NMOS transistor N4 is connected between the power supply voltage terminal and the reference clamp voltage Vclmp_ref output terminal, and the clamp voltage VCLMP is applied through the gate terminal. Therefore, the reference clamp voltage Vclmp_ref is generated according to the clamp voltage VCLMP in order to set the voltage level of the global bit line GBL and its voltage value to be the same.

The NMOS transistor N5 is connected between the reference clamp voltage Vclmp_ref output terminal and the ground voltage terminal so that the gate terminal is commonly connected to the source terminal.

The amplifier A1 buffers the reference clamp voltage Vclmp_ref according to the read enable signal VBLREAD_EN to output the bit line read voltage VBLREAD. The amplifier A1 is supplied with the reference clamp voltage Vclmp_ref through the positive (+) terminal and fed back with the bit line read voltage VBLREAD through the negative (-) terminal.

The bit line read voltage VBLREAD is set to a voltage value smaller than the clamp voltage VCLMP by the threshold voltage Vt of the NMOS transistor N4. The activation period of the amplifier A1 is determined according to the read enable signal VBLREAD_EN. Since one reference node Nref is connected to the plurality of sense amplifiers S / A, the driving capability of the bit line read voltage VBLREAD is increased through the amplifier A1.

FIG. 6 is a circuit diagram of a core part related to a reference in the phase change memory device of FIG. 4.

The cell array CA includes a reference cell array RCA. The reference cell array RCA includes a plurality of reference bit lines RSBL1 to RSBL4 and a reference global bit line REF_GBL. Here, the reference cell array RCA has the same configuration as the main cell array MCA.

That is, in order to reflect the characteristics of the main bit line SBL in the reference bit line RSBL, the bit line and sub cell arrays having the same condition are configured. In addition, the order of switches activated in the reference cell array RCA is the same as that of the main cell array MCA.

In the reference cell array RCA, a plurality of reference bit lines RSBL1 to RSBL4 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The reference cell RC is formed in a region where the plurality of reference bit lines RSBL1 to RSBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

The local column switching means includes a plurality of PMOS transistors P5 to P8. Here, the plurality of PMOS transistors P5 to P8 are connected between the plurality of reference bit lines RSBL1 to RSBL4 and the plurality of reference global bit lines REF_GBL, respectively, and the column selection signals LY1_n to LY4_n are applied through respective gate terminals.

The bit line precharge unit 100 includes a pull-up switching device. Here, it is preferable that the pull-up switching element is made of NMOS transistor N1. The NMOS transistor N1 is connected between the power supply voltage VDD terminal and the reference global bitline REF_GBL, and the bitline precharge control signal BLPRE_CON is applied through the gate terminal.

The read voltage controller 300 includes a PMOS transistor P3. Here, the PMOS transistor P3 is connected between the reference global bit line REF_GBL and the bit line read voltage VBLREAD applying terminal, and the read control signal BLREAD_CON is applied through the gate terminal. The reference resistor Rref for flowing the reference current Iref is connected between the reference global bit line REF_GBL and the reference voltage generator 500.

FIG. 7 is a circuit diagram of a core part associated with a main cell in the phase change memory device of FIG. 4.

The cell array CA includes a main cell array MCA. The main cell array MCA includes a plurality of bit lines SBL1 to SBL4 and a plurality of global bit lines GBL <0> to GBL <n>.

In the main cell array MCA, a plurality of bit lines SBL1 to SBL4 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The unit cell C is formed in an area where the plurality of bit lines SBL1 to SBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

The local column switching means includes a plurality of PMOS transistors P9 to P12. Here, the plurality of PMOS transistors P9 to P12 are connected between the plurality of bit lines SBL1 to SBL4 and the global bit line GBL, respectively, and the column selection signals LY1_n to LY4_n are applied through respective gate terminals.

The bit line precharge unit 100 includes a pull-up switching device. Here, it is preferable that the pull-up switching element consists of NMOS transistors N2 and N3. The NMOS transistors N2 and N3 are connected between the power supply voltage VDD applying stage and the global bitline GBL, respectively, and the bitline precharge control signal BLPRE_CON is applied through the gate terminal.

The global column switching unit 200 includes a plurality of PMOS transistors P1 and P2. Here, the plurality of PMOS transistors P1 and P2 are connected between the plurality of global bit lines GBL <0>, GBL <n> and the node NBL, respectively, and the global column selection signals GY1 to GYn are applied through the gate terminal.

The read voltage controller 300 includes a PMOS transistor P4. Here, the PMOS transistor P4 is connected between the node NBL and the bit line read voltage VBLREAD applying terminal, and the read control signal BLREAD_CON is applied through the gate terminal. The node NBL is connected to the sense amplifier S / A and the write driver W / D.

FIG. 8 is a detailed circuit diagram of the cell array CA of FIG. 4.

The cell array CA includes a reference cell array RCA and a main cell array MCA.

In the reference cell array RCA, a plurality of reference bit lines RSBL1 to RSBL4 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The reference cell RC is formed in a region where the plurality of reference bit lines RSBL1 to RSBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

Here, the reference cell RC includes a phase change resistance device PCR and a diode D. The diode D is preferably made of a PN diode element. One electrode of the phase change resistance element PCR is connected to the reference bit line RSBL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. According to the set current Iset and the reset current Ireset flowing through the reference bit line RSBL, the phase of the phase change resistance element PCR is changed to write data.

In the main cell array MCA, a plurality of bit lines SBL1 and SBL2 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The unit cell C is formed in an area where the plurality of bit lines SBL1 to SBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

Here, the unit cell C includes a phase change resistance device PCR and a diode D. The diode D is preferably made of a PN diode element. One electrode of the phase change resistance element PCR is connected to the bit line SBL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. The phase of the phase change resistance element PCR is changed according to the set current Iset and the reset current Ireset flowing in the bit line SBL, so that data can be written.

FIG. 9 is another embodiment of the cell array CA of FIG. 4.

The cell array CA includes a reference cell array RCA and a main cell array MCA.

In the reference cell array RCA, a plurality of reference bit lines RSBL1 to RSBL4 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The reference cell RC is formed in a region where the plurality of reference bit lines RSBL1 to RSBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

Here, the reference cell RC includes a diode D. The diode D is preferably made of a PN diode element. The P-type region of the diode D is connected to the reference bit line RSBL, and the N-type region is connected to the word line WL.

In the main cell array MCA, a plurality of bit lines SBL1 and SBL2 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The unit cell C is formed in an area where the plurality of bit lines SBL1 to SBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

Here, the unit cell C includes a phase change resistance device PCR and a diode D. The diode D is preferably made of a PN diode element. One electrode of the phase change resistance element PCR is connected to the bit line SBL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. The phase of the phase change resistance element PCR is changed according to the set current Iset and the reset current Ireset flowing in the bit line SBL, so that data can be written.

9 is different from FIG. 8 in that the reference cell RC of the reference cell array RCA does not include the phase change resistance element PCR.

Accordingly, the low voltage level is applied to the selected word line WL in the read operation mode, and the bit line read voltage VBLREAD is applied to the reference global bit line REF_GBL and the global bit line GBL. Therefore, using the set current Iset (or reset current Ireset) flowing in the word line WL through the bit line SBL (or reference bit line RSBL), the phase change resistance element PCR and the diode D, and the reference current Iref flowing in the reference cell RC, The amplification operation is performed.

10 is an operation waveform diagram illustrating a phase change memory device according to the present invention.

First, in the precharge period t0, the column select signal LY1_n becomes a high level so that the PMOS transistors P5 and P9 remain turned off. Accordingly, the connection between the reference bit line RSBL and the reference global bit line REF_GBL is cut off. Then, the connection between the bit line SBL and the global bit line GBL is cut off.

Then, the global column select signal GY1 is at a high level so that the PMOS transistor P1 remains turned off. Accordingly, the connection between the global bit line GBL and the node NBL is cut off.

In addition, the word line WL1_n and the bit line precharge control signal BLPRE_CON maintain the high level. Accordingly, all of the NMOS transistors N1 to N3 are turned on to precharge the reference global bit line REF_GBL and the global bit line GBL to the power supply voltage VDD level during the precharge period.

Then, the read control signal BLREAD_CON is at a high level so that the PMOS transistors P3 and P4 remain turned off. Accordingly, the connection between the node NBL and the read voltage VBLREAD applying end is cut off. Therefore, the bit line read voltage VBLREAD is not applied to the reference global bit line REF_GBL and the global bit line GBL.

Subsequently, in the active period t1, the column select signal LY1_n transitions to a low level so that the PMOS transistors P5 and P9 are turned on. Accordingly, the reference bit line RSBL and the reference global bit line REF_GBL are connected to each other. The bit line SBL and the global bit line GBL are connected to each other.

The global column select signal GY1 transitions to a low level, and the PMOS transistor P1 is turned on. Accordingly, the global bit line GBL and the node NBL are connected to each other.

In addition, the word line WL1_n and the bit line precharge control signal BLPRE_CON transition to a low level. Accordingly, the NMOS transistors N1 to N3 are all turned off so that the power supply voltage VDD level is not applied to the reference global bit line REF_GBL and the global bit line GBL.

Then, the read control signal BLREAD_CON transitions to a low level and the PMOS transistors P3 and P4 are turned on. Accordingly, the node NBL and the read voltage VBLREAD applying terminal are connected to each other. Accordingly, the bit line read voltage VBLREAD is applied to the reference global bit line REF_GBL and the global bit line GBL so that the voltages of the precharged reference global bit line REF_GBL and the global bit line GBL are reset to the bit line read voltage VBLREAD.

Subsequently, in the active period t2, the column select signal LY1_n, the global column select signal GY1, the word line WL1_n and the bit line precharge control signal BLPRE_CON maintain a low level.

The read control signal BLREAD_CON transitions to the high level again, and the PMOS transistors P3 and P4 are turned off. Accordingly, the connection between the node NBL and the read voltage VBLREAD applying end is cut off. Therefore, the bit line read voltage VBLREAD is not applied to the reference global bit line REF_GBL and the global bit line GBL.

Next, when a sufficient sensing voltage is generated in the t2 section, the sense amplifier enable signal SNE transitions to the high level in the active section t3. Accordingly, the sense amplifier S / A senses and amplifies data applied from the global bit line GBL according to the reference voltage.

Thereafter, in the precharge period t4, the column select signal LY1_n, the global column select signal GY1, the word line WL1_n and the bit line precharge control signal BLPRE_CON transition to a high level. The read control signal BLREAD_CON maintains the high level. In addition, the sense amplifier enable signal SNE transitions to a low level to stop the sensing operation.

FIG. 11 is another embodiment of a core portion associated with a main cell in the phase change memory device of FIG. 4.

The cell array CA includes a main cell array MCA. The main cell array MCA includes a plurality of bit lines SBL1 to SBL4 and a plurality of global bit lines GBL <0> to GBL <n>.

In the main cell array MCA, a plurality of bit lines SBL1 to SBL4 are arranged in a column direction, and a plurality of word lines WL1_n to WLn_n are arranged in a row direction. The unit cell C is formed in an area where the plurality of bit lines SBL1 to SBL4 and the plurality of word lines WL1_n to WLn_n cross each other.

The local column switching means includes a plurality of PMOS transistors P13 to P16. Here, the plurality of PMOS transistors P13 to P16 are connected between the plurality of bit lines SBL1 to SBL4 and the global bit line GBL, respectively, and the column selection signals LY1_n to LY4_n are applied through respective gate terminals.

The bit line precharge unit 700 includes a pull-up switching device and a switching device. Here, it is preferable that the pull-up switching element consists of PMOS transistors P17 and P18. The switching element is preferably made of NMOS transistors N6 and N7.

The PMOS transistors P17 and P18 are connected between the power supply voltage VDD terminal and the NMOS transistors N6 and N7, respectively, and the bit line precharge control signal BLPRE_CON is applied through the gate terminal. The NMOS transistors N6 and N7 are connected between the PMOS transistors P17 and P18 and the global bit line GBL, respectively, and the clamp voltage VCLMP is applied through the gate terminal.

The global column switching unit 710 includes a plurality of PMOS transistors P19 and P20. Here, the plurality of PMOS transistors P19 and P20 are connected between the plurality of global bit lines GBL <0>, GBL <n> and the node NBL, respectively, and the global column selection signals GY1 to GYn are applied through the gate terminal.

The read voltage controller 720 includes a PMOS transistor P21. Here, the PMOS transistor P21 is connected between the node NBL and the bit line read voltage VBLREAD applying terminal, and the read control signal BLREAD_CON is applied through the gate terminal. The node NBL is connected to the sense amplifier S / A and the write driver W / D.

12 is an operation waveform diagram illustrating the phase change memory device of FIG. 11.

First, in the precharge period t0, the column select signal LY1_n becomes high and the PMOS transistor P13 maintains the turn-off state. Accordingly, the connection between the reference bit line RSBL and the reference global bit line REF_GBL is cut off. Then, the connection between the bit line SBL and the global bit line GBL is cut off.

Then, the global column select signal GY1 is at a high level so that the PMOS transistor P19 remains turned off. Accordingly, the connection between the global bit line GBL and the node NBL is cut off.

In addition, the word line WL1_n maintains a high level, and the bit line precharge control signal BLPRE_CON maintains a low level. Accordingly, the PMOS transistors P17 and P18 are all turned on, the NMOS transistors N6 and N7 are turned on according to the clamp voltage VCLMP, and the global bit line GBL is precharged to the power supply voltage VDD level.

Then, the read control signal BLREAD_CON is at a high level so that the PMOS transistor P21 remains turned off. As a result, the connection between the node NBL and the read voltage VBLREAD applying terminal is cut off. Therefore, the bit line read voltage VBLREAD is not applied to the global bit line GBL.

Thereafter, in the active period t1, the column select signal LY1_n transitions to a low level, and the PMOS transistor P13 is turned on. Accordingly, the bit line SBL and the global bit line GBL are connected to each other.

Then, the global column select signal GY1 transitions to the low level, and the PMOS transistor P19 is turned on. Accordingly, the global bit line GBL and the node NBL are connected to each other.

In addition, the word line WL1_n transitions to a low level, and the bit line precharge control signal BLPRE_CON transitions to a high level. Accordingly, the PMOS transistors P17 and P18 are all turned off, and the NMOS transistors N6 and N7 are turned off according to the clamp voltage VCLMP so that the power supply voltage VDD level is not supplied to the global bit line GBL.

Then, the read control signal BLREAD_CON transitions to the low level and the PMOS transistor P21 is turned on. Accordingly, the node NBL and the read voltage VBLREAD applying terminal are connected to each other. Therefore, the bit line read voltage VBLREAD is applied to the global bit line GBL.

Next, in the active period t2, the column select signal LY1_n, the global column select signal GY1, and the word line WL1_n maintain a low level. The bit line precharge control signal BLPRE_CON maintains the high level.

Then, the read control signal BLREAD_CON transitions to the high level again and the PMOS transistor P21 is turned off. Accordingly, the connection between the node NBL and the read voltage VBLREAD applying end is cut off. Therefore, the bit line read voltage VBLREAD is not applied to the global bit line GBL.

Next, in the active period t3, the sense amplifier enable signal SNE transitions to a high level. Accordingly, the sense amplifier S / A senses and amplifies data applied from the global bit line GBL according to the reference voltage.

Thereafter, in the precharge period t4, the column select signal LY1_n, the global column select signal GY1, and the word line WL1_n transition to a high level. Then, the bit line precharge control signal BLPRE_CON transitions to the low level. The read control signal BLREAD_CON maintains the high level. In addition, the sense amplifier enable signal SNE transitions to a low level to stop the sensing operation.

13 is a diagram illustrating a relationship between a set resistor, a reset resistor, and a reference resistor of the phase change memory device according to the present invention.

The set resistor Rset flowing through the bit line SBL has a smaller resistance value than the reference resistor Rref, and the reset resistor Rreset flowing through the bit line BL has a larger resistance value than the reference resistor Rref.

14 is a diagram illustrating a read current relationship of a phase change memory device according to the present invention.

The set current Iset flowing through the bit line SBL has a higher current value than the reference current Iref, and the reset current Ireset flowing through the bit line BL has a lower current value than the reference current Iref.

FIG. 15 is a detailed circuit diagram illustrating the sense amplifier S / A of FIG. 4.

The sense amplifier S / A includes an equalizing unit 800, a latch unit 810, an activation controller 820, an amplifier 830, and an amplification activation controller 840.

Here, the equalizing unit 800 includes PMOS transistors P22 and P23 and NMOS transistor N8. The PMOS transistor P22 is connected between the supply voltage VDD terminal and the node S1. The PMOS transistor P23 is connected between the supply voltage VDD terminal and node S2. NMOS transistor N8 is connected between nodes S1 and S2. The PMOS transistors P22 and P23 and the NMOS transistor N8 receive a precharge enable signal SPE through a common gate terminal.

The latch unit 810 includes PMOS transistors P24 and P25 and NMOS transistors N9 to N11. PMOS transistors P24 and P25 and NMOS transistors N10 and N11 are cross coupled.

Here, the PMOS transistor P24 and the NMOS transistor N10 are connected in series between the node S1 and the NMOS transistor N12 so that the common gate terminal is connected to the output terminal OUT. The PMOS transistor P25 and the NMOS transistor N11 are connected in series between the node S2 and the NMOS transistor N12 so that a common gate terminal is connected to the output terminal / OUT. The NMOS transistor N9 is connected between the gate terminals of the PMOS transistors P24 and P25 and controlled by the precharge enable signal SPE.

The activation control unit 820 includes an NMOS transistor N12. Here, the NMOS transistor N12 is connected between the output terminal OUT, / OUT and the ground voltage terminal, and the sense amplifier enable signal SNE2 is applied through the gate terminal.

The amplifier 830 includes NMOS transistors N13 and N14. The NMOS transistor N13 is connected between the node S1 and the NMOS transistor N15 to receive the sense amplifier input signal SAIN through the gate terminal. Here, the sense amplifier input signal SAIN is a signal applied from the global bit line GBL through the node NBL. The NMOS transistor N14 is connected between the node S2 and the NMOS transistor N15 so that the voltage of the reference node Nref is applied through the gate terminal.

The amplification activation control unit 840 includes an NMOS transistor N15. Here, the NMOS transistor N15 is connected between the amplifier 830 and the ground voltage terminal, and the sense amplifier enable signal SNE1 is applied through the gate terminal.

16 is another embodiment of the sense amplifier S / A of FIG. 4.

The sense amplifier S / A includes an equalizing unit 900, a latch unit 910, an activation controller 920, an amplifier 930, and an amplification activation controller 940.

Here, the equalizing unit 900 includes PMOS transistors P26 and P27 and NMOS transistor N16. The PMOS transistor P26 is connected between the supply voltage VDD terminal and the node S1. The PMOS transistor P27 is connected between the supply voltage VDD terminal and node S2. NMOS transistor N16 is connected between nodes S1 and S2. The precharge enable signal SPE is applied to the PMOS transistors P26 and P27 and the NMOS transistor N16 through a common gate terminal.

The latch unit 910 includes PMOS transistors P28 and P29 and NMOS transistors N17 to N21. The NMOS transistor N19 is connected between the gate terminals of the PMOS transistors P28 and P29 and controlled by the precharge enable signal SPE.

The NMOS transistor N17 is connected between the gate terminal of the PMOS transistor P28 and the ground voltage terminal, and a precharge enable signal SPE is applied through the gate terminal. The NMOS transistor N18 is connected between the gate terminal of the PMOS transistor P29 and the ground voltage terminal, and a precharge enable signal SPE is applied through the gate terminal.

During the precharge period, output stages OUT and / OUT are equalized to NMOS transistor N19. The output terminals OUT and / OUT are precharged to the ground voltage GND through the NMOS transistors N17 and N18. Accordingly, the amplification efficiency of the output terminals OUT and / OUT can be improved.

PMOS transistors P28 and P29 and NMOS transistors N20 and N21 are cross coupled. Here, the PMOS transistor P28 and the NMOS transistor N20 are connected in series between the node S1 and the NMOS transistor N22 so that the common gate terminal is connected to the output terminal OUT. The PMOS transistor P29 and the NMOS transistor N21 are connected in series between the node S2 and the NMOS transistor N22 so that a common gate terminal is connected to the output terminal / OUT.

The activation control unit 920 includes an NMOS transistor N22. Here, the NMOS transistor N22 is connected between the output terminal OUT, / OUT and the ground voltage terminal, and the sense amplifier enable signal SNE2 is applied through the gate terminal.

The amplifier 930 includes NMOS transistors N23 and N24. The NMOS transistor N23 is connected between the node S1 and the NMOS transistor N25 so that the sense amplifier input signal SAIN is applied through the gate terminal. The NMOS transistor N24 is connected between the node S2 and the NMOS transistor N25 so that the voltage of the reference node Nref is applied through the gate terminal.

The amplification activation control unit 940 includes an NMOS transistor N25. Here, the NMOS transistor N25 is connected between the amplifier 930 and the ground voltage terminal, and the sense amplifier enable signal SNE1 is applied through the gate terminal.

The operation of the sense amplifier S / A having such a configuration will be described with reference to the waveform diagram of FIG. 17 as follows.

First, in the t0 period, the word line WL and the sense amplifier enable signal SNE1 become high level, and the NMOS transistor N15 is turned on. As a result, the equalizing unit 800 is activated.

The precharge enable signal SPE and the sense amplifier input signal SAIN maintain the high voltage level. Accordingly, the NMOS transistors N8, N9, and N13 are turned on so that the node S2 maintains a low voltage level. Then, the PMOS transistors P22 and P23 are turned off.

At this time, the sense amplifier input signal SAIN and the reference node Nref are in a high level state, and the nodes S1 and S2 and the sense amplifier enable signal SNE2 maintain a low voltage level. Accordingly, the output terminals OUT and / OUT are both precharged and equalized to the low state.

Thereafter, when the read signal READ is enabled, the read cycle period t1 is entered. Here, the read cycle section is set to t1 section to t5 section. When entering the read period t2, the word line WL transitions to the low voltage level. When wordline WL is activated at a low level, sensing current flows through the cell.

Accordingly, the sensing voltage is applied to the amplifier 830 to apply the sense amplifier input signal SAIN. Then, a reference voltage is applied to the reference node Nref. Accordingly, the amplifier 830 compares and amplifies the sense amplifier input signal SAIN with a reference voltage REF applied to the reference node Nref.

Thereafter, in the period t3, the precharge enable signal SPE transitions to the low voltage level to stop the equalizing operation. Accordingly, the NMOS transistors N8 and N9 are turned off. Then, the PMOS transistors P22 and P23 which are sensing load current elements are turned on.

Therefore, the primary amplification current is supplied to the nodes S1, S2, and the voltage levels of the nodes S1, S2 increase. That is, the primary amplification voltage is generated at the nodes S1 and S2 by the current difference between the NMOS transistors N13 and N14. Accordingly, the reference voltage REF and the data "0" are distinguished through the output terminal OUT, and the data "1" is distinguished through the output terminal / OUT.

Next, in a period t4, the sense amplifier enable signal SNE2 transitions to a high level. Accordingly, the NMOS transistor N12 is turned on so that the latch unit 810 performs an amplification operation.

Subsequently, in the period t5, the sense amplifier enable signal SNE1 transitions to a low voltage level, and currents flowing through the NMOS transistors N13 and N14 are cut off. Accordingly, the nodes S1 and S2 are raised to the full CMOS level.

The sense amplifier enable signal SNE2 is maintained at a high level. Accordingly, the NMOS transistor N15 is turned off, and the NMOS transistors N10 and N11 and the PMOS transistors P24 and P25 which are the secondary amplifiers are operated. Therefore, the voltage levels of the node S2 and the output terminals OUT and / OUT are amplified to output data of a full CMOS level.

At this time, since the data voltage of the cell is smaller than the reference voltage REF, the output terminal OUT is output at a low voltage level. Since the data voltage of the cell is greater than the reference voltage REF, the output terminal / OUT is output at a high voltage level.

Subsequently, in the precharge period t6, the word line WL, the sense amplifier enable signal SNE1, and the precharge enable signal SPE transition to a high level, and the sense amplifier enable signal SNE2 transition to a low voltage level. Then, the sense amplifier input signal SAIN is not applied so that the node S2 and the output terminals OUT and / OUT maintain the low voltage level.

18 is another embodiment illustrating an operation process of the sense amplifier S / A.

First, in the t0 period, the word line WL and the sense amplifier enable signal SNE1 become high level, and the NMOS transistor N15 is turned on. As a result, the equalizing unit 800 is activated.

The precharge enable signal SPE and the sense amplifier input signal SAIN maintain the high voltage level. Accordingly, the NMOS transistors N8, N9, and N13 are turned on so that the node S2 maintains a low voltage level. Then, the PMOS transistors P22 and P23 are turned off.

At this time, the sense amplifier input signal SAIN and the reference node Nref are in a high level state, and the nodes S1 and S2 maintain the sense amplifier enable signal SNE2 at a low voltage level. Accordingly, the output terminals OUT and / OUT are both precharged and equalized to the low state.

Thereafter, when the read signal READ is enabled, the read cycle period t1 is entered. Here, the read cycle section is set to t1 section to t6 section. When entering the read period t2, the word line WL transitions to the low voltage level. When wordline WL is activated at a low level, sensing current flows through the cell.

Accordingly, the sensing voltage is applied to the amplifier 830 to apply the sense amplifier input signal SAIN. Then, a reference voltage is applied to the reference node Nref. Accordingly, the amplifier 830 compares and amplifies the sense amplifier input signal SAIN with a reference voltage REF applied to the reference node Nref.

Thereafter, in the period t3, the precharge enable signal SPE transitions to the low voltage level to stop the equalizing operation. Accordingly, the NMOS transistors N8 and N9 are turned off. Then, the PMOS transistors P22 and P23 which are sensing load current elements are turned on.

Therefore, the primary amplification current is supplied to the nodes S1, S2, and the voltage levels of the nodes S1, S2 increase. That is, the primary amplification voltage is generated at the nodes S1 and S2 by the current difference between the NMOS transistors N13 and N14. Accordingly, the reference voltage REF and the data "0" are distinguished through the output terminal OUT, and the data "1" is distinguished through the output terminal / OUT.

Next, in a period t4, the sense amplifier enable signal SNE2 transitions to a high level. Accordingly, the NMOS transistor N12 is turned on so that the latch unit 810 performs an amplification operation.

Subsequently, in the period t5, the sense amplifier enable signal SNE1 transitions to a low voltage level, and currents flowing through the NMOS transistors N13 and N14 are cut off. Accordingly, the nodes S1 and S2 are raised to the full CMOS level.

The sense amplifier enable signal SNE2 is maintained at a high level. Accordingly, the NMOS transistor N15 is turned off, and the NMOS transistors N10 and N11 and the PMOS transistors P24 and P25 which are the secondary amplifiers are operated. Therefore, the voltage levels of the node S2 and the output terminals OUT and / OUT are amplified to output data of a full CMOS level.

At this time, since the data voltage of the cell is smaller than the reference voltage REF, the output terminal OUT is output at a low voltage level. Since the data voltage of the cell is greater than the reference voltage REF, the output terminal / OUT is output at a high voltage level.

Thereafter, in the burst access mode period t6, the word line WL transitions to the high voltage level. Accordingly, when the word line WL is deactivated at the high voltage level, the sense amplifier input signal SAIN and the reference voltage REF are again in the precharge state at the high level.

However, the remaining control signals remain active during the read cycle period. Accordingly, the latch data is continuously maintained by the latch unit 810 of the sense amplifier S / A during the t6 period, thereby outputting the respective latch data in the burst mode.

Therefore, the signal of the word line WL, the sense amplifier input signal SAIN and the reference node Nref, which are first deactivated within the read cycle period, is prepared in advance for another address access of the next cycle. Accordingly, after the data of the sense amplifier S / A is latched, the output of the sense amplifier S / A and other word line accesses can be simultaneously processed in parallel.

In the t7 period, the sense amplifier enable signal SNE1 and the precharge enable signal SPE are transitioned to the high level, and the sense amplifier enable signal SNE2 is transitioned to the low voltage level. The node S2 and the output terminals OUT and / OUT maintain the low voltage level.

19 is a detailed circuit diagram illustrating the reference voltage generator 500 of FIG. 4.

The reference voltage generator 500 includes a load unit 510 for sensing a reference current, a bias controller 520, and a buffer unit 530.

The load unit 510 includes a load resistor Rload connected between the high voltage terminal VPPSA and the bias controller 520. Here, the voltage applied to the high voltage terminal VPPSA has a voltage level higher than that of the power supply voltage VDD, and is set to a pumping voltage VPP value suitable for sensing the sensing current of the bit line and changing it to the sensing voltage. For example, the voltage of the high voltage terminal VPPSA is preferably set to about 3V.

The bias control unit 520 includes an NMOS transistor N26. The NMOS transistor N26 is connected between the load resistor Rload and the node refblin to apply the clamp voltage VCLMP through the gate terminal.

The buffer unit 530 outputs a reference voltage to the reference node Nref including the amplifier A2. Here, amplifier A2 has a negative terminal connected to the reference node Nref. In the amplifier A2, a positive (+) terminal is commonly connected to the load resistor Rload and the NMOS transistor N26 to apply a reference current Iref.

In the reference voltage generator 500 having such a configuration, the load unit 510 sets a load resistance value for detecting the reference current Iref. That is, the reference current Iref is converted into the reference voltage value by the load value of the load resistor Rload.

The bias control unit 520 controls the gate voltage of the NMOS transistor N27 by the clamp voltage VCLMP. That is, the bias value of the reference global bit line REF_GBL is adjusted according to the clamp voltage VCLMP.

The buffer unit 530 outputs a reference voltage value to the reference node Nref. At this time, the buffer unit 530 amplifies the driving capability and outputs the same to the reference node Nref while maintaining the reference voltage value.

20 is another embodiment of the reference voltage generator 500 of FIG. 4.

The reference voltage generator 500 includes a load unit 540 for sensing a reference current, a bias controller 550, and a buffer unit 560.

Here, the load unit 540 includes a PMOS transistor P30 connected between the high voltage terminal VPPSA and the bias controller 550 to which the load voltage Vload is applied through the gate terminal. The bias control unit 550 includes an NMOS transistor N27. The NMOS transistor N27 is connected between the PMOS transistor P30 and the node refblin to apply the clamp voltage VCLMP through the gate terminal.

The buffer unit 560 outputs a reference voltage to the reference node Nref including the amplifier A3. Here, amplifier A3 has a negative terminal connected to the reference node Nref. In the amplifier A3, a positive (+) terminal is commonly connected to the load unit 540 and the NMOS transistor N27 to apply a reference current Iref.

In the reference voltage generator 500 having such a configuration, the load unit 540 includes a PMOS transistor P30 controlled by the load voltage Vload. That is, the reference current Iref is converted into the reference sensing voltage value by the load value of the PMOS transistor P30.

The bias controller 550 controls the gate voltage of the NMOS transistor N27 by the clamp voltage VCLMP. That is, the bias value of the reference global bit line REF_GBL is adjusted according to the clamp voltage VCLMP.

The buffer unit 560 outputs a reference voltage value to the reference node Nref. At this time, the buffer unit 560 amplifies the driving capability and outputs the same to the reference node Nref while maintaining the reference voltage value.

1A and 1B are diagrams for explaining a conventional phase change resistance element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a circuit diagram of a phase change memory device according to the present invention.

FIG. 5 is a detailed circuit diagram of the read voltage generator of FIG. 4. FIG.

6 is a circuit diagram of a core portion associated with a reference in the phase change memory device of FIG.

FIG. 7 is a circuit diagram of a core portion associated with a main cell in the phase change memory device of FIG. 4. FIG.

FIG. 8 is a detailed circuit diagram of the cell array of FIG. 4. FIG.

9 is another embodiment of the cell array of FIG.

10 is an operational waveform diagram of a phase change memory device according to the present invention;

11 is another embodiment of a core portion associated with a main cell in the phase change memory device according to the present invention.

FIG. 12 is an operational waveform diagram of the phase change memory device of FIG.

13 is a diagram showing the relationship between the set resistor, the reset resistor and the reference resistor of the phase change memory device according to the present invention;

14 is a view showing a read current relationship of a phase change memory device according to the present invention.

FIG. 15 is a detailed circuit diagram of the sense amplifier of FIG. 4. FIG.

16 is another embodiment of the sense amplifier of FIG.

17 is an operational waveform diagram relating to the sense amplifier of FIG. 15.

18 is another embodiment of an operating waveform diagram of the sense amplifier of FIG. 15;

FIG. 19 is a detailed circuit diagram illustrating a reference voltage generator of FIG. 4. FIG.

20 is another embodiment of the reference voltage generator of FIG. 4;

Claims (41)

delete A reference global bit line shared by the plurality of reference bit lines; A plurality of global bit lines, each shared by a plurality of bit lines; A reference cell array formed in an area where the plurality of reference bit lines and word lines cross each other and output a reference current; A main cell array including a phase change resistance cell disposed in an area where the plurality of bit lines and word lines cross each other; A sense amplifier connected to the plurality of global bit lines to apply a cell data current and the reference current of the main cell array; And And a write driver configured to supply driving voltages corresponding to write data to the plurality of global bit lines. And said sense amplifier is shared by a plurality of global bit lines. A reference global bit line shared by the plurality of reference bit lines; A plurality of global bit lines, each shared by a plurality of bit lines; A reference cell array formed in an area where the plurality of reference bit lines and word lines cross each other and output a reference current; A main cell array including a phase change resistance cell disposed in an area where the plurality of bit lines and word lines cross each other; A sense amplifier connected to the plurality of global bit lines to apply a cell data current and the reference current of the main cell array; A write driver supplying a driving voltage corresponding to write data to the plurality of global bit lines; First local column switching means connected between the plurality of reference bit lines and the reference global bit line and controlled by a column select signal; And And a second local column switching means connected between the plurality of bit lines and the global bit line, respectively, and controlled by the column select signal. 4. The phase change memory device of claim 3, wherein the first local column switching means and the second local column switching means comprise a PMOS transistor. delete delete delete delete delete delete A reference global bit line shared by the plurality of reference bit lines; A plurality of global bit lines, each shared by a plurality of bit lines; A reference cell array formed in an area where the plurality of reference bit lines and word lines cross each other and output a reference current; A main cell array including a phase change resistance cell disposed in an area where the plurality of bit lines and word lines cross each other; A sense amplifier connected to the plurality of global bit lines to apply a cell data current and the reference current of the main cell array; A write driver supplying a driving voltage corresponding to write data to the plurality of global bit lines; A bit line precharge unit configured to precharge the reference global bit line and the global bit line according to a bit line precharge control signal; A global column switching unit for selecting a corresponding global bit line according to the global column selection signal; A read voltage controller supplying a bit line read voltage to the reference global bit line and the global bit line according to a read control signal; A read voltage generator for generating the bit line read voltage according to a clamp voltage; And And a reference voltage generator configured to supply a reference voltage to the reference global bit line and the sense amplifier according to the clamp voltage. 12. The phase change memory device of claim 11, further comprising a reference resistor connected between the reference global bit line and the reference voltage generator. The phase change memory device as claimed in claim 12, wherein the reference resistor is defined as a value obtained by subtracting the set resistor from an average of the set resistance and the reset resistor of the phase change resistor cell. 12. The phase change memory device as claimed in claim 11, further comprising a clamp voltage generator configured to generate the clamp voltage and supply the clamp voltage to the read voltage generator, the reference voltage generator, and the write driver. 12. The method of claim 11, wherein the bit line precharge unit includes a plurality of pull-up switching elements connected between a power supply voltage terminal, the reference global bit line, and the global bit line, respectively, and controlled by the bit line precharge control signal. A phase change memory device characterized by the above-mentioned. 16. The phase change memory device of claim 15 wherein the plurality of pull-up switching elements comprise an NMOS transistor. 12. The method of claim 11, wherein the bit line precharge unit A plurality of pull-up switching elements controlled by a bit line precharge control signal to selectively supply a precharge voltage; And And a plurality of switching elements connected between the plurality of pull-up switching elements, the reference global bit line, and the global bit line, respectively, and controlled by the clamp voltage. 18. The phase change memory device of claim 17 wherein the plurality of pull-up switching elements comprise a PMOS transistor. 18. The phase change memory device of claim 17, wherein the plurality of switching elements comprise an NMOS transistor. The method of claim 11, wherein the global column switching unit And a switching transistor connected between the global bit line and the sense amplifier and controlled by the global column select signal. The method of claim 11, wherein the read voltage control unit A first PMOS transistor connected between the reference global bit line and an application terminal of the bit line read voltage and controlled according to the read control signal; And And a second PMOS transistor connected between the global column switching unit and an application terminal of the bit line read voltage and controlled according to the read control signal. The method of claim 11, wherein the read voltage generating unit A first NMOS transistor connected between a power supply voltage terminal and an output terminal of a reference clamp voltage to which the clamp voltage is applied through a gate terminal; A second NMOS transistor connected between an output terminal of the reference clamp voltage and a ground voltage terminal and having a gate terminal commonly connected to a source terminal; And And a first amplifier configured to generate the bit line read voltage by buffering the reference clamp voltage according to a read enable signal. 23. The phase change memory device of claim 22, wherein the bit line read voltage is set to a value smaller than the clamp voltage by a threshold voltage of the first NMOS transistor. The method of claim 11, wherein the reference voltage generator A load unit controlling a load of the reference voltage; A bias control unit controlling the reference voltage flowing in the reference global bit line according to the clamp voltage; And And a buffer configured to buffer the output of the load unit and the bias control unit. The method of claim 24, wherein the rod portion And a third PMOS transistor connected between a high voltage terminal and the bias controller to apply a load voltage through a gate terminal. The method of claim 24, wherein the rod portion And a load resistor coupled between the high voltage terminal and the bias control unit. 27. The phase change memory device as claimed in claim 25 or 26, wherein the voltage applied to the high voltage terminal has a voltage level higher than a power supply voltage and is set to a voltage level for sensing a sensing current of a bit line. The method of claim 24, wherein the bias control unit And a third NMOS transistor connected between the load unit and the reference global bit line to apply the clamp voltage through a gate terminal. The method of claim 24, wherein the buffer unit And a second amplifier connected to the load unit and the bias control unit to output a reference voltage. 30. The phase change memory device as claimed in claim 29, wherein the output of the load unit and the bias control unit is applied through a positive terminal, and the reference voltage is fed back through the negative terminal. A reference global bit line shared by the plurality of reference bit lines; A plurality of global bit lines, each shared by a plurality of bit lines; A reference cell array formed in an area where the plurality of reference bit lines and word lines cross each other and output a reference current; A main cell array including a phase change resistance cell disposed in an area where the plurality of bit lines and word lines cross each other; A sense amplifier connected to the plurality of global bit lines to apply a cell data current and the reference current of the main cell array; And A phase change memory device including a write driver configured to supply driving voltages corresponding to write data to the plurality of global bit lines. The sense amplifier An equalizer for precharging the output stage during the precharge period according to the precharge enable signal; A latch unit configured to latch data of both nodes according to the precharge enable signal; An activation controller for controlling activation of the latch unit according to a first sense amplifier enable signal; An amplifier for amplifying a voltage at the output terminal according to a sense amplifier input signal corresponding to the cell data current and the reference current; And And an amplification activation controller configured to control activation of the amplifier according to a second sense amplifier enable signal. 32. The apparatus of claim 31, wherein the equalizing unit A fourth NMOS transistor for precharging the both nodes upon activation of the precharge enable signal; And And a fourth and fifth PMOS transistors configured to supply a pull-up voltage to both nodes when the precharge enable signal is inactivated. 33. The apparatus of claim 32, wherein the equalizing unit And a primary amplifying current is supplied to both nodes according to the turn-on operation of the fourth and fifth PMOS transistors when the second sense amplifier enable signal is activated. The method of claim 31, wherein the latch unit A fifth and sixth NMOS transistor and a sixth and seventh PMOS transistor which are cross coupled to the output terminal; And And a seventh NMOS transistor connected between the gate terminals of the sixth and seventh PMOS transistors to receive the precharge enable signal through a gate terminal. The method of claim 34, wherein the latch unit An eighth NMOS transistor connected between the gate terminal of the sixth PMOS transistor and a ground voltage terminal to which the precharge enable signal is applied; And And a ninth NMOS transistor connected between the gate terminal and the ground voltage terminal of the seventh PMOS transistor, to which the precharge enable signal is applied. The method of claim 31, wherein the activation control unit And a tenth NMOS transistor connected between the latch unit and a ground voltage terminal to which the first sense amplifier enable signal is applied through a gate terminal. The method of claim 31, wherein the amplification unit An eleventh NMOS transistor connected between the first node of the equalizing unit and the amplification activation control unit to receive the sense amplifier input signal through a gate terminal; And And a twelfth NMOS transistor connected between a second node of the equalizing unit and the amplification activation control unit to which the reference current is applied through a gate terminal. The method of claim 31, wherein the amplification activation control unit And a thirteenth NMOS transistor connected between the amplifying unit and a ground voltage terminal to which the second sense amplifier enable signal is applied through a gate terminal. The method of claim 38, wherein the amplification activation control unit And when the second sense amplifier enable signal is inactivated, the voltage of the both nodes is increased to a CMOS level according to a turn-off operation of the thirteenth NMOS transistor. 32. The phase change memory device of claim 31, wherein the first sense amplifier enable signal is activated later than the second sense amplifier enable signal. 32. The phase change memory device of claim 31, wherein the sense amplifier outputs data latched by the latch unit in a burst mode during a burst access mode period.

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