KR100979374B1 - Phase change memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device, and discloses a technique for improving a sensing margin by removing coupling noise during operation of a sense amplifier. The present invention includes a cell array including a phase change resistance element and a read and write operation of data, and a sense amplifier for comparing and amplifying a cell sensing voltage applied from a cell array through a bit line and a reference voltage. The sense amplifier includes first noise removing means for controlling the reference voltage constantly by canceling coupling noise generated at the application terminal of the reference voltage during data read operation.

Description

Phase change memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device, and is a technique for improving a sensing margin by removing coupling noise during operation of a sense amplifier.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the electrical conduction state due to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a chalcogenide (chalcogenide) mainly composed of chalcogen elements (S, Se, Te). ).

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

FIG. 4 is a diagram for describing the influence of coupling noise related to a sense amplifier operation of a phase change memory device.

Each sense amplifier S / A is connected in a one-to-one correspondence with a bit line BL. The reference voltage terminal to which the reference voltage REF is applied is commonly connected to the plurality of sense amplifiers S / A. The sense amplifier S / A is applied with a cell sensing voltage through the bit line BL, and a reference voltage REF is applied through the reference voltage terminal.

In this case, the sense amplifier S / A receives the cell sensing voltage and the reference voltage described above through the gate terminal of the MOS transistor included therein. The output signal of the sense amplifier S / A is output through the drain terminal, which is an output node of the MOS transistor.

Accordingly, parasitic capacitance Cn exists between the gate input of the MOS transistor connected to the bit line BL and the drain of the MOS transistor connected to the reference voltage terminal REF. Therefore, coupling noise occurs when the voltage variation generated at the drain terminal of the MOS transistor during the operation of the sense amplifier S / A affects the gate input terminal.

Here, since each bit line BL is separately connected to the sense amplifier S / A one by one, the influence of the coupling noise may be insignificant. However, the reference voltage terminal REF is shared by the plurality of sense amplifiers S / A, so that one reference voltage is commonly applied to the n sense amplifiers S / A.

Accordingly, the influence of the coupling noise in the sense amplifier S / A is increased by n times. Therefore, as the coupling noise of the reference voltage terminal REF increases during the amplifying operation of the sense amplifier S / A, the sensing margin may be affected.

The present invention has the following object.

First, the purpose of the present invention is to improve the sensing margin by eliminating coupling noise generated at the reference voltage applying terminal during the operation of the sense amplifier.

Second, the purpose of the present invention is to improve the sensing margin by removing coupling noise generated in the bit line during the operation of the sense amplifier.

A phase change memory device of the present invention for achieving the above object includes a cell array including a phase change resistance element to read and write data; And a sense amplifier for comparing and amplifying the cell sensing voltage applied from the cell array and the reference voltage through the bit line, and the sense amplifier cancels coupling noise generated at the application terminal of the reference voltage during data read operation. First noise removing means for constantly controlling the reference voltage; And second noise removing means for constantly controlling the cell sensing voltage by canceling coupling noise generated in the bit line during the data read operation, wherein the first noise removing means includes a first MOS capacitor connected to an input terminal of a reference voltage. And the second noise removing means includes a second MOS capacitor connected to the bit line.
The present invention provides a cell array including a phase change resistance device to perform data read and write operations; And a sense amplifier for comparing and amplifying a cell sensing voltage applied from the cell array through a bit line and a reference voltage, wherein the sense amplifier cancels coupling noise generated in the bit line during a data read operation. Noise canceling means for controlling the constant and including a MOS capacitor connected to the bit line; An equalizer for precharging the output stage during the precharge period according to the precharge enable signal; A latch unit for latching data applied to both nodes of the sense amplifier according to an equalizing signal; An activation control unit controlling an activation of the latch unit according to the first sense amplifier enable signal; An amplifier for amplifying the voltage at the output terminal according to the cell sensing voltage and the reference voltage; An amplification activation control unit controlling an activation of the amplifying unit according to the second sense amplifier enable signal; And a pull-down unit which pulls down the output terminal according to the precharge enable signal.

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The present invention provides an effect of improving the coupling margin by removing the coupling noise during the operation of the sense amplifier.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a configuration diagram illustrating a cell array of a phase change memory device according to the present invention.

The present invention includes a unit cell C in an area where a plurality of bit lines BL1 to BL4 and a plurality of word lines WL1 to WL4 intersect. The unit cell C includes a phase change resistance element PCR and a diode D. Here, the diode D is made of a PN diode element.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL.

In the phase change memory device, a low voltage is applied to the selected word line WL in the read mode. The read voltage Vread is applied to the bit line BL to cause the set current or the reset current Ireset to flow toward the word line WL through the bit line BL, the phase change resistance element PCR and the diode D. do.

The sense amplifier S / A senses cell data applied through the bit line BL and compares the data "1" with the data "0" by comparing with the reference voltage REF. The reference current Iref flows through the reference voltage REF applying end. The write driver W / D supplies a driving voltage corresponding to the write data to the bit line BL when writing data to the cell.

FIG. 6 is a detailed circuit diagram of the sense amplifier S / A of FIG. 5.

The sense amplifier S / A includes an equalizing unit 100, a latch unit 110, an activation control unit 120, an amplification unit 130, an amplification activation control unit 140, a pull-down unit 150, and a noise removing unit CC1. It includes.

Here, the equalizing unit 100 includes PMOS transistors P1 and P2. The PMOS transistor P1 is connected between the supply voltage VDD terminal and the node S1. The PMOS transistor P2 is connected between the supply voltage VDD terminal and node S2. The PMOS transistors P1 and P2 are supplied with a precharge enable signal SPE through a common gate terminal.

The latch unit 110 includes PMOS transistors P3 and P4 and NMOS transistors N1 to N3. PMOS transistors P3 and P4 and NMOS transistors N1 and N2 are cross coupled.

Here, the PMOS transistor P3 and the NMOS transistor N1 are connected in series between the node S1 and the NMOS transistor N4 so that the common gate terminal is connected to the output terminal SAOUT. The PMOS transistor P4 and the NMOS transistor N2 are connected in series between the node S2 and the NMOS transistor N4 so that the common gate terminal is connected to the output terminal / SAOUT. The NMOS transistor N3 is connected between the gate terminals of the PMOS transistors P3 and P4 and controlled by the equalizing signal SEQ.

The activation control unit 120 includes an NMOS transistor N4. Here, the NMOS transistor N4 is connected between the latch unit 110 and the ground voltage terminal, and the sense amplifier enable signal SNE2 is applied through the gate terminal.

The amplifier 130 includes NMOS transistors N5 and N6. The NMOS transistor N5 is connected between the node S1 and the NMOS transistor N7 so that the gate terminal is connected to the bit line BL. The NMOS transistor N6 is connected between the node S2 and the NMOS transistor N7 so that the reference voltage REF is applied through the gate terminal.

The amplification activation control unit 140 includes an NMOS transistor N7. Here, the NMOS transistor N7 is connected between the amplifier 130 and the ground voltage terminal, and the sense amplifier enable signal SNE1 is applied through the gate terminal.

The pull-down unit 150 includes NMOS transistors N8 and N9. Here, the NMOS transistor N8 is connected between the output terminal / SAOUT and the ground voltage GND applying terminal, and the precharge enable signal SPE is applied through the gate terminal. In addition, the NMOS transistor N9 is connected between the output terminal SAOUT and the ground voltage GND applying terminal, and the precharge enable signal SPE is applied through the gate terminal.

The noise canceller CC1 includes a MOS capacitor connected between the reference voltage REF applying terminal and the gate terminal of the NMOS transistor N9. Here, the MOS capacitor is preferably made of an NMOS capacitor.

FIG. 7 is another embodiment of the sense amplifier S / A of FIG. 5.

The sense amplifier S / A includes an equalizing unit 200, a latch unit 210, an activation control unit 220, an amplifier 230, an amplification activation control unit 240, a pull-down unit 250, and a noise removing unit CC2. And CC3.

Here, the equalizing unit 200 includes PMOS transistors P5 and P6. The PMOS transistor P5 is connected between the supply voltage VDD terminal and node S1. The PMOS transistor P6 is connected between the supply voltage VDD terminal and node S2. The PMOS transistors P5 and P6 receive a precharge enable signal SPE through a common gate terminal.

The latch unit 210 includes PMOS transistors P7 and P8 and NMOS transistors N10 to N12. PMOS transistors P7 and P8 and NMOS transistors N10 and N11 are cross coupled.

Here, the PMOS transistor P7 and the NMOS transistor N10 are connected in series between the node S1 and the NMOS transistor N13 so that the common gate terminal is connected to the output terminal SAOUT. The PMOS transistor P8 and the NMOS transistor N11 are connected in series between the node S2 and the NMOS transistor N13 so that a common gate terminal is connected to the output terminal / SAOUT. The NMOS transistor N12 is connected between the gate terminals of the PMOS transistors P7 and P8 and controlled by the equalizing signal SEQ.

The activation control unit 220 includes an NMOS transistor N13. Here, the NMOS transistor N13 is connected between the latch unit 210 and the ground voltage terminal, and the sense amplifier enable signal SNE2 is applied through the gate terminal.

The amplifier 230 includes NMOS transistors N14 and N15. The NMOS transistor N14 is connected between the node S1 and the NMOS transistor N16 so that the gate terminal is connected to the bit line BL. The NMOS transistor N15 is connected between the node S2 and the NMOS transistor N16 to receive a reference voltage REF through the gate terminal.

The amplification activation control unit 240 includes an NMOS transistor N16. Here, the NMOS transistor N16 is connected between the amplifier 230 and the ground voltage terminal, and the sense amplifier enable signal SNE1 is applied through the gate terminal.

The pull-down unit 250 includes NMOS transistors N17 and N18. Here, the NMOS transistor N17 is connected between the output terminal / SAOUT and the ground voltage GND applying terminal, and the precharge enable signal SPE is applied through the gate terminal. In addition, the NMOS transistor N18 is connected between the output terminal SAOUT and the ground voltage GND applying terminal, and the precharge enable signal SPE is applied through the gate terminal.

The noise canceller CC2 includes a MOS capacitor connected between the bit line BL and the gate terminal of the NMOS transistor N17. The noise removing unit CC3 includes a MOS capacitor connected between the reference voltage REF applying terminal and the gate terminal of the NMOS transistor N18. Here, the MOS capacitor is preferably made of an NMOS capacitor.

An operation process of the sense amplifier S / A having such a configuration will be described below with reference to the waveform diagram of FIG. 8.

First, in the t0 period, the word line WL and the sense amplifier enable signal SNE1 are at a high level, and the NMOS transistor N7 is turned on. Then, the equalizing signal SEQ becomes high level and the NMOS transistor N3 is turned on.

The precharge enable signal SPE and the bit line BL maintain a high level state. As a result, the NMOS transistors N8 and N9 are turned on to precharge and equalize the node S2 and the output terminals SAOUT and / SAOUT to the ground voltage GND level. Then, the PMOS transistors P1 and P2 are maintained in a turn off state.

Thereafter, when the read signal READ is enabled, the read cycle period t1 is entered. Here, the read cycle section is set to t1 section to t6 section. When entering the read period t2, the word line WL transitions to the low voltage level. When wordline WL is activated at a low level, sensing current flows through the cell.

Accordingly, the sensing voltage is applied to the amplifier 130 and the cell sensing voltage is applied to the bit line BL. The reference voltage REF is applied to the reference node. Therefore, the amplifier 130 compares and amplifies the voltage applied to the bit line BL and the reference voltage REF.

Thereafter, in the period t3, the precharge enable signal SPE transitions to the low voltage level to stop the equalizing operation. Accordingly, the NMOS transistors N8 and N9 are turned off. The PMOS transistors P1 and P2 which are sensing load current devices are turned on to supply the power supply voltage VDD to the nodes S1 and S2.

Therefore, the primary amplification current is supplied to the nodes S1, S2, and the voltage levels of the nodes S1, S2 increase. That is, the primary amplification voltage is generated at the nodes S1 and S2 by the current difference between the NMOS transistors N13 and N14. Accordingly, the reference voltage REF and the data "0" are distinguished through the output terminal SAOUT, and the data "1" is distinguished through the output terminal / SAOUT.

At this time, when the precharge enable signal SPE is activated at the low voltage level, the drain voltage of the NMOS transistor N6 to which the reference voltage REF is input and the node S2 become the power supply voltage VDD level. Here, the voltage levels of the node S2 and the precharge enable signal SPE are opposite in phase.

One electrode of the noise removing unit CC1 is connected to the reference voltage REF applying end, and the other electrode is connected between the applying end of the precharge enable signal SPE. Accordingly, when the precharge enable signal SPE maintains a high level, the NMOS transistors N8 and N9 are turned on, and the output terminals SAOUT and / SAOUT are pulled down to the ground voltage GND level.

On the other hand, when the precharge enable signal SPE transitions to a low level, the node S2 becomes a power supply voltage level and is affected by noise. Accordingly, as shown in FIG. 9, the level of the reference voltage REF rises momentarily in the period t3 and t4 so that the reference voltage REF leaves the sensing operation region.

At this time, the present invention lowers the level of the reference voltage REF according to the noise removing unit CC1 so that a constant reference voltage REF is input as shown in FIG. 8. That is, the reference voltage REF temporarily raised in the period t3, t4 is canceled by the noise canceller CC1 to control the constant reference voltage REF.

Here, the capacitance of the noise removing unit CC1 is preferably set such that the node S2 has the same voltage value as that of the noise voltage induced at the reference voltage REF applying terminal and has the opposite phase.

Meanwhile, in the embodiment of FIG. 7, when the precharge enable signal SPE is activated at the low voltage level, the drain voltage of the NMOS transistor N14 and the node S1 to which the cell sensing voltage of the bit line BL is input become the power supply voltage VDD level. Here, the voltage levels of the node S1 and the precharge enable signal SPE are opposite in phase.

One electrode of the noise removing unit CC2 is connected to the bit line BL, and the other electrode is connected between the applying ends of the precharge enable signal SPE. Accordingly, when the precharge enable signal SPE maintains the high level, the NMOS transistors N17 and N18 are turned on, and the output terminals SAOUT and / SAOUT are pulled down to the ground voltage GND level.

On the other hand, when the precharge enable signal SPE transitions to a low level, the node S1 becomes a power supply voltage level and is affected by noise. As a result, the voltage level of the bit line BL rises instantaneously in the period t3, t4.

In this case, the present invention lowers the voltage level of the bit line BL according to the noise removing unit CC2 so that a constant bit line BL voltage is input as shown in FIG. 8. That is, the bit line BL voltage temporarily raised in the period t3, t4 is canceled by the noise canceller CC2 to control the stable bit line BL voltage.

Here, the capacitance of the noise removing unit CC2 is preferably set such that the node S1 has the same voltage value as that of the noise voltage induced on the bit line BL and has the opposite phase.

Next, in the period t4, the equalizing signal SEQ shifts to the low voltage level. Accordingly, the NMOS transistor N3 is turned off to disconnect the gates of the PMOS transistors P3 and P4.

Next, in the period t5, the sense amplifier enable signal SNE2 transitions to the high level. Accordingly, the NMOS transistor N4 is turned on so that the latch unit 110 performs an amplification operation.

Subsequently, in the period t6, the sense amplifier enable signal SNE1 transitions to a low voltage level to cut off current flowing through the NMOS transistors N5 and N6. Accordingly, the nodes S1 and S2 are raised to the full CMOS level.

The sense amplifier enable signal SNE2 is maintained at a high level. Accordingly, the NMOS transistor N7 is turned off, and the NMOS transistors N1, N2 and the PMOS transistors P3, P4, which are secondary amplifiers, operate. Therefore, the voltage levels of the node S2 and the output terminals SAOUT, / SAOUT are amplified to output data of a full CMOS level.

At this time, since the data voltage of the cell is smaller than the reference voltage REF, the output terminal SAOUT is output at a low voltage level. Since the data voltage of the cell is greater than the reference voltage REF, the output terminal / SAOUT is output at a high voltage level.

Thereafter, in the precharge period t7, the word line WL, the sense amplifier enable signal SNE1, the equalizing signal SEQ, and the precharge enable signal SPE transition to a high level, and the sense amplifier enable signal SNE2 transition to a low voltage level. The cell sensing voltage is not applied from the bit line BL, so that the node S2 and the output terminal SAOUT, / SAOUT transition to a low voltage level.

1A and 1B are diagrams for explaining a conventional phase change resistance element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a diagram for explaining the influence of coupling noise related to the operation of a sense amplifier in a conventional phase change memory device.

5 is a block diagram of a cell array of a phase change memory device according to the present invention;

FIG. 6 is a detailed circuit diagram of the sense amplifier of FIG. 5. FIG.

7 is another embodiment of the sense amplifier of FIG.

8 and 9 are operation timing diagrams for describing an operation process of the sense amplifiers of FIGS. 6 and 7.

Claims (16)

A cell array including a phase change resistance element and configured to read and write data; And A sense amplifier for comparing and amplifying a cell sensing voltage applied from the cell array through a bit line and a reference voltage, The sense amplifier First noise removing means for controlling the reference voltage constantly by canceling coupling noise generated at the application terminal of the reference voltage during a read operation of the data; And Second noise canceling means for constantly controlling the cell sensing voltage by canceling coupling noise generated in the bit line during the read operation of the data; And the first noise removing means comprises a first MOS capacitor connected to an input terminal of the reference voltage, and the second noise removing means comprises a second MOS capacitor connected to the bit line. delete The method of claim 1, wherein the second MOS capacitor And a phase change between the bit line and an applying end of the precharge enable signal. The method of claim 1, wherein the sense amplifier An equalizer for precharging the output stage during the precharge period according to the precharge enable signal; A latch unit for latching data applied to both nodes of the sense amplifier according to an equalizing signal; An activation controller for controlling activation of the latch unit according to a first sense amplifier enable signal; An amplifier for amplifying the voltage at the output terminal according to the cell sensing voltage and the reference voltage; An amplification activation control unit controlling an activation of the amplification unit according to a second sense amplifier enable signal; And And a pull-down unit configured to pull down the output terminal according to the precharge enable signal. The phase change memory device as claimed in claim 4, wherein the first MOS capacitor is connected between an input terminal of the reference voltage and an application terminal of the precharge enable signal. The phase change memory device as claimed in claim 4, wherein the voltage level of the precharge enable signal and the voltage level of both nodes are opposite in phase. 5. The phase change memory device as claimed in claim 4, wherein the first noise canceling means cancels the level of the reference voltage when the precharge enable signal is activated to increase the voltage at both nodes. The phase change memory device of claim 4, wherein the first sense amplifier enable signal is activated later than the second sense amplifier enable signal. The phase change memory device of claim 4, wherein the equalizing signal is activated before the precharge enable signal. A cell array including a phase change resistance element and configured to read and write data; And A sense amplifier for comparing and amplifying a cell sensing voltage applied from the cell array through a bit line and a reference voltage, The sense amplifier Noise canceling means including a MOS capacitor connected to the bit line by constantly controlling the cell sensing voltage by canceling coupling noise generated in the bit line during the read operation of the data; An equalizer for precharging the output stage during the precharge period according to the precharge enable signal; A latch unit for latching data applied to both nodes of the sense amplifier according to an equalizing signal; An activation controller for controlling activation of the latch unit according to a first sense amplifier enable signal; An amplifier for amplifying the voltage at the output terminal according to the cell sensing voltage and the reference voltage; An amplification activation control unit controlling an activation of the amplification unit according to a second sense amplifier enable signal; And And a pull-down unit configured to pull down the output terminal according to the precharge enable signal. delete The method of claim 10, wherein the MOS capacitor And a phase change between the bit line and the applying end of the precharge enable signal. The phase change memory device of claim 10, wherein a voltage level of the precharge enable signal and a voltage level of both nodes are opposite in phase. 11. The phase change memory device as claimed in claim 10, wherein the voltage level of the bit line is canceled by noise removing means when the precharge enable signal is activated to increase the voltage at both nodes. The phase change memory device of claim 10, wherein the first sense amplifier enable signal is activated later than the second sense amplifier enable signal. The phase change memory device of claim 10, wherein the equalizing signal is activated before the precharge enable signal.

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