JP2002367385A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the influence of switching noise is reduced and high speed access is made possible by improving an equalizing circuit. SOLUTION: A sense amplifier column 50 comprising a plurality of sense amplifiers shares a reference potential generating circuit 60. One side of the input terminal of a differential amplifier 51 of each sense amplifier main body is connected to a sense line SN, and the other side of the input terminal is connected in common to a reference sense line RSN. Current source loads 52, 61 are connected to the sense line SN and the reference sense line RSN. The sense line SN and the reference sense line RSN are connected respectively to a data line DL and a reference data line RDL through clamp circuits 53, 62. Equalizing circuits E01-E0n provided between each sense line SN and reference sense line RSN consists of two NMOS transistors QNL and QNS being connected in series. The switching noise is reduced by making the gate area of the transistor QNL of a sense line SN side greater than that of the transistor QNS of the reference sense line RSN side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which stores data depending on the presence or absence or magnitude of a current draw, and more particularly to a sense amplifier circuit for comparing data potentials of a data line and a reference data line to perform data sensing. Regarding improvement.

[0002]

2. Description of the Related Art As a semiconductor memory device, an EEPROM capable of storing data in a nonvolatile manner and electrically rewritable.
It has been known. Among EEPROMs, a type in which a plurality of memory cells are collectively erased is called a flash memory. In this type of semiconductor memory, a memory cell stores data depending on the presence or absence or magnitude of current draw, and therefore, a current read type sense amplifier circuit is used. As such a sense amplifier circuit, a method of reading data by comparing a potential of a data line from which data is read from a memory cell with a reference potential of a reference data line is often used.

FIG. 25 shows a configuration of such a conventional sense amplifier circuit. The sense amplifier circuit main body is constituted by a differential amplifier 101. One input terminal of the differential amplifier 101 is connected to the sense line SN, and the other input terminal is connected to the reference sense line RSN. The current source loads 102 and 2 are respectively applied to the sense line SN and the reference sense line RSN.
01 is connected. The sense line SN and the reference sense line RSN are respectively connected to an isolation circuit (clamp circuit) 105,
It is connected to the data line DL and the reference data line RDL via 202.

[0004] The data of the memory cell MC is read to the data line DL. Specifically, when the flash memory has a large capacity, the data of the memory cell MC is stored in the local bit line B
L, which is transferred to the main bit line MBL via the first column gate 103 and further transferred to the data line DL via the second column gate 104. Read through. The data “0”,
A current source 203 set to an intermediate current value of the cell current at “1” is connected, and a dummy data line capacitance CR is connected to balance the capacitance with the data line DL.

The current source load 20 on the reference sense line RSN side
1. The separation circuit 202 and the reference data line RDL
The reference potential generation circuit 200 generates a reference potential for detecting the potential of the cell data transferred to the sense line SN.

Since the load on the data line DL is large, it is necessary to detect data while suppressing the potential amplitude for high-speed sensing. For this purpose, a clamp circuit 105 for suppressing the potential amplitude of the data line DL is provided, and the data line DL is separated from the sense line SN by the clamp circuit 105 to reduce the capacitance of the sense line SN. Specifically,
Read data “0” of the data line DL and the sense line SN,
The relationship between the potential amplitudes at the time of “1” is as shown in FIG. 26, and the amplitude ΔVSN at the sense line SN is equal to the data line DL
Is about four times the potential amplitude ΔVDL.

By providing a clamp circuit, the sense line SN
Has a small capacity, but the effect on the sensing speed cannot be ignored. That is, as described with reference to FIG. 26, the amplitude of the sense line SN is about four times larger than that of the data line DL, and the capacitance of the sense line SN is about 1/10 of that of the data line DL. Nearly 30% of the charge to be charged as seen from the load 102 is allocated to the capacitance charging of the sense line SN. Therefore, the sense line SN and the reference sense line R
If the SN capacities are not aligned, the difference in charging speed between the two will result in a delay in data sensing.

The clamp circuit also has a purpose of suppressing a drain voltage at the time of reading applied to a bit line of a cell array via a data line. At the time of data reading, a positive read voltage is applied from the word line to the control gate of the memory cell, and a positive drain voltage is applied from the bit line to detect the presence or absence of a current. This potential relationship is the same as when data "0" is written. When the drain voltage is high, a slight writing phenomenon (soft write phenomenon) occurs. To prevent this, it is necessary to lower the drain voltage so that the memory cell does not operate as a pentode, and the clamp circuit functions.

Prior to data sensing, between sense line SN and reference sense line RSN, between sense line SN and reference sense line RSN, and thus between data line DL and reference data line RD.
There is provided an equalizing circuit 106 for short-circuiting between L and setting them to the same potential. Here, the equalizing circuit 106 is configured by an n-channel MISFET.

As shown in FIG. 27, the equalizing circuit 106 is selectively turned on by the equalizing signal EQL to short-circuit the sense line SN and the reference sense line RSN. At this time, the time width t1-t of the equalize signal EQL
It is necessary for the high-speed sensing operation that 0 is set to an optimum value required to short-circuit the sense line SN and the reference sense line RSN. After the equalizing signal EQL becomes “L” and cancels the equalizing operation, the potential difference between the sense line SN and the reference sense line RSN becomes equal to the data line DL and the reference data line RN.
The difference is enlarged according to the potential difference of DL, and the sense output SAout is obtained at a certain value of the difference voltage ΔV.

If the time width of the equalizing signal EQL is too short, reliable equalization cannot be performed, causing erroneous reading, or since the potential difference between the sense line SN and the reference sense line RSN needs to be reversed by data, the sense Operation is delayed. If the equalizing signal EQL is too long, the sensing operation will be delayed.

[0012]

In the above-mentioned conventional flash memory, what should be noted about the equalizing circuit 106 is switching noise. As shown in FIG. 28, at the time of canceling the equalization, that is, the equalization signal EQL
Is changed from "H" to "L", the capacitances C1 and C2 between the gate and the source and between the gate and the drain cause the reference sense line RSN and the sense line SN as shown in FIG.
, Large switching noises N1 and N2 are superimposed.

The sense line SN and the reference sense line RSN are 1:
1 and an equalizing circuit is provided for each pair, assuming that the capacitances of the sense line SN and the reference data line RDL are equal, the switching noises N1 and N2
Are equal. However, there is a problem when a plurality of sense lines SN share one reference sense line RN and an equalizing circuit is provided between each sense line SN and the reference sense line. At this time, while one equalizing circuit is connected to each sense line SN, a plurality of equalizing circuits are connected to the reference sense line. The noise N1 becomes several times larger through the plurality of equalizing circuits, and becomes larger than the noise N2 coupled to each sense line SN.

Moreover, these switching noises N1,
The size of N2 may be as large as about 200 mv, and may be about 10 times the potential difference between the data line DL and the reference data line RDL during data sensing. As a result, the sense line SN
And the potential relationship between the reference sense line RSN and the reference sense line RSN are temporarily inverted, and must be inverted again by the sense amplifier, which makes high-speed sensing difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device capable of high-speed access by reducing the influence of switching noise in an equalizing circuit.

[0016]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention has a memory cell array in which memory cells for storing data are arranged according to the presence or absence or magnitude of current draw, and a plurality of memory cells to which read data of the memory cell array is transferred. A sense amplifier array including a plurality of sense lines, a reference sense line for applying a reference potential during a read operation, and a plurality of sense amplifiers for detecting a potential difference between the plurality of sense lines and the reference sense line; A plurality of equalizing circuits for selectively shorting each of the sense lines and the reference sense line, and each of the equalizing circuits has one end connected to the sense line and the reference sense line, respectively. First and second MIs whose other ends are commonly connected
A first MISF on the sense line side having an SFET
The gate area of ET is the second MIS on the side of the reference sense line.
It is characterized in that it is set larger than the gate area of the FET.

In the case where a reference sense line is shared to form a sense amplifier row and an equalizing circuit is provided between each sense line and a common reference sense line, an equalizing circuit is formed by connecting two MISFETs having different gate areas in series. By making the connection, and increasing the gate area of the MISFET on the sense line side, it is possible to suppress the difference in magnitude between the switching noise on the sense line and the switching noise on the reference sense line when the equalization is released. .

Specifically, for example, when the number of sense lines is n (n is an integer of 2 or more) with respect to one reference sense line, the gate area of the first MISFET on the sense line side is It is set to n times the gate area of the second MISFET. This makes it possible to equalize the magnitude of the switching noise on the reference sense line via the n equalizing circuits and the magnitude of the switching noise on each sense line via the one equalizing circuit. As described above, high-speed access becomes possible.

In the present invention, specifically, the sense amplifier array includes a plurality of differential amplifiers each having a first input terminal connected to the sense line and a second input terminal commonly connected to the reference sense line. An amplifier, a plurality of first current source loads for supplying current to each sense line, and a second current source load for supplying current to the reference sense line can be provided. The sense amplifier array also includes a plurality of inverters each having an input terminal connected to a sense line, a first current source MISFET having a gate and a drain commonly connected for supplying current to a reference sense line, and a sense amplifier. It can be configured to include a first current source MISFET for supplying current to the line and a plurality of second current source MISFETs forming a current mirror.

In the present invention, preferably, each sense line is connected to a corresponding data line via a first separation circuit, and the reference sense line is connected to a reference data line via a second separation circuit. Shall be connected.

In the present invention, the first and second MISFETs constituting each equalizing circuit can be of, for example, an n-channel type. Alternatively, in each equalizing circuit, the first and second MISFETs are of an n-channel type, and a p-channel MISFET is connected in parallel to the first and second MISFETs respectively, and one end of the equalizing circuit is connected to the sense line. A series circuit of the connected first CMOS transfer gate and the second CMOS gate having one end connected to the reference sense line may be configured. In this case, when the number of sense lines is n (n is an integer of 2 or more) with respect to one reference sense line, the gate area of the first CMOS transfer gate is n times as large as the gate area of the second CMOS transfer gate. What is necessary is just to become. Switching resistance between the first and second CMOS transfer gates or interposition of resistance between the first and second CMOS transfer gates and the sense line and the reference sense line may also cause switching noise. It is effective in reducing the amount of slag.

The semiconductor memory device according to the present invention also includes:
A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current draw are arranged; a sense line to which read data of the memory cell array is transferred;
A reference sense line for applying a reference potential during a read operation; a sense amplifier that detects a potential difference between the sense line and the reference sense line to determine read data; An equalizing MISFET interposed between the sense line and the reference sense line for selectively short-circuiting the sense line and the reference sense line;
And a resistor interposed between the ET and the sense line and the reference sense line.

As described above, the system in which the resistance is interposed between the sense line and the reference sense line of the equalizing MISFET is used even when the sense line and the reference sense line are arranged in a 1: 1 pair. The effect of reducing switching noise can be expected.

The semiconductor memory device according to the present invention further comprises:
A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current draw are arranged; a sense line to which read data of the memory cell array is transferred;
A reference sense line for applying a reference potential during a read operation; a sense amplifier that detects a potential difference between the sense line and the reference sense line to determine read data; An equalizing circuit, which is provided between the sense line and the reference sense line, and is configured to selectively short-circuit the sense line and the reference sense line, and an n-channel side gate and a p-type gate of the CMOS transfer gate based on a reference timing signal. And a timing control circuit for generating complementary first and second equalizing signals for driving the channel-side gates with the same number of logic gate stages.

In the case where the equalizing circuit is constituted by CMOS transfer gates, if there is a timing deviation between the complementary first and second equalizing signals for driving the gates on the n-channel side and the p-channel side, switching noise may be caused. Become. On the other hand, by using a timing control circuit that generates the first and second equalizing signals with the same number of logic gate stages, switching noise can be reduced.

Specifically, the timing control circuit
For example, one end is commonly connected to a first output terminal for a first equalizing signal, and the other end is fixed to a power supply potential and a ground potential, respectively, and is driven complementarily based on a reference timing signal to connect the power supply potential and the ground. First and second CMOS transfer gates for selectively outputting a potential to a first output terminal, one end of which is commonly connected to a second output terminal for a second equalizing signal, and the other end of which is connected to a ground potential, respectively. And the power supply potential, and the first and second
, And third and fourth CMOS transfer gates which are simultaneously driven and selectively output the ground potential and the power supply potential to the second output terminal.

The semiconductor memory device according to the present invention further comprises:
A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current drawing are arranged, a plurality of sense lines to which read data of the memory cell array is transferred, and a reference sense line for applying a reference potential during a read operation. A sense amplifier array including a plurality of sense amplifiers for detecting a potential difference between the plurality of sense lines and the reference sense line, and between each of the plurality of sense lines,
A plurality of equalizing circuits for selectively shorting each of the plurality of sense lines and the reference sense line,
It is characterized by having.

As described above, by providing the equalizing circuit not only between the sense line and the reference sense line but also between each sense line, it is possible to effectively reduce the influence of noise due to simultaneous switching of the equalizing circuit. it can. In this case, the equalizing circuit may be the same as the conventional one.
By connecting the same number of equalizing circuits to each of the plurality of sense lines and the reference sense lines, preferable results can be obtained.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a flash memory according to an embodiment of the present invention. The memory cell array 1 includes a word line WL and a bit line B
A plurality of Ls are arranged so as to cross each other, and a memory cell MC is arranged at each intersection. Specifically, in this embodiment, as shown in FIG. 2, the memory cell array 1 is configured by connecting memory cells MC having a stacked gate MISFET structure in a NOR type.

A row decoder 2 is provided for selecting a word line of the memory cell array 1, and a column decoder 3 and a column gate 4 selectively activated thereby are provided for selecting a bit line. The address is sent to the control circuit 9 via the address buffer 8, and the internal row address signal and the internal column address signal are transferred to the row decoder 2 and the column decoder 3, respectively.

For writing and erasing data, a potential obtained by increasing the power supply potential is used as described later. Therefore, a booster circuit 10 controlled by the control circuit 9 according to the operation mode is provided. The output of the booster circuit 10 is supplied to the word line WL and the bit line BL via the row decoder 2 and the column decoder 3. The memory cell array 1 is divided into blocks for each unit of batch erasing, and a well decoder 11 is provided to control the well potential of each block.

The flash memory of this embodiment is mounted in a page mode, and the sense amplifier circuit 5 has sense amplifiers connected to data lines DL of one page (for example, 128 bits). The data read by the sense amplifier circuit 5 is held in the page buffer 6, and under the control of the control circuit 9, one page of data is randomly accessed and output via the data output buffer 7a. ing. The write data is temporarily held in the page buffer 6 via the data input buffer 7b, and is transferred to the data line DL under the control of the control circuit 9.

FIG. 3 shows the structure of the memory cell MC. The memory cell MC is a nonvolatile memory cell having a MISFET structure in which a floating gate 24 as a charge storage layer and a control gate 26 are stacked. p-type silicon substrate 2
0, an n-type well 21 is formed.
A mold well 22 is formed, and a memory cell MC is formed in this p-type well 22.

In the memory cell MC, a floating gate 24 of a polycrystalline silicon film is formed on a p-type well 22 with a gate insulating film 23 interposed therebetween.
5, a control gate 26 of a polycrystalline silicon film is formed, and source and drain diffusion layers 27 and 28 are formed on the control gate 26 in a self-aligned manner. The control gate 26 is formed continuously in one direction of the matrix and becomes a word line WL. The drain diffusion layer 28 is a bit line B
L, and the source diffusion layer 27 is connected to the source line SL.

The p-type well 22 is formed independently for each unit of data erasure (hereinafter referred to as a block). FIG. 2 shows a part of a cell array in one block. In the block, word lines WL and bit lines BL are continuous in a direction crossing each other, and source lines SL are connected to source lines of all memory cells in the block. Are connected in common.
Therefore, as described later, the independent bit line BL for each block becomes a local bit line, which is selectively connected to a higher-order main bit line.

The operation of the memory cell MC is as follows. Data writing is performed on the p-type well 22 and the source line S
L is set to 0 V, a write potential of about 10 V is applied to the selected word line WL, and data “0” and “1” are applied to the bit line BL.
6V and 0V are applied according to In a memory cell to which “0” data is given, hot electrons are generated by a strong lateral electric field between the drain and the source, and injected into the floating gate 24. In the case of "1" data, such electron injection does not occur.

As a result, the state where electrons are injected into the floating gate to increase the threshold value is "0". In the case of "1" data, no hot electrons are generated, and therefore no electrons are injected into the floating gate, and the erased state, that is, the "1" data state with a low threshold is maintained.

In data erasing, batch erasing is performed in block units. At this time, 10 V is applied to the p-type well 22 and the source line SL of the selected block together with the n-type well 21.
And a voltage of about -7 V is applied to all the word lines WL in the selected block. As a result, a large electric field is applied to the gate insulating film 23 of the memory cell in the block, and electrons of the floating gate are emitted to the channel side by the Fowler-Noldheim current (tunnel current), and the data "1" is erased.

For data reading, a read voltage set to an intermediate value between threshold values of data "0" and "1" is applied to a selected word line, and the presence or absence of a current draw of a memory cell is connected to a bit line. Judge by the sense amplifier.

FIG. 4 shows a configuration of the column decoder 3 and the column gate 4. As described above, the number of the bit lines BL for each block BLKi, BLKi + 1,... Of the memory cell array 1 is, for example, four, and the main bit lines MBL0, MBL1,. ... are selectively connected. The column decoder 3 has a first column decode circuit CD1 for selecting a bit line of each block and a second column decode circuit CD2 for selecting a main bit line.

The column gate transistors QN0 to QN3, QN4 to QN are provided by first column selection lines Hi, Hi + 1,... Which are output lines of the first column decode circuit CD1.
The gates of 7,... Are controlled. A column gate transistor QN for selecting a main bit line by a second column selection line D which is an output line of the second column decode circuit CD2
, QN22,... Are controlled. As described above, the selected bit line BL of the selected block is connected to the main bit line MBL through the column gate transistors activated by the first column selection lines Hi, Hi + 1,..., And the main bit line MBL is connected to the second bit line. Is connected to the data line DL via the column gate transistor activated by the column selection line D.

FIG. 5 shows a main configuration of the sense amplifier circuit 5 connected to the data line DL. In this embodiment, in order to perform the page mode operation, the sense amplifier circuit 5 has one page (for example, one page = 8wo).
rds = 128 bits) are arranged, and it is a basic feature of this embodiment that a large number of these sense amplifiers are configured to share a reference potential generating circuit. FIG. 5 shows a configuration of one sense amplifier row 50 including n (n is an integer of 2 or more) sense amplifier bodies and a reference potential generating circuit 60 shared by each sense amplifier in the sense amplifier row 50. ing.

Each sense amplifier body of the sense amplifier array 50 is a differential amplifier 51 in the case of FIG.
Are connected to independent sense lines SN, and the other input terminals are commonly connected to a reference sense line RSN. Each sense line SN is a p-channel MISFET (hereinafter referred to as PMOS
It is connected to a power supply Vcc via a current source load 52 composed of a transistor QP1. Similarly, the reference sense line RSN is connected to a power supply Vcc via a current source load 61 including a PMOS transistor QP2 having a gate and a drain connected.
Connected to.

Each of the sense lines SN is an n-channel MISFET whose gate is supplied with a predetermined bias BIAS.
A data line D is connected via a clamp circuit (separation circuit) 53 including a QN41 (hereinafter referred to as an NMOS transistor).
L. Similarly, the reference sense line RSN is connected to the reference data line DL via a clamp circuit 62 composed of an NMOS transistor QN42 having a gate supplied with a predetermined bias BIAS. These clamp circuits 5
The reference numerals 3 and 62 are provided for suppressing the potential amplitude of the data line DL and the reference data line RDL and increasing the potential amplitude of the sense line SN and the reference sense line RSN as in the related art.

The reference data line RDL is connected to a current source 63 for flowing a current intermediate between the current values of “0” and “1” data of the memory cells MC connected to the data line DL. As described above, the data line DL has a large capacitance because it is connected to the bit line BL via the multi-stage column gate transistors. Therefore, the dummy data line capacitance CR is connected to the reference data line RDL so that the load capacitance is substantially the same as the capacitance of the data line DL. That is, the portion of the reference sense line RSN, the current source load 61 connected to the reference sense line RSN, and the reference data line RDL connected to the reference sense line RSN via the clamp circuit 62 are shared by the sense amplifier array 50 to generate the reference potential. The circuit 60 is constituted.

Between each sense line SN of the sense amplifier row 50 and a common reference sense line RSN, n equalizing circuits E01, E02,
, E0n are provided. A specific configuration of the equalizing circuit group 70 will be described later.

As described above, when the sense amplifier row 50 shares the reference potential generating circuit 60, a plurality of sense amplifier bodies are connected to the reference sense line RSN, so that the capacitance of the sense line SN and the reference sense line RSN is increased. Imbalance. As described in the related art, in order to perform high-speed data sensing, the capacitance balance between the data line DL and the reference data line RDL, the sense line SN and the reference sense line RS
It is also important to balance the capacity of N.

In consideration of this point, preferably, a dummy sense line capacitance CS is added to each sense line SN as shown in FIG. 6 based on FIG. As described above, the capacity of the sense line SN is intentionally increased to match the capacity increase caused by connecting a plurality of sense amplifiers to the reference sense line RSN, and the capacities of the sense line SN and the reference sense line RSN are increased. To be substantially the same.

FIG. 7 shows another configuration example of the sense amplifier array 50 and the reference potential generating circuit 60. In this example, the sense amplifier body uses an inverter 51a. Since the sense amplifier itself is not a differential amplifier, the reference sense line RSN
And a current source load 52 connected to each sense line SN constitute a current mirror circuit. That is, the gate and the drain of the PMOS transistor QP2 of the current source load 61 are shared by the reference sense line R
The gate of the PMOS transistor QP1, which is connected to the SN and is the current source load of each sense amplifier body, is connected to the reference sense line RSN.

Also in this case, n equalizing circuits E0 for selectively short-circuiting each of sense lines SN of sense amplifier row 50 and a common reference sense line RSN are provided.
, E0n, equalizing circuit group 70
Is provided. FIG. 8 is based on the configuration of FIG.
Similarly to the above, a dummy sense line capacitance CS is added to each sense line SN so that the capacitances of the sense line SN and the reference sense line RSN become substantially the same.

FIG. 9 shows the equalizing circuit shown in FIGS.
The specific configuration of the road group 70 is shown. Each equalization time
Paths E01, E02, ... are two NMOS transistors
QN _L, QN_SAre connected in series. two
NMOS transistor QN_L, QN_SThe gate of Equali
Control signal at the same time. Here is the sense line
NMOS transistor QN having one end connected to SN
_LIs an NMOS whose one end is connected to the reference sense line RSN.
Transistor QN_SLarger gate area than
And Specifically, for example, when the number of reference sense lines RSN is n
When shared by the sense line SN, the NMOS transistor
Star QN_LThe gate area of the NMOS transistor QN_S
 N times that of

FIG. 10 shows a layout example of such an equalizing circuit. Two NMOS transistors Q
When the channel lengths L of N _L and QN _S are the same, the channel width is W2 = n × W1.

As described above, by changing the transistor size of the equalizing circuit seen from each sense line SN and the reference sense line RSN, the switching noise caused by the difference in the number of equalizing circuits seen from each sense line SN and the reference sense line RSN is reduced. The effect can be reduced.
As shown in FIG. 11, two transistors QN _L and QN _S
And the sense line SN and the reference sense line RS, respectively.
The coupling capacitances C2 and C1 with N are C2 = n · C1 from the difference in gate area. On the other hand, the reference sense line RSN
Is connected to a capacitor C1 of n equalizing circuits. That is, the capacitive coupling from the gate to the sense line SN is performed via one large capacitance C2, whereas the reference sense line RSN is performed via n small capacitances C1.

Therefore, according to this embodiment, it is possible to make the switching noise on the sense line SN and the reference sense line RSN substantially equal when canceling the equalization.
That is, the potential difference between the sense line SN and the reference sense line RSN is maintained regardless of the switching noise. As a result, the switching of the sense line S
The potential difference between N and the reference sense line RSN is reversed, so that a situation in which data sensing is not delayed does not occur, and high-speed access becomes possible. Note that two NMOS transistors QN _S ,
Coupling to the connection node of QN _L noise, since the two NMOS transistors QN _S, QN _L is simultaneously turned off and is not transmitted to the outside.

It should be noted that the differential amplifier 51 is shown in FIGS.
It can be configured as shown in FIG. FIG. 12 (a)
Is an example in which a pair of differential PMOS transistors QP21 and QP22 and one operational amplifier OP having a current mirror load by NMOS transistors QN31 and QN32 are used. FIG. 12B shows a two-stage operational amplifier O
This is an example using P1 and OP2. FIG. 12C shows an example in which two operational amplifiers OP11 and OP12 are provided side by side in the input stage, and an operational amplifier OP12 that takes the difference between these outputs is provided.

FIG. 13A shows the current source load 52.
A resistor R can be used as shown in FIG.
As shown in (b), a PMOS transistor QP1 whose gate is grounded can be used. Clamp circuit 53
14A, a configuration may be adopted in which a bias voltage generation circuit 531 for driving the gate of the NMOS transistor QN41 is provided as shown in FIG.
As shown in (5), a feedback type in which the potential of the data line DL is fed back by the inverter 532 to control the gate of the NMOS transistor QN41 may be used.

The dummy sense line capacitance CS in FIG.
For example, as shown in FIG. 15, a PMOS transistor having the same gate area as the gate area of the input-stage PMOS transistor of the differential amplifier 51 as the sense amplifier body may be used and (number of sense amplifiers-1) may be provided. Similarly, the dummy sense line capacitance CS in the case of FIG.
PMOS having the same gate area as two PMOS transistors
It suffices to provide (the number of sense amplifiers-1) transistors in parallel.

FIG. 16 shows the read operation timing in the page mode of the flash memory according to this embodiment. A page address Add is input, a memory cell is selected, the selected memory cell data is sensed, and the sensing result is latched in a page buffer. The internal operation so far requires a time of, for example, 100 ns in order to utilize the charging and discharging of the data line having a large load capacity connected to the main bit line and the local bit line. After the data for one page is latched in the page buffer, the addresses in the page are switched at high speed as a0, a1, a2,... And the corresponding data D0, D1, D2,. This intra-page access requires only about 25 ns, for example, since there is no charge / discharge of a large load capacity.

FIG. 17 shows another example of the configuration of the equalizing circuit group 70. Unlike the configuration of FIG. 9, the equalizing circuit E0
, E02, ..., NMOS transistor and PMO
Two CMOS transfer gate TG _L connected in parallel with S transistors are connected in series TG _S. NMOS
The gates of the transistor side and the PMOS transistor side are
It is controlled by complementary equalizing signals EQL and EQLB. CMOS transfer gate TG C of the gate area reference sense line RSN side of _L connected to the sense line SN
To that of n times the MOS transfer gates TG _S is the same as in the case of using a single transistor.

[0060] Two CMOS transfer gate TG _L Thus, in the case of using TG _S as the equalizing circuit, N
If the MOS transistor and the PMOS transistor are simultaneously turned on and off, switching noise does not occur in principle as described in the related art. When one equalizing signal EQL changes from “H” to “L”, the other equalizing signal EQLB changes from “L” to “H”,
This is because the capacitive coupling is canceled. However, since the equalizing signals EQL and EQLB are normally generated from the basic timing signal through gates having different numbers of stages,
Since a timing difference occurs between the two switching operations, it is effective to connect two transistors having different gate areas in series even when such a CMOS transfer gate is used.

However, the CMOS transfer gate TG
_L, in the case of using TG _S, equalize signal EQL, EQ
Another problem arises from the LB timing differences. As shown in FIG. 18, the equalizing signal EQL changes from "H" to "L".
The transition to, a transition from "H" of the equalizing signal EQLB to "L" is delayed, the CMOS transfer gate TG _L, TG _S, PMOS transistor does not turn off even NMOS transistor is turned OFF period Occurs.

Then, as shown in FIG.
S transfer gates TG _L, TG _S respectively reference sense line RSN and sense line SN to switching noise a gate of the NMOS transistor, when the b ride, connection of two transfer gates from the gate of the larger transfer gate TG _L of noise from the equalizing circuit of n partial coupling to the point it is transferred as noise c in the reference sense line RSN through the PMOS transistor of the transfer gate TG _S not turned off.

[0063] The smaller noise coupling to the connection point of two of the transfer gate from the gate of the transfer gate TG _S also, sense line via the PMOS transistor of the transfer gate TG _L that is not turned off S
N, which is negligible compared to noise c. This is because the gate area is small and only one equalizing circuit is connected to each sense line SN. As a result, as shown in FIG. 18, the switching noise N11 on the reference sense line RSN is
The switching noise N12 is larger than the switching noise N12.

Such equalizing signals EQL, EQLB
For switching noise due to timing difference, for example, as illustrated in Figure 20, it is effective to connect a resistor R1 between the two CMOS transfer gates TG _L, TG _S. Thus, the leakage noise c described with reference to FIG. 19 can be reduced.

Further, as shown in FIG. 21, two transfer gates TGL and TG constituting the equalizing circuit E are provided.
It is also effective to insert resistors R2 and R3 between S and the sense line SN and the reference sense line RSN, respectively. This alleviates not only the leakage noise c due to the timing difference between the equalization signals described with reference to FIG. 19 but also the noises a and b that couple the reference sense line RSN and the sense line SN directly from each gate. it can.

The resistors R1 and R shown in FIGS.
As R2 and R3, a diffusion layer resistance, a polycrystalline silicon film resistance, a MOS transistor having a constant voltage applied to the gate, or the like can be used. However, since these resistors R1, R2, and R3 limit the function of the equalizing circuit, an excessively large resistance value cannot be used.

As shown in FIG. 20 or FIG. 21, a method of reducing switching noise by using a resistor is as follows.
The present invention can be applied not only to the case where the CMOS transfer gate is used but also to the case where two single-channel MOS transistors are connected in series as described with reference to FIG. For example, two MOS transistors are located at a distance from each other,
In the case where a timing difference occurs even if this is controlled by the same equalizing signal, it is effective to reduce noise by using a resistor.

As described above, the equalizing circuit is implemented by the CMO
In the case of the configuration using the S transfer gate, if the PMOS transistor and the NMOS transistor are simultaneously turned on and off, the switching noise does not cause any problem. An embodiment taking this point into consideration will be described below.

FIG. 22 shows the relationship between the sense line SN and the reference sense line R.
One CMOS transistor gate TG1 during SN
To form the equalizing circuit E. CMO
An equalizing signal EQL for driving the gate of the S transfer gate TG1 on the NMOS transistor side;
Equalize signal EQ that drives the gate on the transistor side
A timing control circuit 80 is used to generate LB based on the reference timing signal EQLS without any timing difference.

The timing control circuit 80 has a pair of two CMOS transfer gates TG2 and TG3 for generating an equalize signal EQL and a pair of two CMOS transfer gates TG4 and TG5 for generating an equalize signal EQLB. One end of each of the pair of transfer gates TG2 and TG3 is connected to the power supply potential Vcc and the ground potential Vss, respectively, and the other end is connected to the terminal N.
1 are connected in common. The terminal N1 is a terminal that outputs the equalize signal EQL via the inverter buffer INV1. The other pair of transfer gates TG4,
One end of each of the TGs 5 is connected to the ground potential Vss and the power supply potential Vcc, and the other end is commonly connected to the terminal N1. Terminal N2 is connected via an inverter buffer INV2.
The output terminal for the equalize signal EQLB.

NM of transfer gates TG2 and TG4
OS transistor and transfer gates TG3, TG
The gate of the PMOS transistor 5 is a signal E obtained by inverting the reference timing signal EQLS by the inverter INV11.
Driven by QLSB. Transfer gate TG
The gates of the PMOS transistors 2 and TG4 and the gates of the NMOS transistors of the transfer gates TG3 and TG5 are driven by the signal EQLSB obtained by further inverting the signal EQLSB by the inverter INV12. Inverter IN
Outputs of V1 and INV2 become equalizing signals EQL and EQLB for driving the gates of the NMOS transistor and the PMOS transistor of the transfer gate TG1, respectively.

Such a timing control circuit 80
Is used, equalizing signals EQL and EQLB complementary to "H" and "L" can be obtained from the reference timing signal EQLS with the same number of logic gate stages. This is shown in FIG. When the reference timing signal EQLS rises (time t1), the signal EQLS is slightly delayed.
B becomes "L" (time t2). Thus, the transfer gates TG2 and TG4 are turned off from on, and the transfer gates TG3 and TG5 are simultaneously turned on instead.

At this time, transfer gates TG3, T
In G5, there is a difference in the on-timing of the PMOS transistor and the NMOS transistor, but when the PMOS transistor is turned on, Vss and Vcc are supplied to the input terminals N1 and N2 of the inverters INV1 and INV2, respectively.
At the same time, the equalizing signals EQL = “H”, EQLB =
It becomes “L” (time t3). That is, in the timing control circuit 80, there is no difference in the number of gate stages from the rising of the reference timing signal EQLS to the rising of the equalizing signal EQL and the falling of the equalizing signal EQLB.

When the equalizing signal EQL changes from “H” to “L”
The same applies to the transition to. Reference timing signal EQL
S becomes "L" (time t4), and a little later, the transfer gates TG2 and TG4 are simultaneously turned on (time t5). As a result, Vcc and Vss are supplied to the input terminals of the inverters INV1 and INV2, and EQL =
“H”, EQLB = “L” (time t6). At this time, there is no timing shift.

As a result, equalizing signals EQL and EQLB with no timing shift are applied to transfer gate TG1 of equalizing circuit E, so that sense line S
No switching noise is applied to N and the reference sense line RSN. The transfer gates TG2 to TG
5 is sufficiently large, the inverter INV
1 and INV2 may be omitted, and the terminals N1 and N2 may be directly used as output terminals for the equalizing signals EQL and EQLB.

FIG. 24 shows the structure of an equalizing circuit group 70 according to another embodiment. In this embodiment, the number of equalizing circuits connected to one reference sense line RSN and a plurality of sense lines SN sharing the same is set to be the same. That is, FIG. 24 shows the case where the number of the sense lines SN is four.
In addition to providing E04, equalizing circuits E12 and E1 are also provided between sense line SN1 and all other sense lines SN2 to SN4.
3, E14 are provided, and the sense line SN2 and the sense line SN3 are provided.
Equalizing circuits E23 and E24 are also provided between SN4,
The equalizing circuit E34 is also provided between the sense lines SN3 and SN4.
Is provided.

As described above, by connecting the same number of equalizing circuits to each of the reference sense line RS and each of the sense lines SN, specifically, four equalizing circuits in this embodiment, the equalizing circuit group 70 is formed. Features controlled on and off at the same time,
When equalization is released, the reference sense line RSN and each sense line S
The switching noise on N is the same. Therefore, even if the equalizing circuit configuration described in the above embodiment is not used for the equalizing circuit group 70 and a conventionally known equalizing circuit configuration is used, a delay in the sensing operation due to switching noise does not occur.

The present invention is not limited to the above embodiment.
For example, in the above-described embodiment, the NOR type flash memory has been described. However, the present invention is similarly applied to various other semiconductor memories in which the memory cells are of a current draw type and use a current detection type sense amplifier. It is possible. Further, in the embodiment, the flash memory having the page mode is described. However, since a large number of sense amplifiers are similarly arranged in the burst mode, it is effective to apply the present invention. In this case, the data latched in the page buffer can be parallel / serial converted and output by providing a clock driven shift register. Further, since the equalizing circuit E of the embodiment shown in FIGS. 21 and 22 is a system for reducing the switching noise itself, it is not equipped with the page mode or the burst mode, but the sense line and the reference sense line are paired by 1: 1. The present invention is also applicable to a semiconductor memory of a prepared type. Furthermore, the method of FIG. 21 is also effective when applied to the case where one equalizing MISFET or one equalizing CMOS transfer gate is used.

[0079]

As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of high-speed access by reducing the influence of switching noise by improving the equalizing circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a flash memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a memory cell array of the flash memory.

FIG. 3 is a sectional view showing a memory cell structure of the flash memory.

FIG. 4 is a diagram showing an equivalent circuit of a column decoder and a column gate of the flash memory.

FIG. 5 is an equivalent circuit showing a configuration example of a main part of a sense amplifier circuit of the flash memory.

FIG. 6 is an equivalent circuit showing a configuration example of a main part of another sense amplifier circuit.

FIG. 7 is an equivalent circuit showing a configuration example of a main part of another sense amplifier circuit.

FIG. 8 is an equivalent circuit showing a configuration example of a main part of another sense amplifier circuit.

FIG. 9 is a diagram showing a configuration example of an equalizing circuit of the flash memory.

FIG. 10 is a diagram showing a layout of the equalizing circuit.

FIG. 11 is a diagram for explaining switching noise caused by the equalizing circuit.

FIG. 12 is a diagram illustrating a configuration example of a differential amplifier in FIG. 5;

13 is a diagram illustrating a configuration example of a current source load of FIG. 5;

FIG. 14 is a diagram illustrating a configuration example of a clamp circuit in FIG. 5;

FIG. 15 is a diagram showing a configuration example of a dummy sense line capacitance shown in FIGS. 5 and 7;

FIG. 16 is a timing chart for explaining a page mode read operation according to the embodiment;

FIG. 17 is a diagram illustrating another configuration example of the equalizing circuit.

FIG. 18 is a diagram for explaining switching noise of the equalizing circuit.

FIG. 19 is a diagram showing how switching noise is generated.

20 is a diagram illustrating a configuration example of an equalizing circuit obtained by improving the configuration of FIG. 17;

21 is a diagram illustrating a configuration example of an equalizing circuit obtained by improving the configuration of FIG. 17;

FIG. 22 is a diagram illustrating a configuration example of an equalizing circuit according to another embodiment.

FIG. 23 is a timing chart for explaining the operation of the equalizing circuit of FIG. 22;

FIG. 24 is a diagram illustrating a configuration example of an equalizing circuit according to another embodiment;

FIG. 25 is a diagram showing a configuration of a conventional sense amplifier circuit.

FIG. 26 is a diagram showing a potential change of a data line and a sense line during data sensing.

FIG. 27 is a diagram for explaining an equalizing operation by the equalizing circuit.

FIG. 28 is a diagram showing a state of capacitive coupling by the equalizing circuit.

FIG. 29 is a diagram for explaining switching noise caused by the equalizing circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Column decoder, 4 ... Column gate, 5 ... Sense amplifier circuit,
6 page buffer, 7a, 7b data buffer, 8
... address buffer, 9 ... control circuit, 10 ... boost circuit, 11 ... source well decoder, 50, 50A,
50B: sense amplifier array, 60: reference potential generation circuit, 5
DESCRIPTION OF SYMBOLS 1 ... Differential amplifier, 51a ... Inverter, 52,61 ... Current source load, 53,62 ... Clamp circuit, 63 ... Current source
70: equalizing circuit group, SN: sense line, RSN: reference sense line, DL: data line, RDL: reference data line,
CS ... dummy sense line capacity, CR ... dummy data line capacity, E, E01~E0n ... equalizing circuit, QN _L, Q
N _S ... NMOS transistor, TG _L, TG _S ... CMOS
Transfer gates, TG1 to TG5 ... CMOS transfer gates.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AA02 AD05 AD11 AD15 AE05

Claims (17)

[Claims] 1. A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current draw are arranged, a plurality of sense lines to which read data of the memory cell array is transferred, and a reference potential for giving a reference potential during a read operation. A reference sense line, a sense amplifier row including a plurality of sense amplifiers for detecting a potential difference between the plurality of sense lines and the reference sense line, and between each of the plurality of sense lines and the reference sense line. And a plurality of equalizing circuits for selectively short-circuiting the first and second equalizing circuits, wherein each of the equalizing circuits has a first end connected to the sense line and the reference sense line, and a second end commonly connected to the other end. A gate surface of the second MISFET on the reference sense line side having a MISFET and having a gate area of the first MISFET on the sense line side; The semiconductor memory device characterized by being set larger. 2. When the number of sense lines is n (n is an integer of 2 or more) with respect to one reference sense line, the first M
2. The semiconductor memory device according to claim 1, wherein the gate area of the ISFET is set to be n times the gate area of the second MISFET. 3. The sense amplifier array includes: a plurality of differential amplifiers each having a first input terminal connected to the sense line, and a second input terminal commonly connected to the reference sense line; 3. The semiconductor memory according to claim 1, comprising: a plurality of first current source loads for supplying a current to a sense line; and a second current source load for supplying a current to the reference sense line. apparatus. 4. A sense amplifier array comprising: a plurality of inverters each having an input terminal connected to the sense line; and a first inverter having a gate and a drain commonly connected for supplying current to the reference sense line. A current source MISFET; and a plurality of second current sources forming a current mirror with the first current source MISFET for supplying a current to each of the sense lines.
3. The semiconductor memory device according to claim 1, further comprising a current source MISFET. 5. The sense line is connected to a corresponding data line via a first separation circuit, and the reference sense line is connected to a reference data line via a second separation circuit. 3. The semiconductor memory device according to claim 1, wherein: 6. The first and second MISFETs each have an n
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is of a channel type. 7. The equalizer circuit according to claim 1, wherein the first and second MISFETs are n-channel type, and the first and second MISFETs are connected to the p-channel type MISFET in parallel, respectively. 2. A series circuit comprising a first CMOS transfer gate having one end connected to a sense line and a second CMOS gate having one end connected to the reference sense line.
The semiconductor memory device according to claim 1. 8. When the number of sense lines is n (n is an integer of 2 or more) with respect to one reference sense line, the first C
The gate area of the MOS transfer gate is the second C
8. The semiconductor memory device according to claim 7, wherein the gate area is set to n times the gate area of the MOS transfer gate. 9. The semiconductor memory device according to claim 7, wherein a resistor is interposed between said first and second CMOS transfer gates. 10. The semiconductor device according to claim 7, wherein a resistor is interposed between each of the first and second CMOS transfer gates and each of the sense line and the reference sense line.
The semiconductor memory device according to claim 1. 11. A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current draw, a sense line to which read data of the memory cell array is transferred, and a reference for applying a reference potential during a read operation A sense line, a sense amplifier for detecting a potential difference between the sense line and the reference sense line to determine read data, and a sense amplifier provided between the sense line and the reference sense line;
An equalizing MISFET for selectively short-circuiting the sense line and the reference sense line, and a resistor interposed between the equalizing MISFET, the sense line, and the reference sense line. Semiconductor memory device. 12. A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current draw are arranged, a sense line to which read data of this memory cell array is transferred, and a reference for applying a reference potential during a read operation. A sense line, a sense amplifier for detecting a potential difference between the sense line and the reference sense line to determine read data, and a sense amplifier provided between the sense line and the reference sense line;
An equalizing circuit including a CMOS transfer gate for selectively shorting the sense line and the reference sense line; and driving an n-channel side gate and a p-channel side gate of the CMOS transfer gate based on a reference timing signal. And a timing control circuit for generating first and second equalizing signals having a complementary relationship for the same number of logic gate stages. 13. The timing control circuit has one end commonly connected to a first output terminal for the first equalizing signal, and the other end fixed to a power supply potential and a ground potential, respectively, based on the reference timing signal. First and second CMOS transfer gates which are driven complementarily and selectively output a power supply potential and a ground potential to the first output terminal, one end of which is a second for the second equalizing signal. The other end is fixed to a ground potential and a power supply potential, respectively, and is driven simultaneously with the first and second CMOS transfer gates based on the reference timing signal to select a ground potential and a power supply potential. 13. The semiconductor device according to claim 12, further comprising third and fourth CMOS transfer gates for outputting to said second output terminal. Li equipment. 14. A memory cell array in which memory cells for storing data according to the presence or absence or magnitude of current draw are arranged, a plurality of sense lines to which read data of the memory cell array is transferred, and a reference potential for giving a reference potential during a read operation. A plurality of sense amplifiers including a plurality of sense amplifiers for detecting a potential difference between the plurality of sense lines and the reference sense line; and a plurality of sense amplifiers between each of the plurality of sense lines and the plurality of sense lines. A semiconductor memory device, comprising: a plurality of equalizing circuits for selectively shorting each of the lines and the reference sense line. 15. The semiconductor memory device according to claim 14, wherein an equal number of equalizing circuits are connected to each of said plurality of sense lines and reference sense lines. 16. Each of the plurality of sense lines is connected to the remaining sense lines via the equalizing circuit,
15. The semiconductor memory device according to claim 14, wherein said reference sense line is connected to each of said plurality of sense lines via said equalizing circuit. 17. The memory cell according to claim 1, wherein said memory cell is an electrically rewritable nonvolatile memory cell having a MISFET structure in which a charge storage layer and a control gate are stacked. The semiconductor memory device according to any one of the above.