JP2002367386A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory adopting a sense amplifier circuit system in which the area of dummy data line capacitors for generating a reference potential is reduced and chip area can be reduced. SOLUTION: A sense amplifier column 50 comprising a plurality of sense amplifiers shares a reference potential generating circuit 60. One side of the input terminal of a differential amplifier 51 of each sense amplifier main body is connected to a sense line SN, and the other side of the input terminal is connected in common to a reference sense line RSN. Current source loads 52, 61 are connected to the sense line SN and the reference sense line RSN. The sense line SN and the reference sense line RSN are connected respectively to a data line DL and a reference data line RDL through clamp circuits 53, 62. A current source 63 for supplying an intermediate current between '0' and '1' is connected to the reference data line RDL, and a dummy data line capacitor CR corresponding to the capacity of the data line DL is connected to the reference data line RDL. As the reference sense line RSN is shared, dummy sense line capacitors CS are added to the sense line SN to balance the capacity of the reference sense line RSN and the sense line SN.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which stores data depending on the presence or absence or magnitude of a current draw. Regarding improvement.

[0002]

2. Description of the Related Art As a semiconductor memory device, an EEPROM capable of storing data in a nonvolatile manner and electrically rewritable.
It has been known. Among EEPROMs, a type in which a plurality of memory cells are collectively erased is called a flash memory. In this type of semiconductor memory, a memory cell stores data depending on the presence or absence or magnitude of current draw, and therefore, a current read type sense amplifier circuit is used. As such a sense amplifier circuit, a method of reading data by comparing a potential of a data line from which data is read from a memory cell with a reference potential of a reference data line is often used.

FIG. 16 shows a configuration of such a conventional sense amplifier circuit. The sense amplifier circuit main body is constituted by a differential amplifier 101. One input terminal of the differential amplifier 101 is connected to the sense line SN, and the other input terminal is connected to the reference sense line RSN. The current source loads 102 and 2 are respectively applied to the sense line SN and the reference sense line RSN.
01 is connected. The sense line SN and the reference sense line RSN are respectively connected to an isolation circuit (clamp circuit) 105,
It is connected to the data line DL and the reference data line RDL via 202.

[0004] The data of the memory cell MC is read to the data line DL. Specifically, when the flash memory has a large capacity, the data of the memory cell MC is stored in the local bit line B
L, which is transferred to the main bit line MBL via the first column gate 103 and further transferred to the data line DL via the second column gate 104. Read through. The data “0”,
A current source 203 set to an intermediate current value of the cell current at “1” is connected, and a dummy data line capacitance CR is connected to balance the capacitance with the data line DL.

The current source load 20 on the reference sense line RSN side
1. The separation circuit 202 and the reference data line RDL
The reference potential generation circuit 200 generates a reference potential for detecting the potential of the cell data transferred to the sense line SN.

Since the load on the data line DL is large, it is necessary to detect data while suppressing the potential amplitude for high-speed sensing. For this purpose, a clamp circuit 105 for suppressing the potential amplitude of the data line DL is provided, and the data line DL is separated from the sense line SN by the clamp circuit 105 to reduce the capacitance of the sense line SN. Specifically,
Read data “0” of the data line DL and the sense line SN,
The relationship between the potential amplitudes at the time of “1” is as shown in FIG. 17, and the amplitude ΔVSN at the sense line SN is equal to the data line DL
Is about four times the potential amplitude ΔVDL.

By providing a clamp circuit, the sense line SN
Has a small capacity, but the effect on the sensing speed cannot be ignored. That is, as described with reference to FIG. 17, the amplitude of the sense line SN is about four times larger than that of the data line DL, and the capacitance of the sense line SN is about 1/10 of that of the data line DL. Nearly 30% of the charge to be charged as seen from the load 102 is allocated to the capacitance charging of the sense line SN. Therefore, the sense line SN and the reference sense line R
If the SN capacities are not aligned, the difference in charging speed between the two will result in a delay in data sensing. That is, to perform high-speed data sensing, the data line DL
It is important to balance the capacitance of the sense line SN and the reference sense line RSN together with the capacitance balance of the reference data line RDL.

On the other hand, for fast charging of the sense line SN, it is effective to increase the transistor size (channel width) of the current source load 102, but this also has a limit. This point will be specifically described. FIG. 18 shows a current source load 1
2 shows the relationship between the transistor size 02, the charging time, and the sense line capacitance C _SN . While the size of the load transistor is small, the wiring capacitance of the sense line SN and the capacitance of another circuit connected to the sense line SN are dominant over the capacitance of the load transistor, and the inclination of the sense line capacitance C _SN is small. . However, when the size of the load transistor increases, the gate capacitance and the junction capacitance of the load transistor relatively increase, and the curve of the increase in the sense line capacitance C _SN increases. The charging time decreases rapidly as the size of the load transistor increases while the size of the load transistor is small.
When the size becomes larger than a certain size, the time required for charging itself becomes dominant, and the inclination becomes small. From the above,
There is a limit to increasing the size of the load transistor in order to accelerate the charging of the sense line.

[0009]

In recent years, flash memories have been provided with page modes and burst modes similar to DRAMs.
To mount these modes, for example, one page = 8w
It is necessary to arrange sense amplifiers for ord = 128 bits. However, as described above, a current read type sense amplifier requires a reference data line provided with a large capacity and a dummy data line capacity of a large area. The chip area becomes large.

An object of the present invention is to provide a semiconductor memory device employing a sense amplifier circuit system capable of reducing the area of a dummy data line capacitance for generating a reference potential and reducing the chip area. Another object of the present invention is to provide a semiconductor memory device capable of high-speed access while reducing the area of a dummy data line capacitance for generating a reference potential.

[0011]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention comprises a memory cell array in which memory cells for storing data are arranged according to the presence or absence or magnitude of current draw, and a plurality of memory cells for transmitting and receiving data to and from the memory cell array. Having a data line, a sense amplifier array having a plurality of sense lines respectively connected to the plurality of data lines, and a reference data line for applying a reference potential to a reference sense line shared by the sense amplifier array. It is characterized by.

According to the present invention, the area of the dummy data line capacitance can be reduced by sharing the reference data line with the sense amplifier row including the plurality of sense amplifiers, and thus the chip area can be reduced.

In the present invention, preferably, a dummy sense line capacitance is connected to each sense line. That is, the sharing of the reference data line increases the capacity of the reference sense line as compared with the related art. In response to this, a dummy sense capacitor is added to the sense line to balance the capacity, thereby achieving high-speed operation. Data sensing becomes possible.

More specifically, the sense amplifier array includes a plurality of differential amplifiers each having a first input terminal connected to the sense line and a second input terminal commonly connected to a reference sense line. It can be configured to include a first current source load for supplying a current to the sense line and a second current source load for supplying a current to the reference sense line. The sense amplifier array also includes a plurality of inverters each having an input terminal connected to the sense line, and a current supply circuit for supplying current to the reference sense line.
First current source MIS having gate and drain connected together
An FET, a first current source MISFET for supplying a current to each sense line, and a second current source MISFET forming a current mirror can be provided.

In the present invention, preferably, each sense line is connected to a corresponding data line via a first separation circuit, and the reference sense line is connected to a reference data line via a second separation circuit. Shall be connected.

In the present invention, not all sense amplifier rows include the same number of sense amplifiers. For example, in the case of a semiconductor memory or the like employing a redundant circuit method, a first sense amplifier row including m (m is an integer of 2 or more) sense amplifiers is provided for a normal cell array, and a redundant column cell array is provided. (Ie, spare data line)
A second sense amplifier row including n (n is an integer of 2 or more smaller than m) sense amplifiers is provided.

Even when the sense amplifier arrays having different numbers of sense amplifiers coexist as described above, preferably, the first dummy sense line capacitance is connected to each sense line of the first sense amplifier array, and the second dummy sense line capacitance is connected to the second sense amplifier array. A second dummy sense line capacitance is connected to each sense line of the sense amplifier row. In this case,
When a third dummy sense line capacitor is connected to each of the sense lines and the reference sense line of the second sense amplifier row, high-speed sensing becomes possible by improving the balance of the data line charging speed.

Further, in the present invention, the first and second current source loads connected to the sense line and the reference sense line are set to MI.
When configured with SFETs, these MISFE
It is preferable that the gate area of T is set larger than the gate area of the input stage MISFET of the sense amplifier.
As a result, it is possible to reduce the influence of the threshold variation of the current source load.

Further, it is preferable to connect a sense line charging acceleration circuit for accelerating the charging of the sense lines to each of the sense lines. If such a charge acceleration circuit is connected to the sense line, unlike the case where the charge acceleration circuit is connected to the data line, there is no risk of overcharging the data line. Also, since the capacity of the dummy sense line is added to the sense line, the effect of the capacity increase due to the addition of the charge acceleration circuit is small.

Preferably, in the present invention, the memory cell is a MISFET in which a charge storage layer and a control gate are stacked.
An electrically rewritable nonvolatile memory cell having a structure.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a flash memory according to an embodiment of the present invention. The memory cell array 1 includes a word line WL and a bit line B
A plurality of Ls are arranged so as to cross each other, and a memory cell MC is arranged at each intersection. Specifically, in this embodiment, as shown in FIG. 2, the memory cell array 1 is configured by connecting memory cells MC having a stacked gate MISFET structure in a NOR type.

A row decoder 2 is provided for selecting a word line of the memory cell array 1, and a column decoder 3 and a column gate 4 selectively activated thereby are provided for selecting a bit line. The address is sent to the control circuit 9 via the address buffer 8, and the internal row address signal and the internal column address signal are transferred to the row decoder 2 and the column decoder 3, respectively.

For writing and erasing data, a potential obtained by boosting the power supply potential is used as described later. Therefore, a booster circuit 10 controlled by the control circuit 9 according to the operation mode is provided. The output of the booster circuit 10 is supplied to the word line WL and the bit line BL via the row decoder 2 and the column decoder 3. The memory cell array 1 is divided into blocks for each unit of batch erasing, and a well decoder 11 is provided to control the well potential of each block.

The flash memory of this embodiment is mounted in a page mode, and the sense amplifier circuit 5 has sense amplifiers connected to data lines DL of one page (for example, 128 bits). The data read by the sense amplifier circuit 5 is held in the page buffer 6, and under the control of the control circuit 9, one page of data is randomly accessed and output via the data output buffer 7a. ing. The write data is temporarily held in the page buffer 6 via the data input buffer 7b, and is transferred to the data line DL under the control of the control circuit 9.

FIG. 3 shows the structure of the memory cell MC. The memory cell MC is a nonvolatile memory cell having a MISFET structure in which a floating gate 24 as a charge storage layer and a control gate 26 are stacked. p-type silicon substrate 2
0, an n-type well 21 is formed.
A mold well 22 is formed, and a memory cell MC is formed in this p-type well 22.

In the memory cell MC, a floating gate 24 of a polycrystalline silicon film is formed on a p-type well 22 with a gate insulating film 23 interposed therebetween.
5, a control gate 26 of a polycrystalline silicon film is formed, and source and drain diffusion layers 27 and 28 are formed on the control gate 26 in a self-aligned manner. The control gate 26 is formed continuously in one direction of the matrix and becomes a word line WL. The drain diffusion layer 28 is a bit line B
L, and the source diffusion layer 27 is connected to the source line SL.

The p-type well 22 is formed independently for each unit of data erasure (hereinafter referred to as a block). FIG. 2 shows a part of a cell array in one block, in which word lines WL and bit lines BL are continuous in a direction crossing each other, and source lines SL are connected to source lines SL of all memory cells in the block. Are connected in common. Therefore, as described later, the independent bit line BL for each block becomes a local bit line, which is selectively connected to a higher-order main bit line.

The operation of the memory cell MC is as follows. Data writing is performed on the p-type well 22 and the source line S
L is set to 0 V, a write potential of about 10 V is applied to the selected word line WL, and data “0” and “1” are applied to the bit line BL.
6V and 0V are applied according to In a memory cell to which “0” data is given, hot electrons are generated by a strong lateral electric field between the drain and the source, and injected into the floating gate 24. In the case of "1" data, such electron injection does not occur.

As a result, a state in which electrons are injected into the floating gate to increase the threshold value is "0". In the case of "1" data, no hot electrons are generated, and therefore no electrons are injected into the floating gate, and the erased state, that is, the "1" data state with a low threshold is maintained.

In data erasing, batch erasing is performed in block units. At this time, 10 V is applied to the p-type well 22 and the source line SL of the selected block together with the n-type well 21.
And a voltage of about -7 V is applied to all the word lines WL in the selected block. As a result, a large electric field is applied to the gate insulating film 23 of the memory cell in the block, and electrons of the floating gate are emitted by the Fowler-Noldheim current (tunnel current), so that the data "1" is erased.

In data reading, a read voltage set to an intermediate value between threshold values of data "0" and "1" is applied to a selected word line, and the presence / absence of current drawing of a memory cell is connected to a bit line. Judge by the sense amplifier.

FIG. 4 shows the configuration of the column decoder 3 and the column gate 4. As described above, the number of the bit lines BL for each block BLKi, BLKi + 1,... Of the memory cell array 1 is, for example, four, and the main bit lines MBL0, MBL1,. ... are selectively connected. The column decoder 3 has a first column decode circuit CD1 for selecting a bit line of each block and a second column decode circuit CD2 for selecting a main bit line.

The column gate transistors QN0 to QN3, QN4 to QN are output by first column selection lines Hi, Hi + 1,... Which are output lines of the first column decode circuit CD1.
The gates of 7,... Are controlled. A column gate transistor QN for selecting a main bit line by a second column selection line D which is an output line of the second column decode circuit CD2
, QN22,... Are controlled. As described above, the selected bit line BL of the selected block is connected to the main bit line MBL through the column gate transistors activated by the first column selection lines Hi, Hi + 1,..., And the main bit line MBL is connected to the second bit line. Is connected to the data line DL via the column gate transistor activated by the column selection line D.

FIG. 5 shows a main configuration of the sense amplifier circuit 5 connected to the data line DL. In this embodiment, in order to perform the page mode operation, the sense amplifier circuit 5 has one page (for example, one page = 8wo).
rds = 128 bits) are arranged, and it is a basic feature of this embodiment that a large number of these sense amplifiers are configured to share a reference potential generating circuit. FIG. 5 shows a configuration of one sense amplifier row 50 and a reference potential generation circuit 60 shared by each sense amplifier in the sense amplifier row 50.

Each sense amplifier body of the sense amplifier array 50 is a differential amplifier 51 in FIG.
Are connected to independent sense lines SN, and the other input terminals are commonly connected to a reference sense line RSN. Each sense line SN is a p-channel MISFET (hereinafter referred to as PMOS
It is connected to a power supply Vcc via a current source load 52 composed of a transistor QP1. Similarly, the reference sense line RSN is connected to a power supply Vcc via a current source load 61 including a PMOS transistor QP2 having a gate and a drain connected.
Connected to.

Each of the sense lines SN is an n-channel MISFET having a gate supplied with a predetermined bias BIAS.
A data line D is connected via a clamp circuit (separation circuit) 53 including a QN41 (hereinafter referred to as an NMOS transistor).
L. Similarly, the reference sense line RSN is connected to the reference data line DL via a clamp circuit 62 composed of an NMOS transistor QN42 having a gate supplied with a predetermined bias BIAS. These clamp circuits 5
The reference numerals 3 and 62 are provided for suppressing the potential amplitude of the data line DL and the reference data line RDL and increasing the potential amplitude of the sense line SN and the reference sense line RSN as in the related art.

The reference data line RDL is connected to a current source 63 for flowing an intermediate current between the data values of the "0" and "1" data of the memory cells MC connected to the data line DL. As described above, the data line DL has a large capacitance because it is connected to the bit line BL via the multi-stage column gate transistors. Therefore, the dummy data line capacitance CR is connected to the reference data line RDL so that the load capacitance is substantially the same as the capacitance of the data line DL. That is, the portion of the reference sense line RSN, the current source load 61 connected to the reference sense line RSN, and the reference data line RDL connected to the reference sense line RSN via the clamp circuit 62 are shared by the sense amplifier array 50 to generate the reference potential. The circuit 60 is constituted.

FIG. 6 shows another example of the configuration of the sense amplifier array 50 and the reference potential generating circuit 60. In this example, the sense amplifier body uses an inverter 51a. Since the sense amplifier itself is not a differential amplifier, the reference sense line RSN
And a current source load 52 connected to each sense line SN constitute a current mirror circuit. That is, the gate and the drain of the PMOS transistor QP2 of the current source load 61 are shared by the reference sense line R
The gate of the PMOS transistor QP1, which is connected to the SN and is the current source load of each sense amplifier body, is connected to the reference sense line RSN.

It should be noted that the differential amplifier 51 has the configuration shown in FIGS.
It can be configured as shown in FIG. FIG. 7 (a)
A pair of differential PMOS transistors QP21 and QP22;
This is an example in which one operational amplifier OP has a current mirror load by NMOS transistors QN31 and QN32. FIG. 7B shows a two-stage operational amplifier OP1,
This is an example using OP2. FIG. 7C shows an example in which two operational amplifiers OP11 and OP12 are provided in the input stage and an operational amplifier OP12 for obtaining a difference between these outputs is provided.

As the load 52, a resistor R may be used as shown in FIG. 8A, or a PMOS transistor QP1 whose gate is grounded may be used as shown in FIG. 8B. The clamp circuit 53 may have a configuration in which a bias voltage generation circuit 531 for driving the gate of the NMOS transistor QN41 is provided as shown in FIG. 9A, or an inverter 532 as shown in FIG.
, The potential of the data line DL may be fed back to control the gate of the NMOS transistor QN41. In this case, the bias voltage generation circuit 531 of the clamp circuit is preferably shared by the sense line SN and the reference sense line RSN. When shared, the noise on the bias voltage BIAS at the start of the sensing operation can be the same on the main body side and the reference side.

FIG. 11 shows the read operation timing in the page mode of the flash memory according to this embodiment. A page address Add is input, a memory cell is selected, the selected memory cell data is sensed, and the sensing result is latched in a page buffer. The internal operation so far requires a time of, for example, 100 ns in order to utilize the charging and discharging of the data line having a large load capacity connected to the main bit line and the local bit line. After the data for one page is latched in the page buffer, the addresses in the page are switched at high speed as a0, a1, a2,... And the corresponding data D0, D1, D2,. This intra-page access requires only about 25 ns, for example, since there is no charge / discharge of a large load capacity.

According to this embodiment, a reference potential generating circuit is not provided for each sense amplifier as in the prior art, and one reference potential generating circuit 60 is shared by a sense amplifier array 50 including a plurality of sense amplifiers. . Therefore, the number of the dummy data line capacitors CR requiring a large area (accordingly, the capacitance area) can be reduced, and the chip area of the flash memory can be reduced.

However, as described above, the sense amplifier array 50
Share the reference potential generating circuit 60, the reference sense line R
Since a plurality of sense amplifier bodies are connected to SN,
The capacity balance between the sense line SN and the reference sense line RSN is greatly disrupted. As described in the related art, in order to perform high-speed data sensing, it is important to balance the capacitance of the sense line SN and the reference sense line RSN as well as the capacitance of the data line DL and the reference data line RDL. .

In consideration of this point, preferably, a dummy sense line capacitance CS is added to each sense line SN as shown in FIG. As described above, in order to meet the capacity increase caused by connecting a plurality of sense amplifiers to the reference sense line RSN,
By intentionally increasing the capacitance of the sense line SN, the sense line S
N and the reference sense line RSN have substantially the same capacitance. The same applies to the case of the sense amplifier configuration of FIG.

The dummy sense line capacitance CS in FIG.
For example, as shown in FIG. 10, (the number of sense amplifiers-1) PMOS transistors having the same gate area as the gate area of the input-stage PMOS transistor of the differential amplifier 51 as the sense amplifier body may be provided. Similarly, the dummy sense line capacitance CS in the case of FIG.
It suffices to provide (the number of sense amplifiers-1) PMOS transistors having the same gate area as the S transistor.

As described above, by adding the dummy sense line capacitance to the sense line SN and balancing the capacitance with the reference sense line RSN, the sense amplifier array 50 shares the reference potential generating circuit 60. Can be accessed at high speed.

In the embodiments described above, a large number of sense amplifiers for one page are equally divided into, for example, eight sense amplifier rows, and one reference potential generating circuit is provided for each sense amplifier row. And However, in an actual flash memory, the sense amplifier group may not be equally divided. Typically, a flash memory adopts a redundant circuit system and a spare column data line (spare data line)
And a sense amplifier is provided for each spare data line.

In such a case, the sense amplifier arrays having different numbers of sense amplifiers coexist. That is, FIG.
As shown in FIG. 5, a first sense amplifier row 50A including m (m is an integer of 2 or more) sense amplifiers and n (n is
second sense amplifier having an integer of 2 or more smaller than m).
Are made to coexist. On the sense amplifier row 50A side, (m-1) PM
A dummy sense capacitor CS1 corresponding to an OS transistor is connected, and on the sense amplifier row 50B side, each sense line SN
The (n-1) dummy sense line capacitors CS2 corresponding to the PMOS transistors are connected.

More specifically, for example, the first sense amplifier train 5
0A is connected to each of m = 8 normal data lines DL, and the second sense amplifier row 50B is connected to n = 2 to n = 2.
Assume that they are connected to three spare data lines. In this way, in each of the sense amplifier arrays 50A and 50B, the capacitance balance between the reference sense line RSN and the sense line SN can be achieved.

By the way, in the configuration of FIG. 12, the dummy sense line capacitance CS1 of the first sense amplifier row 50A and the dummy sense line capacitance CS2 of the second sense amplifier row 50B are not balanced in each sense amplifier row. , CS1> CS2 corresponding to m> n.
Therefore, although the capacity is balanced in each of the sense amplifier arrays 50A and 50B, a difference occurs in the data line charging speed by each sense amplifier, and hence the sense speed.

In order not to cause such a difference in sense speed, it is desirable to match the capacity of the dummy sense lines connected to the sense lines SN of the two sense amplifier arrays 50A and 50B. For example, as shown in FIG.
And the second sense amplifier row 50B
On the side, another dummy sense line capacitance CS3 is connected to the sense line SN and the reference sense line RSN. At this time,
The relationship between the dummy sense line capacitances CS1, CS2 and CS3 between the first sense amplifier row 50A and CS1 = CS2
+ CS3.

In this manner, the second sense amplifier row 50
Even if the capacity balance in B is slightly broken, the sense line capacities of the first sense amplifier row 50A and the second sense amplifier row 50B are made uniform, and these sense amplifier rows 50A, 50B
By setting the data line charging rates to the same, high-speed sensing becomes possible.

By the way, in the configuration of FIG. 5, when a variation in the threshold value occurs due to a variation in the gate area between the PMOS transistors of the current source loads 52 and 61,
The sense speed is adversely affected. The variation of the threshold value is usually inversely proportional to the half power of the gate area. Specifically, if there is such a variation in the threshold value, the data cannot be determined unless there is a potential difference between the sense line SN and the reference sense line RSN that exceeds the difference in the threshold value (absolute value). Become slow.

On the other hand, in this embodiment, the gate areas of the current source loads 52 and 61 are made large, for example, larger than the gate area of the input-stage PMOS transistor of the differential amplifier 51, so that the variation in threshold voltage is reduced. It is effective to do. Usually, increasing the load size too much
As described with reference to FIG. 18, it is not preferable because the capacitance of the sense line is increased. However, in this embodiment, by sharing the reference sense line RSN, the capacity of the reference sense line RSN becomes several times larger than usual. The line capacitance is also large. Therefore, even if the gate areas of the current source loads 52 and 61 are increased, the effect on the sense line capacitance is small, and the effect of reducing the variation in the threshold value can be expected.

Similarly, in the case of the configuration shown in FIG.
It is effective to make the gate area of the 2,62 PMOS transistors larger than the gate area of the inverter 51a to reduce the influence of threshold variation.

In the present invention, since the capacitances of the sense line and the reference sense line are larger than those of the related art, it takes much time to charge the data line, that is, the bit line during sensing. On the other hand, it is effective to provide a circuit for accelerating data line charging. For example, as shown in FIG. 14, a charge accelerating NMOS is provided on the data line DL side of the clamp circuit 53.
One end of the transistor QN61 is connected. The other end of the NMOS transistor QN61 is connected to the power supply Vcc via the switch SW, and the gate of the NMOS transistor QN61 has the NMO
A bias BIAS similar to that of the S transistor QN41 is applied.

As described above, at the time of data sensing, the switch SW is turned on, and the charging operation of the data line DL can be accelerated using the NMOS transistor QN61 as an auxiliary current source. However, in this data line charging method, it is difficult to control the timing of the switch SW, and if the timing is shifted, the data line DL may be overcharged.

Therefore, in this embodiment, more preferably, as shown in FIG. 15, the charging transistor QP31 is connected to the sense line SN side of the clamp circuit 53. Here, the charge transistor QP31 is connected to the current source load 51.
Similarly, a PMOS transistor is diode-connected, and one end is connected to the power supply Vcc via the switch SW.

Thus, at the time of data sensing, the switch SW is turned on, and the charging operation of the sense line SN and the data line DL can be accelerated using the NMOS transistor QN61 as an auxiliary current source. In this case, even if there is a slight deviation in the timing of the switch SW, since the charging of the data line DL is limited by the clamp circuit 53, there is no possibility of overcharging of the data line. Also, the increase in the capacity of the sense line SN due to the provision of the charging PMOS transistor QP31 has little effect since the capacity is originally increased by adding the dummy sense line capacity CS.

The present invention is not limited to the above embodiment.
For example, in the above-described embodiment, the NOR type flash memory has been described. However, the present invention is similarly applied to various other semiconductor memories in which the memory cells are of a current draw type and use a current detection type sense amplifier. It is possible. Further, in the embodiment, the flash memory having the page mode is described. However, since a large number of sense amplifiers are similarly arranged in the burst mode, it is effective to apply the present invention. In this case, the data latched in the page buffer can be parallel / serial converted and output by providing a clock driven shift register. Furthermore, the present invention can be similarly applied to a semiconductor memory of a system in which a large number of sense amplifiers are arranged and a large number of data are transferred in parallel, even if the mode is not the page mode or the burst mode.

[0061]

As described above, according to the present invention, by using a sense amplifier circuit system in which a sense amplifier array including a plurality of sense amplifiers shares one reference potential generating circuit, the present invention provides a method for generating a reference potential. A semiconductor memory device in which the area of the dummy capacitor is reduced and the chip area is reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a flash memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a memory cell array of the flash memory.

FIG. 3 is a sectional view showing a memory cell structure of the flash memory.

FIG. 4 is a diagram showing an equivalent circuit of a column decoder and a column gate of the flash memory.

FIG. 5 is an equivalent circuit showing a configuration example of a main part of a sense amplifier circuit of the flash memory.

FIG. 6 is an equivalent circuit showing another configuration example of a main part of the sense amplifier circuit.

FIG. 7 is a diagram illustrating a configuration example of a differential amplifier in FIG. 5;

FIG. 8 is a diagram showing a configuration example of a current source load of FIG. 5;

FIG. 9 is a diagram illustrating a configuration example of a clamp circuit of FIG. 5;

FIG. 10 is a diagram showing a configuration example of a dummy sense line capacitance in FIG. 5;

FIG. 11 is a timing chart for explaining a read operation in a page mode according to the embodiment;

FIG. 12 is a diagram illustrating another configuration example of the sense amplifier circuit.

FIG. 13 is a diagram illustrating another configuration example of the sense amplifier circuit.

FIG. 14 is a diagram illustrating another configuration example of the sense amplifier circuit.

FIG. 15 is a diagram illustrating another configuration example of the sense amplifier circuit.

FIG. 16 is a diagram showing a configuration of a conventional sense amplifier circuit.

FIG. 17 is a diagram showing changes in potentials of a data line and a sense line during data sensing.

FIG. 18 is a diagram showing a relationship between a load size, a sense line capacity, and a data line charging speed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Column decoder, 4 ... Column gate, 5 ... Sense amplifier circuit,
6 page buffer, 7a, 7b data buffer, 8
... address buffer, 9 ... control circuit, 10 ... boost circuit, 11 ... source well decoder, 50, 50A,
50B: sense amplifier array, 60: reference potential generation circuit, 5
DESCRIPTION OF SYMBOLS 1 ... Differential amplifier, 51a ... Inverter, 52,61 ... Current source load, 53,62 ... Clamp circuit, 63 ... Current source
SN: sense line, RSN: reference sense line, DL: data line, RDL: reference data line, CS: dummy sense line capacitance, CR: dummy data line capacitance.

Claims (12)

[Claims] 1. A memory cell array in which memory cells for storing data according to presence or absence or magnitude of current draw are arranged, a plurality of data lines for transmitting and receiving data to and from the memory cell array, and respectively connected to the plurality of data lines. A sense amplifier row having a plurality of sense lines, and a reference data line for applying a reference potential to a reference sense line shared by the sense amplifier row. 2. The semiconductor memory device according to claim 1, further comprising a dummy sense line capacitor connected to each of said sense lines. 3. The sense amplifier array includes: a plurality of differential amplifiers each having a first input terminal connected to the sense line, and a second input terminal commonly connected to the reference sense line; 3. The semiconductor memory according to claim 1, further comprising: a plurality of first current source loads for supplying a current to a sense line; and a second current source load for supplying a current to the reference sense line. apparatus. 4. A sense amplifier array comprising: a plurality of inverters each having an input terminal connected to the sense line; and a first inverter having a gate and a drain commonly connected for supplying current to the reference sense line. A current source MISFET; and a plurality of second current sources forming a current mirror with the first current source MISFET for supplying a current to each of the sense lines.
3. The semiconductor memory device according to claim 1, further comprising a current source MISFET. 5. The sense line is connected to a corresponding data line via a first separation circuit, and the reference sense line is connected to a reference data line via a second separation circuit. 3. The semiconductor memory device according to claim 1, wherein: 6. A first sense amplifier row including m (m is an integer of 2 or more) sense amplifier rows and n (n is an integer of 2 or more smaller than m) sense amplifier rows. 2. The semiconductor memory device according to claim 1, further comprising a second sense amplifier row including an amplifier. 7. A first dummy sense line capacitor is connected to each sense line of the first sense amplifier column, and a second dummy sense line capacitor is connected to each sense line of the second sense amplifier column. 7. The semiconductor memory device according to claim 6, wherein: 8. The semiconductor memory device according to claim 7, wherein a third dummy sense line capacitance is connected to each of the sense lines and the reference sense lines of the second sense amplifier row. 9. The method according to claim 1, wherein the first and second current source loads are MIS.
4. The FET according to claim 3, wherein the gate area of each of the MISFETs is set larger than the gate area of the input-stage MISFET of the differential amplifier.
The semiconductor memory device according to claim 1. 10. The first and second current sources MISFE
5. The semiconductor memory device according to claim 4, wherein a gate area of T is set larger than a gate area of said inverter. 11. The semiconductor memory device according to claim 1, wherein a sense line charge acceleration circuit for accelerating the charge of the sense lines is connected to each of the sense lines. 12. The semiconductor memory according to claim 1, wherein the memory cell is an electrically rewritable nonvolatile memory cell having a MISFET structure in which a charge storage layer and a control gate are stacked. apparatus.