JP2000200494A - Reading out circuit of multi-level memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high-speed and highly accurate memory readout by simplifying read-out sequence of a multi-level memory and enabling highly accurate memory read-out of one cycle. SOLUTION: When data length is (m), reference circuits 29-31 setting respective reference voltage values are provided commonly between each voltaqe level of plural voltage levels for memory cells 21, 25 of a (m) system which can hold plural voltage levels, and comparing circuits 32-37 of (m) systems performing en bloc comparison of magnitude between each reference voltage and voltage levels read out from the memory cells 21. 25 are prepared. A compared result of amplitude by the comparing circuit is decoded by selection circuits 38, 39, and a value of accumulated voltage level is outputted by expression of binary. Amplitude comparison between each voltage level and reference voltage prepared so that each voltage level of a memory cell can be detected can be performed en bloc. a voltage level of a memory cell can be specified by a compared result, and high speed and highly accurate multi-level memory can be read out by the compared result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit for a memory cell, and more particularly, to a multi-level voltage level (hereinafter referred to as V).
A multi-valued memory having a T value) and reading multi-valued memory cells for storing multi-valued logical values by batch reading that does not require a complicated reading sequence, thereby enabling high-speed and high-precision access. In the readout circuit.

[0002]

2. Description of the Related Art A conventional read circuit of a multilevel memory will be described below.

As an example, four VT values (VT1 to VT4)
A read circuit of a memory cell having the following will be described. In the read processing of the memory cell having the four VT values, according to the conventional multi-level memory read circuit, the four VT values cannot be detected unless the comparison processing (reference processing) with the reference voltage is performed twice. there were. FIG. 6 is a table showing this relationship. As shown in FIG. 6, the four VT values can be represented by two bits, and if the upper bit D1 and the lower bit D2 are obtained, the VT value can be detected. Here, the process of determining the upper bit D1 is referred to as a first reference process, and the process of determining the lower bit D2 is referred to as a second reference process.

FIG. 8 shows a read circuit configuration of a conventional multilevel memory. 8, reference numeral 80 denotes a memory cell; 81, a switching element for selecting the memory cell 80; 82, a limit circuit for keeping a drain voltage of the memory cell constant; 83, a current-voltage conversion circuit for converting a current value to a voltage value , 84 are comparison circuits, and 85 and 87 are flip-flops (hereinafter abbreviated as FFs).
Inputs and latches the output of the comparison circuit 84 at the timing of a first reference process (described later) as a control signal, outputs the D1 signal, and outputs the D1 signal to the reference circuit 86 as well. The FF 87 receives and latches the output of the comparison circuit 84 at the timing (described later) of a second reference process, which is a control signal, and outputs a D2 signal. Reference numeral 86 denotes a reference circuit for generating a reference voltage for determining the VT value of the memory cell.
A selection signal S (in this example, high means the first reference processing and low means the second reference processing) specifying the reference processing or the second reference processing and the D1 signal from the FF 85 are input, One of three reference voltages Vref1 to Vref3 is generated according to the input.

[0005] The operation of the read circuit of the conventional multi-valued memory configured as described above will be described.

First, at the timing of the first reference processing shown in FIG. 9, the selection signal S of the reference circuit 86 is set to high. The reference circuit 86 has Vre as shown in FIG.
f1 is output to the comparator 84 as a reference voltage value. Comparator 8
4 compares the reference voltage Vref1 with the read voltage Vout from the current-voltage conversion circuit 83. As a result of the comparison, if the read voltage Vout is higher, D1 = "1" is output, and if the read voltage Vout is lower, D1 = "0" is output.

When D1 = "1", the read voltage Vout becomes either VT3 or VT4, as is apparent from FIG. When D1 = "0", the read voltage Vout is either VT1 or VT2, as is apparent from FIG.

Next, at the timing of the second reference processing shown in FIG. 9, the selection signal S of the reference circuit 86 is set to low. When D1 = "1", the reference circuit 86 uses the Vref3 as shown in FIG.
Output to The difference amplifier 84 compares the reference voltage Vref3 with the read voltage Vout from the current-voltage conversion circuit 83. As a result of the comparison, if the read voltage Vout is higher, D2 = "1" is output, and if the read voltage Vout is lower, D2 = "0" is output. That is, D1 =
If "1" and D2 = "1", Vout can be detected as VT4, and if D1 = "1" and D2 = "0", Vout is VT
3 can be detected. When D1 = "0", the second reference process is performed in the same manner, and it is possible to detect whether Vout is VT1 or VT2 by comparison with the reference voltage Vref2.

[0009]

However, in the conventional multi-valued memory readout circuit, since a plurality of reference processes (the first reference process and the second reference process in the conventional example) are required, the memory read time is reduced. It has a problem that it is slow and the reading sequence is complicated.

Furthermore, since a resistor is used to generate the reference voltage, the accuracy of the reference voltage value generally deteriorates due to the large variation accuracy of the resistance value. As a result, the memory reading accuracy deteriorates. Had occurred. With the demand for lower power consumption, high-precision reading is required to keep the storage voltage of a memory cell as low as possible and to increase the number of levels.

The present invention solves the above-mentioned conventional problems, and simplifies a read sequence, enables one-cycle high-precision reading, and realizes high-speed memory access and high-precision memory reading. Aim.

[0012]

In order to achieve the above object, a read circuit of a multi-valued memory according to the present invention has a plurality of voltage levels that can be held in a memory cell and reads out a multi-valued memory cell that stores multi-valued logic. A reference circuit for setting respective reference voltage values between the respective voltage levels of the plurality of voltage levels; and a reference voltage supplied by the reference circuit and a voltage level read from the memory cell. A comparison circuit that collectively performs the magnitude comparison of the memory cells, and detects which reference voltage value the storage voltage level of the memory cell is between based on the magnitude comparison result of the comparison circuit, and stores the storage logic of the memory cell. An output circuit for outputting a value is provided.

With the above configuration, the voltage level of the memory cell can be collectively compared in one cycle with the reference voltage prepared so that each level can be detected, and the voltage level of the memory cell can be specified based on the result of the comparison. Thus, high-speed and high-precision multi-valued memory reading can be realized.

Next, the output circuit receives, as an input, a magnitude comparison result output between the storage voltage level of the memory cell and each reference voltage value obtained from the comparison circuit, and represents a corresponding multi-valued logical value. It is preferable to encode the bits and output the bits in hexadecimal notation.

According to the above configuration, the detected voltage level of the memory cell can be read out as a binary code which is a multi-valued logical value.

Next, the memory cell is accessed in units of a data length m, and the memory cell, the comparison circuit, and the output circuit are provided in m systems, and one reference circuit common to each system is provided. Preferably, it is provided.

According to the above configuration, multi-valued logic can be read from memory cells collectively in units of data length, and high-speed and high-precision access to the multi-valued memory is made possible. Further, in order to use the reference circuit in common, one reference circuit is sufficient for the reading of m systems,
An increase in circuit scale can be suppressed.

Next, the reference circuit holds a reference voltage for holding a reference voltage, a write control circuit for giving a reference voltage to the reference voltage holding unit, and reads and writes the reference voltage of the reference voltage holding unit. It is preferable that a write voltage confirmation unit that feeds back to a control circuit is provided, and the write control circuit adjusts the feedback write voltage so as to match a reference voltage.

With the above configuration, a highly accurate reference voltage can be obtained, and the voltage levels of the read memory cells can be compared with high accuracy. As the potential difference between the storage voltage levels due to lower power consumption and further multi-valued memory cells becomes smaller, a more accurate reference voltage is required. According to the above configuration, a more accurate reference voltage supply is possible. Becomes

Next, the write control circuit may also write the electric charge to the memory cell, and the write control circuit for the memory cell and the write circuit for the reference voltage holding unit of the reference circuit may be shared. preferable.

With the above configuration, the circuit for writing the VT value to the memory cell of the reference circuit unit and the circuit for writing the VT value to the memory cell for storing data can be shared, and the circuit configuration is simplified. At the same time, it is possible to suppress variations in the write performance due to variations in the manufacturing of the write circuit and improve the accuracy.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, a read circuit of a multilevel memory according to Embodiment 1 of the present invention will be described with reference to the drawings. In the first embodiment, three memory cells are used.
The charge stored in the nonvolatile memory cell having the VT values VT1 to VTn at the above voltage levels is read, and
This is a circuit that reads the T value accurately and at high speed. The basic principle is that n VT values (VT1 to V
Tn), reference voltages which are intermediate values of the VT values of the respective levels (that is, n-1 reference voltages) are prepared, and corresponding comparison circuits (here, n-1 independent comparison circuits are provided). Prepare), and compare the sizes at once.
The VT value detected and determined based on the result is output in binary notation.

In the first embodiment, as an example, it is assumed that a memory cell has four VT values. As shown in FIG.
One VT value can be represented by 2 bits, and VT1 is “00”,
VT2 is “01”, VT3 is “10”, and VT4 is “1”.
The upper bit is defined as D1 and the lower bit is defined as D2. By specifying the upper bit D1 and the lower bit D2, the VT value is read in a 2-bit expression.

VT1 to VT4 and reference voltages Vref1, Vref
2, the relationship between Vref3 is as shown in FIG. The upper bit D1 is determined by a comparison result between the read voltage Vout and the first reference voltage Vref1, and the lower bit D2 is a comparison between the read voltage Vout and the second reference voltage Vref2, or the read voltage Vout and the third reference voltage Vref2. Is compared with the reference voltage Vref3.

FIG. 1 shows an example of a circuit configuration of a read circuit of a multilevel memory according to Embodiment 1 of the present invention. In FIG. 1, 101 is a memory cell unit, 1 is a memory cell for data storage, 2 is a switching element for selecting a memory cell array for data storage, 3 is a limit circuit for keeping a drain voltage of the memory cell 1 for data storage constant, Reference numeral 4 denotes a transistor element as a current-voltage conversion circuit for converting the current of the data storage memory cell 1 into a voltage, 5 a first reference circuit for generating a first reference voltage Vref1, and 6 a second reference circuit. A second reference circuit for generating the reference voltage Vref2, and a third reference circuit 7 for generating the third reference voltage Vref3.

Reference numeral 8 denotes a first comparison circuit for comparing the first reference voltage Vref1 with the read voltage Vout of the data storage memory cell 1, and its output is D1. Reference numeral 9 denotes a second comparison circuit for comparing the second reference voltage Vref2 with the read voltage Vout of the data storage memory cell 1, and reference numeral 9 denotes a third reference voltage Vref3 and the read voltage V of the data storage memory cell 1.
13 is a third comparison circuit that compares out.

An input 11 receives the output D1 of the first comparison circuit 8, the output of the second comparison circuit 9, and the output of the third comparison circuit 10, and outputs the output of the second comparison circuit 9 and the third Comparison circuit 1
This is a selection circuit that selects one of the outputs of 0 based on the result of the output D1 and outputs it as D2. 14 is a gate control signal of the data storage memory cell 1, and 15 is a selection control signal of a selection element for selecting the data storage memory cell array.

FIG. 2 shows an example of the configuration of reference circuits 5 to 7 in the multi-level memory read circuit of FIG.
Reference numeral 6 denotes a memory cell for determining a reference potential, and its VT value has a value corresponding to the reference potential set by the reference circuit. Reference numeral 17 denotes a limit circuit for keeping the drain voltage of the memory cell 16 constant, 18 a current-voltage conversion element for converting the current of the memory cell 16 into a voltage, 19 a gate control signal for the memory cell 16, and 20 a reference potential. .

The operation of the read circuit of the multi-valued memory configured as described above will be described below.

The charge stored in the data storage memory cell 1 is output via the switching element 2 based on the control signal 14 and the selection control signal 15. An output voltage Vout is output by the limiter circuit 3 and the transistor element 4 which is a current-voltage conversion circuit. Here, since the transistor element 4 is used as the current-voltage conversion circuit, the accuracy of variation can be increased. Further, if the semiconductor device is manufactured in the same semiconductor manufacturing process as the memory cell 1 for data storage, the same manufacturing variation is included. And the likelihood of offsetting manufacturing variations increases.

The output voltage Vout is input to the first comparing circuit 8, the second comparing circuit 9, and the third comparing circuit 10, and the reference comparison is independently and collectively performed at one time by each of the comparing circuits. Done.

That is, the output voltage Vout is compared with the first reference voltage Vref1 in the first comparison circuit 8, and if the output voltage Vout is higher than the first reference voltage Vref1, D1
= “1”, and the output voltage Vout is equal to the first reference voltage Vr.
If it is smaller than ef1, D1 = "0" is output.

In the second comparison circuit 9, the output voltage Vout
Is compared with the second reference voltage Vref2. When the output voltage Vout is higher than the second reference voltage Vref2, D2 ′ =
“1” is output, and the output voltage Vout becomes the second reference voltage Vref.
If it is smaller than 2, D2 '= "0" is output.

In the third comparison circuit 10, the output voltage Vou
t is compared with the third reference voltage Vref3. If the output voltage Vout is higher than the third reference voltage Vref3, D2 ″ =
“1” is output, and the output voltage Vout becomes the third reference voltage Vref.
If it is smaller than 3, D2 "=" 0 "is output.

By the comparison processing of the three independent comparison circuits, the comparison processing itself has been completed at a time, and D1 can be uniquely extracted by the output of the first comparison circuit 8, while D2 can be extracted by the output of the second comparison circuit. Either the comparison result or the third comparison result, whichever is valid, must be selected and determined as D2. Which is effective is determined according to the value of D1. The selection circuit 11 receives D1, D2 ′ and D2 ″ as inputs and D1 =
If "1", the output D2 of the third comparison circuit 10 is selected and output as D2. If D1 = "0", the output D2 'of the second comparison circuit 9 is selected and output as D2. A valid comparison result can be immediately selected and a correct D2 value can be output by the selection circuit 11. For example, when the output voltage Vout is VT3, D1 = from FIG.
Although "1" and D2 = "0", the output of the circuit configuration of FIG.
D1 = "1" is output, and the output voltage Vout <Vref3, and D2 "= D2 =" 0 "is output in the third comparison circuit 10 selected as valid by the selection circuit 11. Then, the output voltage Vout is correctly detected as VT3 and read.

As described above, according to the read circuit of the multi-level memory of the first embodiment, each of the memory cells can be used for the non-volatile memory cells having three or more multi-level VT values (VT1 to VTn). A reference voltage (that is, n-1 reference voltages) which is an intermediate value between the VT values of each level is prepared, and the corresponding comparison circuits (n-1 comparison circuits) simultaneously perform the magnitude comparison simultaneously. Then, the VT value detected and determined based on the result can be output in binary notation, and the value of the memory can be read and detected at high speed and with high accuracy.

(Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described.
Will be described with reference to the drawings. In the second embodiment, the memory cell has three or more V
The stored charges of the nonvolatile memory cells having the T values VT1 to VTn are collectively read by the data length, and the VT of each memory cell is read.
This is a circuit that detects values and collectively reads out the data lengths accurately and at high speed. Although the basic principle of reading the VT value of each memory cell is applied to the first embodiment, a reference circuit for generating a reference voltage for comparison with the read voltage Vout of each memory cell is commonly used for each read data length unit. The circuit is simplified and the number of circuits is reduced. As an example, assume that the data length is m as a data read unit. That is, in the second embodiment, an example will be described in which m memory cells are read at a time, and the VT value of each memory cell is detected and read.

In the second embodiment, as in the first embodiment, the memory cell has four VT values, and each of the VT values VT1 to VT
Reference numeral 4 denotes a 2-bit expression as shown in FIG. 6, in which the upper bit is D1 and the lower bit is D2. In the second embodiment, since the VT values of the memory cell units 1 to m are read out as described later, for convenience of explanation, for example, the upper bits of the VT value of the memory cell unit P in binary notation are D (p) 1 , And the lower bits are expressed with an argument such as D (p) 2.

VT1 to VT4 and reference voltages Vref1, Vref
2, the relationship between Vref3 is the same as in the first embodiment, as shown in FIG.
The lower bit D2 is determined by the comparison result between the read voltage Vout and the second reference voltage Vref1.
2 or the comparison result between the read voltage Vout and the third reference voltage Vref3.

FIG. 3 shows a circuit example of a read circuit of a multilevel memory according to the second embodiment of the present invention. In FIG. 3, reference numeral 21 denotes a first data storage memory cell of the data length m, reference numeral 22 denotes a switching element for selecting the data storage memory cell 21, and reference numeral 23 denotes a constant drain voltage of the data storage memory cell 21. The limit circuit 24 is a transistor element which is a current-voltage conversion circuit for converting the current of the memory cell 21 into a voltage. The first memory unit 111 is constituted by the above-mentioned data storage memory cells 21 to 24. The output is Vout1. 25 is an m-th data storage memory cell of the data length m, 26 is a data storage memory cell 2
5, a switching element for selecting 5, a limit circuit 27 for keeping the drain voltage of the data storage memory cell 25 constant, and a current-voltage conversion circuit 28 for converting the current of the data storage memory cell 25 into a voltage. A transistor element, and the m-th memory unit 112
And its output is Voutm. Although not shown, the same applies to the (m-1) th memory unit of the (m-1) th data storage memory cell from the second memory unit of the second data storage memory cell of the data length m. And Vout2 to Vout (m-1) are respectively output.

Reference numerals 29 to 31 denote reference circuits.
Reference numeral 9 denotes a first reference circuit for generating a first reference voltage Vref1, reference numeral 30 denotes a second reference circuit for generating a second reference voltage Vref2, and reference numeral 31 denotes a third reference voltage Vref3. Is a third reference circuit.

Reference numerals 32 to 34 denote comparison circuits for the output Vout0 of the first memory unit, and 32 denotes a first memory unit 11 which is a voltage value of the memory cell 21 for data storage.
1 and the reference voltage Vref of the reference circuit 29.
A comparison circuit 33 compares the output Vout0 of the first memory unit 111 with the reference voltage of the reference circuit 30.
A comparison circuit for comparing Vref2 is a comparison circuit for comparing the output Vout0 of the first memory unit 111 with the reference voltage Vref3 of the reference circuit 31. Similarly, 35-3
7 is a comparison circuit unit for the output Voutm of the m-th memory unit 112, 35 is a comparison circuit for comparing Voutm which is the voltage value of the memory cell 25 for data storage with the reference voltage Vref1 of the reference circuit 29, and 36 is an output Vout
Reference numeral 37 denotes a comparison circuit for comparing the output Voutm with the reference voltage Vref3 of the reference circuit 31. Although not shown, it is assumed that comparison circuit units for the second to (m-1) th memory units are also configured. The configuration of the reference circuits 29 to 31 is the same as the reference circuit of FIG. 2 described in the first embodiment.

Reference numeral 38 denotes the selection circuit 11 described in the first embodiment.
Is a selection circuit similar to. 2 of the VT value of the memory cell 21
D which is the output 40 of the comparison circuit 32
(1) A circuit for selecting one of the outputs of the comparison circuit 33 or 34 which is valid in response to the result of 1;
Lower bit D (1) 2 of the binary number of the VT value of memory cell 21
Is output. Similarly, reference numeral 39 denotes the upper bit of the binary number of the VT value of the memory cell 25, which is valid among the outputs of the comparison circuit 36 or 37 in response to the result of D (m) 1, which is the output 42 of the comparison circuit 35. This is a selection circuit for selecting one of them, and outputs an output 43 which is the lower bit D (m) 2 of the binary number of the VT value of the memory cell 25. In addition,
Although not shown, selection circuits corresponding to the second memory unit to the (m-1) th memory unit are also provided, respectively, and the upper bit and the lower bit (D) of the VT value of each memory cell in the binary number representation are provided. (2) 1, D (2)
2) to (D (m-1) 1, D (m-1) 2) are correctly output.

44 is a gate control signal for the data storage memory cell 21, 45 is a selection signal for the switching element 22,
46 is a gate control signal for the data storage memory cell 25,
47 is a selection signal for the switching element 26.

The above is an example of the circuit configuration of the second embodiment.
The read circuits of the m systems corresponding to the respective data lines having the data length m can share the same reference voltage, so that the reference circuits are shared and only one set is provided.

Next, an outline of the operation of the read circuit of the multi-valued memory configured as described above will be described. First,
The m first to m-th memory cell units, which are data length units, are simultaneously and independently read collectively, and output Vout1 to Voutm, respectively. Next, the respective outputs Vout1 to Voutm are input to the corresponding first to mth comparison circuit units, and the three reference voltages Vref1 and Vref
2, compared with Vref3, and as in the first embodiment, as a comparison result and a selection result by the selection circuit, the binary representation of the VT value of the memory cell (D (1) 1, D (1) 2) to (D (m ) 1, D (m)
2) is obtained correctly.

As described above, according to the second embodiment, when the data length is m, data reading can be executed collectively in the m multi-value memories, and the multi-valued VT value can be increased. It can be detected with high accuracy. Further, the comparison circuit and the selection circuit require m systems, but since the reference circuit is shared by one, the circuit scale can be suppressed.

(Embodiment 3) Hereinafter, Embodiment 3 of the present invention will be described.
Will be described with reference to the drawings. In the third embodiment, the reference voltage memory cell included in the reference circuit is provided with a write circuit, thereby improving the voltage accuracy of the reference voltage and enabling accurate reading even when the quantization width of the VT value is small. Things. The memory cell unit, the comparison circuit unit, the selection circuit, and the like may be the same as those in the first and second embodiments, and the description will focus on the reference circuit. Also, in the third embodiment, the memory cell has four VT values as in the first embodiment.
The values VT1 to VT4 are expressed in two bits as shown in FIG. 6, where the upper bit is D1 and the lower bit is D2.

FIG. 4 shows an example of a reference circuit configuration of a read circuit of a multilevel memory according to the third embodiment of the present invention. Here, an example in which the reference potential Vrefn is obtained as the n-th reference circuit unit 121 will be described.
In FIG. 4, reference numeral 51 denotes a memory cell for determining a reference potential, the VT value of which is the reference potential VTn. 52 is a limit circuit for keeping the drain voltage of the memory cell 51 constant,
Reference numeral 53 denotes a current-voltage conversion element for converting the current of the memory cell 51 into a voltage. 122 is a writing circuit,
54 is a write control circuit for controlling the VT value of the memory cell 51, 55 is a switching element for directly measuring the VT value of the written memory cell 51 from outside as write voltage confirmation means, and 56 is a switching element 5
5 is a control signal, 57 is a control signal for controlling writing, and 58 is a power supply for applying a writing potential.
The write control circuit 54 has a function of adjusting a write voltage by feeding back a signal from the switching element 55 as a write voltage confirmation unit.

59 is a gate control signal for the memory cell 51,
Reference numeral 60 denotes a reference potential Vrefn, and reference numeral 49 denotes a VT value confirmation read output signal of the memory cell 51.

As described above, in order to set the VT value of the memory cell 51 of the reference circuit unit 121 to a target value, a high-accuracy write circuit 122 is provided for the reference circuit unit 121.

The operation of the read circuit of the multi-valued memory configured as described above will be described.

In the initial state, it is assumed that the VT value of the memory cell 51 of the reference circuit unit 121 is not set correctly in the initial state. The write control circuit 54 of the write circuit 122 applies a voltage to the memory cell 51 via the write potential power supply 58 in accordance with the control signal 57, and performs writing so that the VT value of the memory cell 51 becomes a correct value. Next, the switching element 55 is turned on by the control signal 56, the VTn of the memory cell 51 is directly read, and the value of VTn is checked to confirm whether the correct VT value is written. As a result of the confirmation, if the VT value is not correctly written, feedback is made to the write control circuit 54 to adjust the write voltage.

By the above operation, for example, four values of VT1
Reference potentials VVref1, Vref2, V for determining VT4
ref3 can be set with high accuracy.

As described above, according to the fourth embodiment, the write circuit is provided corresponding to the reference circuit unit, the VT value of the memory cell of the reference circuit unit is accurately written, and the write value is directly measured. By determining whether the value is correct or not and performing feedback adjustment as necessary, the accuracy of the reference potential can be improved, and the accuracy of reading can be further improved.

(Embodiment 4) Hereinafter, Embodiment 4 of the present invention will be described.
Will be described with reference to the drawings. Embodiment 4
Is a circuit for writing a VT value to a memory cell of a reference circuit unit and a VT value for a memory cell for storing data.
By sharing the value writing circuit, the configuration of the circuit is simplified, and the variation in the writing performance due to the variation in the manufacturing of the writing circuit is suppressed, and the accuracy is improved.

FIG. 5 shows a circuit configuration of a read circuit of a multilevel memory according to the fourth embodiment of the present invention. FIG.
, 131 is a memory cell unit, 61 is a memory cell for storing data, 62 is a switching element for selecting the memory cell 61, 63 is a limit circuit for keeping the drain voltage of the memory cell 61 constant, and 64 is a memory cell It is a current-voltage conversion element for converting the current of 61 into a voltage. 132 is a reference circuit unit;
5 is a memory cell for determining a reference voltage,
T value is VTn corresponding to the reference voltage to be set,
77 is a switching element for selecting the memory cell 65, 78 is a control signal for the switching element 77, 66 is a limit circuit for keeping the drain voltage of the memory cell 65 constant, and 67 is a conversion circuit for converting the current of the memory cell to a voltage. It is a current-voltage conversion element. 133 is a write circuit,
68 is a write control circuit, 69 is a switching element as write voltage confirmation means for directly measuring the write VT values of the memory cells 61 and 65 from outside, and 76 is a power supply for applying a write potential.

Reference numeral 70 denotes a memory cell 61 for storing data.
Is a control signal of the switching element 62, 72 is a gate control signal of the memory cell 65, 73
Is a control signal for the switching element 69, 75 is a control signal for controlling writing, and 78 is a switching signal 77.
, 79 is the read potential, 80 is the reference potential, 7
Reference numeral 4 denotes an output signal for directly measuring the write VT values of the memory cells 61 and 65.

As described above, the write circuit 133 writes the VT value to the memory cell of the reference circuit unit and the VT to the memory cell for storing data.
A circuit for writing a value is shared.

The operation of the read circuit of the multi-valued memory configured as described above will be described.

It is assumed that the VT value of the memory cell 65 of the reference circuit unit 132 is not set correctly in the initial state. Writing is performed using the writing circuit 133 for setting the target VT so that the target VT value is obtained. Since the write circuit 133 is shared with the write circuit for the data storage memory cell 61, the influence of the variation in the write performance due to the variation in the circuit components affects the write operation to the memory cell unit 131 and the write operation to the reference circuit 132. It is canceled at the time of writing, which leads to improvement of reading performance.

As described above, according to the fourth embodiment, the circuit for writing the VT value to the memory cell of the reference circuit unit and the circuit for writing the VT value to the memory cell for storing data are shared, It is possible to simplify the circuit configuration, suppress variations in write performance due to variations in manufacturing of the write circuit, and improve accuracy.

[0063]

According to the read circuit of the multilevel memory of the present invention, each memory cell has three or more multilevel VT values (VT).
1 to VTn), the reference voltage (that is, n−1) which is an intermediate value between the VT values of each level.
Reference voltages), and the corresponding comparison circuits (n-1 comparison circuits) simultaneously perform the magnitude comparison simultaneously, and output the VT value detected and determined based on the result in binary notation. It is possible to read and detect the value of the memory at high speed and with high accuracy.

Further, according to the read circuit of the multi-level memory of the present invention, when the data length is m, the data read can be collectively executed by the m multi-level memories and the multi-level VT The value can be detected with high accuracy. Further, the comparison circuit and the selection circuit require m systems, but since the reference circuit is shared by one, the circuit scale can be suppressed.

Further, according to the read circuit of the multi-level memory of the present invention, a highly accurate reference potential can be set by the VT value write control circuit for the reference potential setting memory cell of the reference circuit, and the highly accurate read can be performed. Operation becomes possible.

Further, according to the read circuit of the multilevel memory of the present invention, the circuit for writing the VT value to the memory cell of the reference circuit unit and the circuit for writing the VT value to the memory cell for storing data are shared. Thus, the configuration of the circuit can be simplified, and the variation in the write performance due to the variation in the manufacture of the write circuit can be suppressed, and the accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration example of a read circuit of a multilevel memory according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a configuration example of reference circuits 5 to 7 in the multi-level memory read circuit of FIG.

FIG. 3 is a diagram illustrating a circuit configuration example of a read circuit of a multilevel memory according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a reference circuit configuration example of a read circuit of a multilevel memory according to a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit configuration of a read circuit of a multilevel memory according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between a multi-valued VT value and a 2-bit representation of a logical value according to the present invention.

FIG. 7 is a diagram showing a relationship between a VT value and a reference voltage of the multi-level memory of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a conventional read circuit of a multilevel memory.

FIG. 9 is a timing chart of a conventional read circuit of a multilevel memory.

[Explanation of symbols]

1,21,25,61 Memory cell for data storage 2,22,26,55,62,69,77 Switching element 3,17,23,27,52,63,66 Limit circuit 4,24,28,53, 64, 67 Current-voltage conversion element 5, 29 First reference circuit 6, 30 Second reference circuit 7, 31 Third reference circuit 8, 32, 35 First comparison circuit 9, 33, 36 Second comparison Circuits 10, 33, 37 Third comparison circuit 11, 38, 39 Selection circuit 12, 40, 42 Upper bit D1 13, 41, 43 Lower bit D2 14, 19, 44, 46, 59, 70, 72 Gate control signal 15, 45, 47, 71, 73, 78 Selection control signal 16, 51, 65 Reference voltage memory cell 20, 60, 79 Reference potential 55 Memory written Measuring terminals for selecting elements 57 write control signals 58 and 75 write power supply 60 to the outside VT Le direct the measurement for measuring the VT of the reference potential 68 write circuit 74 memory cells directly

Claims (5)

[Claims] 1. A read circuit for a multi-valued memory cell having a plurality of voltage levels that can be held by a memory cell and storing a multi-valued logic, wherein a reference voltage value is set between each of the plurality of voltage levels. A reference circuit to be set; a comparison circuit that collectively performs a magnitude comparison between each reference voltage supplied by the reference circuit and a voltage level read from the memory cell; and a comparison circuit based on a magnitude comparison result of the comparison circuit. An output circuit for detecting which reference voltage value the storage voltage level of the memory cell is between and outputting a storage logic value of the memory cell. 2. A binary number representing a corresponding multi-valued logic value, wherein said output circuit receives a magnitude comparison result output between a storage voltage level of said memory cell and a respective reference voltage value obtained from said comparison circuit as an input. 2. The read circuit of a multi-valued memory according to claim 1, wherein the readout circuit encodes and outputs the expression bits. 3. The memory cell is accessed in units of a data length m, the memory cell, the comparison circuit, and the output circuit are provided in m systems, and one reference circuit common to each system is provided. 2. The read circuit of a multi-level memory according to claim 1, wherein: 4. A reference voltage holding section for holding a reference voltage, a write control circuit for applying a reference voltage to the reference voltage holding section, and a write control circuit for reading the reference voltage of the reference voltage holding section. 2. The read circuit of a multi-valued memory according to claim 1, further comprising: a write voltage confirmation unit that feeds back to the circuit, wherein the write control circuit adjusts the fed back write voltage to be equal to a reference voltage. 5. The write control circuit also writes a charge into the memory cell, and a write control circuit to the memory cell and a write circuit to a reference voltage holding unit of the reference circuit are shared. 3. The read circuit of a multi-valued memory according to claim 1.