KR20030023349A - Flash memory apparatus for multilevel and singlelevel program/read - Google Patents

Abstract

PURPOSE: A flash memory compatible for programming and a reading multi level and a single level is provided to selectively utilize as a multi bit or a single bit flash memory in response to the specification of the system by utilizing the multi level when the capacity of the memory is large enough and by utilizing the single level when the memory program/read speed is relatively high. CONSTITUTION: A flash memory compatible for programming and a reading multi level and a single level includes a high voltage generation block(2) for generating a voltage required for programming/reading the flash memory, a first data buffer block(3), a second data buffer block(4), a sense amplifier block(5) controlled by a program/read control sequence block(1) for outputting the current values of the cell to the first and the second data buffer blocks(3,4) by converting the current values as a bit data, a column decoder and driver block(6) for selecting a column line of the flash memory array block(8) by the row address signal through receiving the voltage from the high voltage generation block(2), a row decoder and driver block(7) for selecting a row line of the flash memory array block(8) by a row address signal by receiving the voltage from the high voltage generation block(2) and the program/read control sequence block(1) for controlling the operations of the high voltage generation block(2), the first and the second data buffer blocks(3,4), the sense amplifier block(5), the column decoder and driver block(6) and the row decoder and driver block(7), respectively.

Description

FLASH MEMORY APPARATUS FOR MULTILEVEL AND SINGLELEVEL PROGRAM / READ}

The present invention relates to a multi-level and single-level program / lead flash memory device. In particular, when programming / reading a flash memory, a multilevel or singlelevel in one flash memory is provided. The present invention relates to a multi-level and single-level program / lead flash memory device that can be programmed and read by selecting.

In the case of the conventional singlelevel flash memory, the program / lead speed is faster than the multilevel flash memory, but there is a problem in that a larger capacity flash memory must be installed when the capacity is larger than the speed of the flash memory. .

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to use a multi-level memory program / lead when the speed is sufficient and the memory capacity is large even if the flash memory is programmed / readed at the multi-level. When the speed needs to be relatively high, the use of single level provides a multi-level and single-level program / lead flash memory device that can be selectively used as a multi-bit or single-bit flash memory according to the system specification.

1 is a block diagram of a multi-level and single-level program / lead flash memory device according to the present invention.

2 is a graph and chart showing threshold voltage (Vt) distribution and program / lead voltage of each level of a flash cell according to the present invention.

3 is a configuration diagram for multi-level or single-level program / read in accordance with the present invention

Explanation of symbols on the main parts of the drawings

1: Program / Lead Control Sequencer 2: High Voltage Generator

3: first data buffer section 4: second data buffer section

5: Sense amplifier block part 6: Column decoder and driver part

7: LOO decoder and driver unit 8: Flash memory array unit

Multi-level and single-level program / lead flash memory device of the present invention for achieving the above object is a high voltage generator for generating a voltage required to program / read the flash memory, and a multi-input to the program / read control sequencer unit A first data buffer section which accepts data to be programmed and read result data when the level select bit indicates a multilevel program / read operation, and which does not operate when the multilevel select bit indicates a single level program / read operation; It accepts data to be programmed and read result data when the multilevel select bit input to the program / read control sequencer indicates a multilevel program / lead operation, and is programmed when the multilevel select bit indicates a single level program / lead operation. Having data and results A second data buffer unit for receiving a second and the program / read control sequencer unit, and a sense amplifier block that reads a current value of a cell during read operation, converts it into bit data, and outputs the bit data to the first and second data buffer units. And a column decoder and driver for receiving a voltage from the high voltage generator and selecting a column line of a flash memory array unit by a column address signal, and receiving a voltage from the high voltage generator and receiving the voltage from the high voltage generator. A low decoder and driver unit selecting a row line of a flash memory array unit and a program / lead command including the multilevel selection bit are received to perform a multilevel or single level program / lead according to the information of the multilevel selection bit. The high voltage generator, the first and second data buffers , The sense amplifier is to block part, it characterized in that it includes a column decoder and driver unit, the Lawrence decoder and driver operation, each control program / read control sequencer section for the portion.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a flash memory device according to the present invention, which includes a program / read control sequencer 1, a high voltage generator 2, a first data buffer 3, a second data buffer 4, The sense amplifier block section 5, the column decoder and driver section 6, the row decoder and driver section 7, and the flash memory array section 8 are provided.

First, the high voltage generator 2 generates a voltage necessary for programming / reading a flash memory and supplies the voltage to the column decoder and driver unit 6 and the row decoder and driver unit 7.

The first data buffer section 3 operates when the multilevel select bit MSB input to the program / read control sequencer section 1 indicates a multilevel program / lead operation (when '1'). When the data to be read and the read result data are received and the multilevel select bit MSB indicates a single level program / lead operation (when '0'), it does not operate.

The second data buffer section 4 operates when the multilevel select bit MSB input to the program / read control sequencer section 1 indicates a multilevel program / read operation (when '1'). The data to be read and the result data to be read are received, and when the multilevel select bit MSB indicates a single-level program / read operation ('0'), the data to be programmed and the result data to be read are received.

The sense amplifier block unit 5 is controlled by the program / read control sequencer unit 1 and reads a current value of a cell during read operation and converts the current value into bit data so that the first and second data buffer units ( Output to 4).

The column decoder and driver unit 6 selects a column line (bit line) of the flash memory array unit 8 by a column address signal (Y-add), and the row decoder and driver unit 7 The row line (word line) of the flash memory array unit 8 is selected by the address signal X-add.

The program / read control sequencer unit 1 receives a program / lead command PRIS including a multilevel select bit MSB for selecting a multilevel or a single level, and receives the information of the multilevel select bit MSB. The high voltage generator 2, the first data buffer unit 3, the second data buffer unit 4, the sense amplifier block unit 5, and the like to perform a multilevel or single level program / lead. The operations of the column decoder and driver section 6 and the row decoder and driver section 7 are respectively controlled.

When the multilevel select bit MSB is '1', the word line and bit line voltages corresponding to the multilevel program / lead are sequentially generated to perform a multilevel program / lead operation, and the multilevel select bit MSB is If the value is '0', the word line and bit line voltages corresponding to the single level program / lead are sequentially generated to perform the single level program / lead operation.

Figure 2 shows the threshold voltage (Vt) distribution and the program / lead voltage of each level of the flash cell according to the present invention.

3 is a configuration diagram for multi-level or single-level program / lead, which includes a high voltage generator 2, a column decoder 6, a low decoder 7, a reference current generator 11, and a comparison unit. (12), a decoder (13) and a flash cell (14).

As shown, the reference current generator 11 receives the word line bias control signal WLBC [1: 0] and generates a reference current IRef, and the word line bias control signal WLBC [1: 0]. A high voltage generator 2 for receiving a high voltage, a comparator 12 for outputting a signal obtained by comparing the reference current IRef with a high voltage, and an output signal of the comparator 12; And a decoder unit 13 for generating data d1 to the first data buffer unit 3 and generating data d0 to the second data buffer unit 4, and an input / output disable control signal. A column decoder 6 for transmitting the high voltage generated by the high voltage generator 2 to one terminal of the flash cell 14 by the IODISAC, and a high voltage generated by the high voltage generator 2 A row decoder unit 7 is transmitted to the gate of the flash cell 14.

First, all the flash cells are recovered to be in the state programmed with the word line voltage Vwl0 after erasing, and are brought to the level 0 level.

In order to program in the flash memory, the program address and data must be accepted as inputs. If the multilevel select bit (MSB) is '1', twice as much data is received for one address as compared to '0'. In other words, for a program instruction having the multilevel select bit MSB of '1', the data bit number is twice as long as the number of data bits is '0', or if the multilevel select bit MSB is '1', it is '0' and data. The number of bits is the same, but two program commands should be input.

Therefore, when the multilevel select bit MSB is '0', only the second data buffer unit 4 of FIG. 1 is used, so that the program / read control sequencer unit 1 writes only to the second data buffer unit 4. While the enable control signal is applied, when the multilevel select bit MSB is '1', both the first and second data buffer units 3 and 4 are used, and thus the first and second data buffer units ( 3) Write enable control signal is sequentially applied to (4).

The program / lead control sequencer section 1 generates the word line bias control signal WLBC [1: 0] of FIG. 3 to generate respective word line voltages. The program / read control sequencer 1 generates the word line voltage Vwl3 of FIG. 2 when the multilevel select bit MSB is '0', thereby causing the row decoder and driver to be generated. The bit line voltage generated by the high voltage generator 2 is applied to the column decoder and the driver 6.

In this case, the program / read control sequencer 1 may include the column decoder and driver 6 so that a bit line voltage is not applied to an input / output IO whose data of the single-level select bit LSB is '1'. The input / output (IO) disable control signal IODISAC of FIG. 3 is generated to prevent voltage from being applied to the bit line of the flash cell by the column decoder and the driver unit 6.

The flash cell whose data is '0' goes up from level (Level0) to level (Level3).

When the multilevel select bit MSB is '1', the program is sequentially programmed from Level 1 to 3 three times. First, the high voltage generator 2 generates the word line voltage Vwl1 of FIG. As in 2, the input / output disable control signal IODISAC is generated for the input / output IO in which the input bit combination of the first data buffer unit 3 and the second data buffer unit 4 is '00'. do.

Finally, the word line voltage Vwl3 is generated and an input / output disable control signal IODISAC is generated for the input / output IO having a bit combination of '00', '01', and '10'.

In the read operation, if the multilevel select bit MSB is '0', the word / line bias control signal WLBC [1: is applied in the program / read control sequencer 1 so that the word line voltage Vwl1 is applied to a given row address. 0]), and compare the current of the cell with the reference current Iref to determine whether the flash cell is in the level (Level0) or level (Level3) state as shown in FIG. One bit (d0 in FIG. 2) is input to the second data buffer unit 4 through the second data buffer unit 4.

When the multilevel select bit MSB is '1', the word line bias control signal WLBC [1: 0] is sequentially generated to apply the word line voltage Vwl0 to a given row address. Determine whether it is in the level (Level1) state and then generate the word line bias control signal WLBC [1: 0] so that the word line voltage Vwl1 is applied next to determine whether it is in the level (Level1) state or the level (Level2) state. Finally, a word line bias control signal WLBC [1: 0] is generated so that the word line voltage Vwl2 is applied to discriminate the level (Level2) state from the level (Level3) state.

As shown in FIG. 3, the 2-bit data d1 and d0 are generated by the decoder using the third read result and the word line bias control signal WLBC [1: 0], and the first data buffer unit 3 and the first data buffer unit 3 are generated. Input to the second data buffer section 4 is made.

As described above, according to the multi-level and single-level program / lead flash memory device of the present invention, when a multi-level or single-level program / lead program / lead method is used, the multi-level is more than the single-level program / lead. It may take a long time, but if the flash memory is programmed / read in multiple levels, the speed is sufficient and if the memory capacity should be large, use multilevel, and if the memory program / read speed should be relatively fast, use single level. Depending on the specifications of the system, it can optionally be used as multibit or singlebit flash memory.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (1)

In the multi-level and single-level program / lead flash memory device, A high voltage generator for generating a voltage required to program / read the flash memory; It accepts data to be programmed and read result data when the multilevel select bit input to the program / read control sequencer indicates a multilevel program / lead operation, and does not operate when the multilevel select bit indicates a single level program / lead operation. A first data buffer section, Receives data to be programmed and read result data when the multilevel select bit input to the program / read control sequencer indicates a multilevel program / lead operation, and programs when the multilevel select bit indicates a single level program / lead operation. A second data buffer section for receiving data to be read and result data to be read; A sense amplifier block unit controlled by the program / read control sequencer unit and configured to read a current value of a cell during read operation, convert it into bit data, and output the bit data to the first and second data buffer units; A column decoder and driver unit for receiving a voltage from the high voltage generator and selecting a column line of a flash memory array unit by a column address signal; A row decoder and driver unit for receiving a voltage from the high voltage generator and selecting a row line of the flash memory array unit by a row address signal; The high voltage generator, the first and second data buffers to receive a program / lead command including the multilevel select bit and perform a multilevel or single level program / read according to the information of the multilevel select bit; And a program / lead control sequencer unit for controlling the operations of the sense amplifier block unit, the column decoder and driver unit, the row decoder and driver unit, respectively.