JPH1173785A - Multiple level memory device and data writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of relieves of error bits when one threshold voltage changes successively along the threshold voltage levels corresponding to the plural conditions that can be displayed by multiple bit data by changing only one of the corresponding data bits. SOLUTION: Suppose that a multiple level memory is provided with the threshold voltage levels distributing at a specified interval in correspondence to four possible states A-D which display two-bit multiple bit data. For example, based on technique 1, '11', '10', '00', '01' of bit data are successively allotted from the lowest threshold voltage level toward higher levels. When, for example, the threshold voltage level of the cell storing '10' ascends in external factors or reliability data, only one bit changes for the bit data corresponding to the former threshold level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a multi-level memory having a memory cell capable of selectively storing one of at least three possible data states. The present invention relates to an apparatus and a data writing method thereof.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices are important components in computer systems, digital handy terminals and the like. High density nonvolatile memory device,
Among them, flash EEPROM (electrically
erable programmable read only memory) device has higher programming speed and
With advantages such as lower power consumption, digital cameras and personal computers (P
C) as a large-capacity medium in an integrated circuit card (IC card) or the like, and instead of a hard disk.

The basic mechanism by which data is stored in a non-volatile memory is a memory cell. Many conventional memory technologies provide a storage capacity of up to one bit or two states per cell. Semiconductor memory cells having more than two possible states are well known in the art.

One flash memory cell has a control gate.
(controlgate), floating gate (floating gat
e) a single effect transistor including a source and a drain.
r: FET). Information is stored in the flash cell by changing the amount of charge on the floating gate such that the threshold voltage (Vt) of the flash cell is changed. Flash cells are read by applying a select voltage to the control gate through a word line. When a selection voltage is applied, the amount of current conducted by the flash cell is determined by the threshold voltage (Vt) of the flash cell.

[0005] Flash cells can theoretically have an independent and identifiable state for each electron applied to the floating gate. In essence, however, most flash cells traditionally rely on the flash cell structure, charge loss over time, and thermal issues and their inconsistencies when designing and the data stored in flash cells. Due to the inaccuracy of sensing the charge on the floating gate, which affects the ability to determine, there are two possible states. like this,
The two states are typically referred to as a programmed state and an erased state, and each state is referred to as a range of Vt volta.
ge). To determine the two possible states, the states are separated by a separation range, which is a predetermined range between the states corresponding to the threshold voltages.

When a flash cell is read, the threshold voltage Vt of the flash cell is compared with a reference flash cell having a threshold voltage Vt set to a reference voltage that is within the isolation range. As is well known in the art, a comparator typically compares a reference voltage with a threshold voltage Vt of a flash cell and outputs the result. Should the flash cell be programmed, the extra electrons will be trapped in the floating gate, and the threshold voltage of the flash cell will cause the selected flash cell to conduct less drain-source current than the reference flash cell To increase. Conventionally, the programmed state of a flash cell is generally indicated by a logic '0'. Conventionally, when a flash cell is erased, there are few or no extra electrons in the floating gate, and the flash cell conducts a greater drain source current than the reference flash cell. Conventionally, the erased state of a flash cell is generally indicated as logic '1'.

[0007] Assuming that the flash cell is initially in an erased state, the flash cell is programmed by arranging the charge on the floating gate such that the threshold voltage Vt of the flash cell is increased. A typical conventional flash cell has a source voltage applied to the source of the flash cell, a program voltage applied to the drain of the flash cell, and a control gate of the flash cell sufficient to change the amount of charge stored in the flash cell. By applying a voltage, it is programmed through hot electron injection. The source voltage is generally a system ground. The program operation is
Generally, it is controlled by a control engine or a write state machine. Other memory technologies program a memory cell by changing the amount of charge stored in a storage element similar to the floating gate of a flash cell.

A flash EEPROM device is generally classified into a NAND type device and a NOR type device in terms of a memory cell structure. Since the NOR structure memory has a structure in which each cell is independently connected to a bit line and a word line, it has an advantage that a corresponding cell is not much interfered by another cell during a write operation or a read operation of one cell. Have. However, since the NOR structure memory requires a contact for interconnecting each cell and its corresponding bit line, a plurality of cells are connected in series from the viewpoint of integration. Unit (u
nit), ie, a string, is disadvantageous when compared to a NAND structure memory that requires only one contact. Therefore, the highly integrated flash memory device mainly adopts the NAND structure.

An important prerequisite for mass storage devices is a low cost per bit. 2. Description of the Related Art Multi-bit flash EEPROM technology has been actively studied as a technology for storing a large number of bits of data in one memory cell in order to improve the integration degree of a flash memory device. Multi-bit EEPROMs are called multi-level or multi-state EEPROMs.

A technology capable of dramatically reducing the unit cost per bit of a flash EEPROM device was introduced in February 1995.
Moon, IEEE, ISSCCDigest of Technical Papers, pp132-133
M. Bauer et al., "A Multilevel-Cell 32Mb Flash
The flash memory device disclosed in the above-mentioned document is a device having a NOR-structured cell array, and the cell size decreases as the cell size decreases.
It has a bit or four state storage capacity.

In the flash memory device disclosed in the literature, data corresponding to the 4-bit 4-bit state is expressed as a binary system, which is "00", "01", "10", "11".
Where each data has a specific threshold voltage, for example, a threshold of 2.5V for data "00", 1.5V for "01", and -3V for "11". Voltages are each provided. Since each memory cell has a specific one of the four threshold voltages, binary data of 00, 01, 10, and 11 is stored in each memory cell. Such a multi-state flash memory device generally has two or more threshold voltage distributions and states corresponding to each threshold voltage.

In a multi-level cell (MLC) storing a plurality of data bits in one state, two or more data inputs are usually combined to form one independent state. Define. For example, assuming an MLC with four possible inputs / outputs having a structure of × 8, as described above, the states are “11” and “1”, respectively.
0, 01, and 00, and each state is a combination of two data outputs.
In the case of “11”, I / O 0 is “1” and I / O 1
Is also “1”, if “10”, I / O 2 is “
1 'and I / O 3 may be' 0 '. It is obvious to those who have acquired ordinary knowledge in this field that the combination for data input / output can be variously combined by cell data or circuit implementation method. In order to independently define at least two bits of multi-bit data into one state, the concept of combining other data outputs is widely applied to a semiconductor memory device implementing a multi-level cell (MLC). .

For convenience, in order to explain the conventional problem, a memory cell having one of four possible states is provided.
8 is a multi-level memory device having an input / output structure of 8, wherein a state stored in a cell is sensed by detecting a current or voltage difference depending on a threshold voltage of the cell to define one state. I do. In a cell having one of the four possible states, the threshold voltage of the cell is sequentially changed according to a threshold voltage distribution corresponding to each of the four possible states. Among the threshold voltages, the lowest voltage corresponds to “11”, the highest voltage corresponds to “00”, and the others correspond to “11” and “0”.
Let us define that "0" corresponds to the order of "10" and "01".

In such a case, when one state is defined by combining two inputs and outputs, that is, when two bits of data are stored in one cell, an electric stress or a temperature such as a reliability test may occur. If the threshold voltage of the cell changes due to stressing conditions or other external factors, the state stored in the cell, that is, its threshold voltage, changes. For example, "10"
If the threshold voltage of the cell corresponding to the state rises and is changed to the threshold voltage of the cell corresponding to the “01” state, a 2-bit change occurs in the input / output difference.
On the other hand, if the threshold voltage of the cell corresponding to the "10" state is lowered and changed to the threshold voltage of the cell corresponding to the "11" state, only one bit changes in the input / output difference.

In general, the threshold voltage of the cell does not change significantly due to the reliability test or external factors as described above. Therefore, the threshold voltage of the cell is usually set to be adjacent to the threshold voltage of the cell. In most cases, data of "01" or data of "10" is changed to data of "11". However, a change in the threshold voltage of the cell corresponding to the “10” state to the threshold voltage corresponding to the “01” state may occur. In this case, error check and correction (error check
In a multi-level memory device where the circuit is supported, if the above factors cause the threshold voltage (Vt) of the cell to be low and the two bits change relative to the bit in the previous state. , As compared with the case where only one bit changes in relation to the bit in the previous state, the overall number of times of error rescue is reduced.

[0016]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory cell having one of at least three or more states for displaying multi-bit data, when an external factor or a test is performed, the state of the cell is changed. An object of the present invention is to provide a multi-level memory device that changes only one bit among bits in a state changed in relation to a bit in a previous state when the state is changed to a contact state, and a data writing method thereof.

[0017]

According to one aspect of the present invention, as described above, at least three states, each of which can be represented by at least two bits of multi-bit data, each having a predetermined state. Each memory cell has one of the threshold voltage levels distributed in the interval, but corresponds to each possible state when the threshold voltage level of the memory cell is sequentially changed along the distributed threshold voltage level. Only one of the data bits is changed.

In this embodiment, the memory cells include electrically erasable and programmable flash EEPROM cells.

According to another feature of the present invention, at least two
An array of electrically erasable and programmable flash EEPROM cells having one of a plurality of threshold voltage levels distributed at predetermined intervals, each corresponding to at least three states representable by multi-bit data of bits; When the threshold voltage level of each cell is sequentially changed along the distributed threshold voltage level, during a write operation, a selected cell can be written to a voltage level that indicates one of the possible states during a write operation. The states in which only one bit of the data bits corresponding to the various states can be changed correspond to the threshold voltage levels, respectively, and correspond to the states stored in the selected cells during the read operation. Means for sensing the voltage level is included.

According to another feature of the present invention, at least two
An array of memory cells each having at least three states respectively corresponding to at least three states that can be displayed by multi-bit data of a bit, each of which is distributed at predetermined intervals and has a sequentially changed threshold voltage level; N
The multi-bit data obtained by dividing the bit information by a predetermined bit corresponds to each of the voltage levels, and one of the two states corresponds to one of the other states in relation to the possible states respectively corresponding to the two contacted voltage levels. Means for associating multi-bit data such that only one bit is changed between a bit in a changed state and a bit in a previous state when the state is changed to one state, and a multi-bit corresponding to a selected cell. Means for writing a voltage level corresponding to a data state is included.

In this embodiment, the memory cells include electrically erasable and programmable flash EEPROM cells.

In this embodiment, the n-bit information matches the data input / output structure of the semiconductor memory device.

According to another feature of the invention, at least two
A plurality of bit data, each of which corresponds to at least three possible states and has one of threshold voltage levels distributed at predetermined intervals, and includes an electrically erasable and programmable flash EEPROM cell. In a data writing method of a multi-level memory device, when a threshold voltage level of a cell is sequentially changed along a distributed threshold voltage level, one of the possible states corresponding to the voltage level corresponds to one. The data bits corresponding to one state and one adjacent to another state are written to the cell such that only one bit is changed to another.

According to the apparatus and the method, the threshold voltage is changed in a cell having one of the threshold voltages corresponding to at least three or more states indicating the multi-bit data, and the state before the change is made. , Only one bit among the bits in the state corresponding to the changed threshold voltage can be changed.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

FIG. 2 illustrates four possible states of the data bit arrangement method according to the present invention. Referring to FIG. 2, the present invention includes a memory cell having one of threshold voltage levels distributed at predetermined intervals, each of which corresponds to four possible states indicating at least two bits of multi-bit data. In a multi-level memory device, when an external factor or reliability test is performed, its threshold voltage level can be varied. In such a case, when the state is changed from one state to another state in terms of two states among the states corresponding to the threshold voltage levels, the bit of the previous state is compared with the bit of the next state. Then, the state is defined so that only one bit is changed separately.

In other words, assuming the state "11" corresponding to the lowest threshold voltage level, the lowest threshold voltage corresponding to the state is sequentially changed to correspond to the changed threshold voltage level. The next state bit to be compared with the previous state bit is 1
Assign the state so that only the bits are changed separately
(assign). According to an example of such a data bit allocation method, the four states are “11”, “10”, “00”, and “01” according to a sequentially changing threshold voltage level, as shown in FIG. Are sequentially changed. When the data bit of the state corresponding to the lowest voltage level among the states is assigned “10”, the four states are set to “1” according to the threshold voltage level.
0, “11”, “01”, “01” or “1”
The number is changed in the order of "0", "00", "01", "11".

Therefore, the threshold voltage level of a cell storing one state (eg, “10”) increases (eg, “00”) due to an external factor or reliability data.
Or lower (eg, “1”).
When changed to the corresponding voltage level (corresponding to a state of "1"), the bits of the state (e.g., "10") corresponding to the threshold voltage level before the change are changed to the changed threshold voltage level. (For example, “11” or “00”), but only one bit is changed separately.
, The number of rescue operations of a multi-level memory device that supports the above can be increased.

Referring again to FIG. 2, the components necessary to achieve the technical idea (or concept) according to the present invention are those of a multi-level memory device having a conventional memory. Therefore, the technical concept according to the present invention is not simply a circuit configuration itself, but rather information on a cell that determines an arbitrary state of a multi-level cell, for example, when allocating binary data in order of low or high threshold voltage. , The binary data bit during the contact state is 1
Assign if only the bits operate separately. When a device is designed through the technical idea according to the present invention, a program time and a program voltage corresponding to a possible state through a sense amplification of a multi-level memory device and a circuit for controlling the same (eg, a control engine or a write state machine) are determined. With the variability, what is possible is a fact that is obvious to those who have acquired a common knowledge in this technical field.

FIG. 3 schematically illustrates a multi-bit state having a state of X. Reference numeral 10 denotes an arbitrary one of the multi-bit states.
It consists of binary data. For example, an MLC having 3 or 4 states is composed of 2 bits such as "10", "11", "01", and the like, and an MLC having 5 to 8 states is "1".
11 ”,“ 110 ”, etc., which means three bits.

In the case of an MLC having four states, as shown in FIG. 1, the four states according to the prior art are 11-1.
The threshold voltages are sequentially assigned in the order of 0-01-00 so as to correspond to the respective threshold voltage levels. However, as shown in FIG. 2, there are eight methods in which only one bit is separately arranged between bits in the four states according to the technique of the present invention. When such a technical concept is applied to an MLC having three states, it is known that the MLC is arranged as shown in Table 1.

[0032]

Table 1 Case 1 11-10-00 Case 2 11-01-00 Case 3 10-11-01 Case 4 10-00-01 Case 5 01-11-10 Case 6 01-00-10 Case 7 00-01-11 Case 8000-100 -11 As can be seen from Table 1 and FIG. 2, when the threshold voltage level of the cell is varied along the sequentially changing threshold voltage level, the threshold voltage of the cell changes when an external factor or reliability test is performed. The bit in the previous state is 1 compared to the bit in the changed state.
It is common knowledge in the art that the concept or concept of the present invention in which only bits are changed is applied to a multi-level memory device including a memory cell having one of at least three possible states. Self-evident. It should be noted that not only the multi-level memory device based on the cell control related to the threshold voltage but also the multi-level cell in the semiconductor memory device applies the technical idea of the present invention.

FIG. 4 is a block diagram showing a configuration of a multi-level memory device according to a preferred embodiment of the present invention.

The multi-level memory device shown in FIG. 4 has at least n (n is a constant larger than 2;
= 4), the threshold voltage level is sequentially changed from a low level to four states (for example, 11-10).
-01-00 or 00-01-10-11) is an example in which the technical idea of the present invention is applied to a multi-level memory device designed to correspond to each. The memory cell array 10 shown in FIG.
0, row selecting circuit, ie, row selecting circuit
ircuit) 110, a column selection circuit or a column selection circuit (co
(lumn selecting circuit) 120, read and write control circuit
(read and write controlling circuit) 130, a sense amplifier circuit, that is, a sense amplifier circuit.
it) 140 and thermal gating circuit (Y-gating cir
The cuit) 150 is well known to those skilled in the art by performing the same role as those of a conventional multi-level memory device, and thus a description thereof will be omitted here.

The data conversion circuit shown in FIG.
When the four states according to the first method of FIG. 2 are arranged, that is, when the states are arranged in order of 11-10-00-01, the data input to “10” is changed to “00”. Convert the data input to “00” to “0”.
This is a case where the data is converted to "1". Since this circuit is also a well-known technique, its detailed circuit is not shown in the drawing. , The conversion circuit 160 converts this to “00”.

Row and column selection circuit 1 for decoding an externally applied address signal during a write operation
One memory cell is selected through 20 and 130,
The data converted through the write control circuit 130 and the sense amplifier circuit 140 is written to a selected cell. Here, as is well known in the art, when data to be written to a selected cell is "00" through a conversion circuit 160, a program operation and a verify operation are repeatedly performed to perform a write operation. The operation is performed. That is,
If the state is "00", it is established by repeating two program loops. Then, during the read operation,
The written data is sensed and amplified by the read control circuit 130 and the sense amplifier circuit 140, and the thermal gating circuit 15
0 is transmitted to the conversion circuit 160. As described above, when a write operation is performed, data “10” is changed to “00”.
When the read data is “00”, it is converted to “10” as originally input through the conversion circuit 160 and output to the outside.

It is known that the technical concept of the present invention is applied to a multilevel memory device having such a configuration.
Accordingly, even if the threshold voltage level of the cell rises or falls due to an external factor or a reliability test, the number of failed bits, that is, the number of changing bits is one, so that the multi-level supporting ECC is required. It is possible to increase the number of error relief operations of the memory device.

[0038]

As described above, among the threshold voltages corresponding to at least three or more states indicating the multi-bit data, the threshold voltage is changed in the cell having one, and the state before contact is changed. When the state is changed, it is possible to increase the number of repairs for the entire error bit of the multi-level memory device by changing only one bit among the bits corresponding to the changed threshold voltage. it can.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating states corresponding to cell threshold voltages in a conventional multi-level memory device.

FIG. 2 is a diagram illustrating a data bit arrangement method for four states according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating data bit data of a multi-level cell having a plurality of states according to the present invention;

FIG. 4 is a block diagram showing a configuration of a multi-level memory device having a data conversion circuit according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory cell array 110 row selection circuit 120 column selection circuit 130 read / write control circuit 140 sense amplifier circuit 150 thermal gating circuit 160 conversion circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Wong, Daesic, Korea, Seoul, Theochok, Jam on Dong, Hanshin 16-cha apartment 120-910

Claims (7)

[Claims] 1. A memory cell having one of threshold voltage levels corresponding to at least three states that can be displayed by at least two bits of multi-bit data and distributed at predetermined intervals, and A multi-level memory device, wherein when a threshold voltage level is sequentially changed along the distributed threshold voltage level, only one bit among data bits corresponding to each of the possible states is changed. 2. The multi-level memory device of claim 1, wherein said memory cells include electrically erasable and programmable flash EEPROM cells. 3. An electrically erasable and programmable flash having one of threshold voltage levels distributed at predetermined intervals, each flash corresponding to at least three states that can be represented by at least two bits of multi-bit data. An array of EEPROM cells and a voltage level that indicates one of the possible states during a write operation when a threshold voltage level of each of the memory cells is sequentially changed along a distributed threshold voltage level. The possible states are written to the selected cells, and among the data bits respectively corresponding to the possible states, only the possible states are changed such that only one bit is changed corresponding to the threshold voltage level and selected during the read operation. A multi-level memory device including means for sensing a voltage level corresponding to the stored state in a cell. 4. A memory cell having at least three states respectively corresponding to at least three states that can be represented by at least two bits of multi-bit data, each of which is distributed at a predetermined interval, and has one of sequentially changed threshold voltage levels. And n-bit information applied from the outside is divided into predetermined bits by multi-bit data corresponding to the respective voltage levels, but associated with the possible states respectively corresponding to the two contacted voltage levels. When two states are changed from one state to another state, the multi-bit data is corresponded so that only one bit is changed between the bit of the changed state and the bit of the previous state. And a means for writing a voltage level corresponding to the state of the multi-bit data corresponding to the selected cell. 5. The multi-level memory device according to claim 4, wherein said memory cells include electrically erasable and programmable flash EEPROM cells. 6. The multi-level memory device according to claim 4, wherein the n-bit information matches a data input / output structure of the semiconductor memory device. 7. Each of at least two bits of multi-bit data, each of which has at least three possible states, has one of threshold voltage levels distributed at predetermined intervals, and is electrically erased and programmed. A method of writing data in a multi-level memory device including possible flash EEPROM cells, wherein when a threshold voltage level of the cell is sequentially changed along the distributed threshold voltage level,
In the possible states respectively corresponding to the voltage levels, only one data bit corresponding to one state and one bit corresponding to another state are changed to another state. Writing data to a cell in a multi-level memory device.