經濟部中央標準局員工消費合作社印製 505857 3378pif.doc/002 A7 B7 五、發明説明（I ) 本發明是有關於記憶體領域，且特別是有關於一種 在多位元記憶體中安排碼位元的方法，其中之多位元記憶 體具有儲存選到之某一臨限電壓狀態的一記憶胞。 在電腦系統或可攜式終端機中，非揮發性記憶體元件 是較能有效達成可靠儲存功能的裝置。特別是快閃記憶 體，它是一種非揮發性記憶體元件，具有較快的程式化速 度及較低的消耗功率之優點，因此可應用在個人電腦的數 位靜態相機（digital still camera)與1C卡中，做爲大量儲存 的零件。 快閃記憶體的記憶胞是由具有一控制閘、一浮置閘、 一源極與一汲極結構的金氧半電晶體所組成，儲存在記憶 胞中之資訊狀態係由保留在浮置閘中的電荷所決定’該些 電荷會改變該記憶胞的臨限電壓。讀取儲存在記憶體中的 數據之方式是將一選擇電壓訊號透過對應的字元線施加予 控制閘，流經選到之記憶體的電流量是取決於初期程式化 的臨限電壓。典型的儲存型態分爲程式化與抹除兩種狀 態，程式化是將一程式化電壓施予一選擇之記憶胞的汲 極，且將一足夠高的電壓施予控制閘’以產生一熱電子射 入。而抹除是將一高電壓施予一選擇之記憶胞的底材 (bulk)，且將控制閘接地或接負電壓。當自一選擇的記憶 胞中讀取數據時，經由對應的字元線施加在控制聞上的讀 取電壓係在一最佳化的位準，該位準滿足一視§亥選擇的百己 憶胞而定之反偏條件，該選擇的記憶胞響應於該讀取電 壓，當抹除時，可以是導通的，而當程式化時’可以是不 4 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝·Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 505857 3378pif.doc / 002 A7 B7 V. Description of the Invention (I) The present invention relates to the field of memory, and in particular to a method for arranging code points in multi-bit memory Meta-method, in which the multi-bit memory has a memory cell that stores a selected threshold voltage state. In computer systems or portable terminals, non-volatile memory components are devices that are more effective at achieving reliable storage functions. Especially flash memory, which is a non-volatile memory element, has the advantages of faster programming speed and lower power consumption, so it can be used in digital still cameras and 1C of personal computers. Card, as a mass storage part. The memory cell of the flash memory is composed of a metal-oxide semiconductor with a control gate, a floating gate, a source, and a drain structure. The information status stored in the memory cell is retained in the floating state. The charge in the gate determines' these charges will change the threshold voltage of the memory cell. The way to read the data stored in the memory is to apply a selection voltage signal to the control gate through the corresponding word line. The amount of current flowing through the selected memory depends on the threshold voltage initially programmed. The typical storage type is divided into two states: stylized and erased. Stylized is to apply a stylized voltage to the drain of a selected memory cell, and apply a sufficiently high voltage to the control gate to generate a Hot electron injection. The erasure is to apply a high voltage to the substrate of a selected memory cell, and ground or control the control gate to a negative voltage. When reading data from a selected memory cell, the reading voltage applied to the control via the corresponding word line is at an optimized level, which meets the requirements of The reverse bias condition depends on the memory cell. The selected memory cell responds to the read voltage. When erased, it can be turned on, and when programmed, it can be different. This paper size is applicable to the Chinese National Standard (CNS). A4 specification (21〇X 297mm) (Please read the precautions on the back before filling this page)
、1T 505857 3378pif.doc/002 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（2 ) 導通的◦自選擇到的記憶胞感測到之電壓位準會與一參考 電壓位準比較，以決定一表示儲存在選擇到的記憶胞中之 邏輯値。 然而，由於加大快閃記憶體之儲存容量的需求增加， 爲了強化應用上的集積度與降低每一位元的成本’業界提 出了一種在一記憶胞中儲存某一多位元的技術’該技術稱 爲多位元或多階技術。眾所週知，一般快閃記憶體中之每 一記憶胞的儲存容量是一個或二個狀態的數據（此處之“狀 態”意指可以程式化之臨限電壓的可能情況），而熟習此藝 者也熟知在一記憶胞中儲存超過兩個狀態之數據的技術。 有一習知文獻提出了一種有效降低每一位元成本的方 法，其係由 M· Bauer 所發表，名爲 A Multilevel-Cell 32Mb Flash Memory(發表在 1995 年 2 月之 ISSCC Digest of Technical Papers的第132-133頁），其中，排列成非或型 矩陣的每一記憶胞可以儲存2或4個位元。Bauer的快閃 記憶體具有4對二位元：“00”、“01”、“10”與“11”，其相 對應的臨限電壓分別是2.5V、1.5V、0.5V與-3V，這些二 位元碼的組合均可在快閃記憶體的輸入/輸出端子上確 認。請參照第1圖，分布成如圖所示的形式之臨限電壓的 四個狀態分別表示一個二位元碼組合。 假設最低的臨限電壓（-3V)係對應於“U”，而最高的臨 限電壓(2.5V)係對應於“〇〇”(其餘的臨限電壓15V與〇.5V 分別對應於“10”與“01”），則因可靠度測試或來自外部的其 他環境影響所產生的電性與溫度應力（stress)，可能將臨限 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇χ297公釐） (請先閲讀背面之注意事項再填寫本頁)1T 505857 3378pif.doc / 002 A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Conducted ◦ The voltage level sensed by the selected memory cell will be equal to a reference voltage level Compare to determine a logical trance stored in the selected memory cell. However, due to the increased demand for increasing the storage capacity of flash memory, in order to strengthen the application density and reduce the cost of each bit, the industry has proposed a technology to store a certain number of bits in a memory cell. This technique is called multi-bit or multi-order technique. As everyone knows, the storage capacity of each memory cell in general flash memory is data of one or two states ("state" here means the possible situation of the threshold voltage that can be programmed), and those who are familiar with this art Techniques for storing data for more than two states in a memory cell are also well known. A well-known literature proposes a method to effectively reduce the cost of each bit, which is published by M. Bauer, named A Multilevel-Cell 32Mb Flash Memory (published in the ISSCC Digest of Technical Papers 132-133), where each memory cell arranged in a NOR matrix can store 2 or 4 bits. Bauer's flash memory has 4 pairs of bits: "00", "01", "10", and "11". The corresponding threshold voltages are 2.5V, 1.5V, 0.5V, and -3V. The combination of these two-digit codes can be confirmed on the input / output terminals of the flash memory. Please refer to Fig. 1. The four states of the threshold voltage distributed in the form shown in the figure respectively represent a two-bit code combination. It is assumed that the lowest threshold voltage (-3V) corresponds to "U" and the highest threshold voltage (2.5V) corresponds to "〇〇" (the remaining threshold voltages of 15V and 0.5V respectively correspond to "10" "And" 01 "), the electrical and temperature stress caused by reliability tests or other environmental influences from the outside may limit the paper size to the Chinese National Standard (CNS) A4 specification (21〇 χ297 mm) (Please read the notes on the back before filling this page)
505857 3378pif.doc/002 ΑΊ B7 經濟部中央標準局員工消費合作社印製 五、發明説明（,） 電壓的某一狀態改變或轉變成另一相鄰的狀態。關於臨限 電壓之碼組合自其預定的狀態改變成不期望的狀態一事， 兩種可能發生的改變情形是：碼組合中的兩個位元均改變 成它們的互補碼，例如“10”變成“01” ；以及碼組合中僅有 一個位元改變成它的互補碼，例如“10”變成“11”。基本上， 在碼組合之不期望的轉換中（或是臨限電壓的改變），大部 分較常見的情形是自“10”變成“01”以及自“10”變成“11”。 通常，典型的快閃記憶體具有一錯誤檢查與校正（error check and correction ; ECC)功能，可偵測失誤的數據位元 並於後將之修復成正確的位元，但是碼組合的完全改變， 例如“1〇”變成“01”，會使ECC功能所執行之更正一個位元 (one-Mt)變異的機會數減少。結果，雖然ECC功能可以自 我執行以防儲存在記憶胞中之數據位元改變，但由於預備 經由輸入/輸出端子讀取之碼組合的最糟變異之故，儲存 的多位元數據之可靠度會退化。 因此，本發明的主要目的就是在提供一種先進的安排 數據碼組合的方法，該數據碼組合對應於指定予一記憶胞 的某一臨限電壓。 本發明的另一目的是在提供一種方法，以強化多位元 記憶體中之數據的可靠度。 爲達成上述目的，本發明提出一種以對應記憶胞之多 個臨限電壓狀態的碼組合存取數據之方法，該方法至少包 括將一外部數據位元轉換成一碼組合的步驟，該碼組合與 相鄰之碼組合有--個位元不同。選擇到之記憶胞被設定一 (請先閲讀背面之注意事項再填寫本頁) 裝·505857 3378pif.doc / 002 ΑΊ B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (,) A certain state of voltage changes or changes to another neighboring state. Regarding the change of the threshold voltage code combination from its predetermined state to an undesired state, two possible change scenarios are: both bits in the code combination are changed to their complementary codes, for example "10" becomes "01"; and only one bit in the code combination is changed to its complementary code, such as "10" becomes "11". Basically, in the unintended conversion of the code combination (or the change of the threshold voltage), most of the more common situations are from "10" to "01" and from "10" to "11". Generally, typical flash memory has an error check and correction (ECC) function, which can detect erroneous data bits and then repair them to the correct bits, but the code combination is completely changed For example, "10" becomes "01", which reduces the number of chances of performing one-Mt mutation correction performed by the ECC function. As a result, although the ECC function can perform itself to prevent the data bits stored in the memory cell from changing, the reliability of the multi-bit data stored is due to the worst variation of the code combination to be read via the input / output terminal. Will degenerate. Therefore, the main object of the present invention is to provide an advanced method for arranging data code combinations corresponding to a certain threshold voltage assigned to a memory cell. Another object of the present invention is to provide a method for enhancing the reliability of data in a multi-bit memory. To achieve the above object, the present invention proposes a method for accessing data by using a code combination corresponding to multiple threshold voltage states of a memory cell. The method includes at least the steps of converting an external data bit into a code combination. The code combination and Adjacent code combinations have different bits. The selected memory cell is set up (please read the precautions on the back before filling this page).
、1T 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 505857 3378pif.doc/002 八7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（f) 對應於轉換的碼組合之臨限電壓，利用相鄰碼組合間之一 個位元不同的差異，解決習知ECC功能無法完全修復一 位元失誤的問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示一種習知多位元記憶體中對應於記憶胞的 臨限電壓之形式圖； 第2圖繪示依據本發明之四種臨限電壓狀態與對應於 該四種臨限電壓狀態之碼位元的安排形式圖； 第3圖進一步繪示依據本發明之臨限狀態與各種碼位 元的組合安排形式圖；以及 第4圖繪示依據本發明之一種記憶體的功能性結構 圖。 在圖中，相同的參考數字是代表相同或相對應的部 分。 圖式之標記說明： 100 :記憶胞陣列 110 :列選擇電路 120 :行選擇電路 130 :讀/寫控制電路 140 :感測放大器 150 ·· Y 聞 7 (請先閱讀背面之注意事項再填寫本頁) •裝_、 1T This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 505857 3378pif.doc / 002 8 7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (f) Corresponding to the conversion The threshold voltage of the code combination utilizes the difference in one bit between adjacent code combinations to solve the problem that the conventional ECC function cannot completely repair a single bit error. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 A form diagram of a threshold voltage corresponding to a memory cell in a conventional multi-bit memory is shown. FIG. 2 shows four threshold voltage states and code positions corresponding to the four threshold voltage states according to the present invention. FIG. 3 is a diagram showing a combination arrangement form of a threshold state and various code bits according to the present invention; and FIG. 4 is a functional structure diagram of a memory according to the present invention. In the figures, the same reference numerals represent the same or corresponding parts. Legend of the diagram: 100: Memory cell array 110: Column selection circuit 120: Row selection circuit 130: Read / write control circuit 140: Sense amplifier 150 ·· Y smell 7 (Please read the precautions on the back before filling in this Page) • installed_
、1T 一線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1 505857 3378pif.doc/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（？） 160 :轉換器 實施例 第2圖繪示的是本發明之多位元數據碼組合的安排方 式，其假設碼組合係由兩個二進位位元（或兩個位元狀態) 組成，且四個碼組合的狀態係對應於同一記憶胞中之四個 可能的臨限電壓狀態：狀態A、B、C與D。請參照第2 圖，碼組合的安排規則是相鄰的組合只有一個位元不相 同。 當最低的臨限電壓（例如-3V)被指定給碼組合“11”時， 則碼組合的排列次序是“11”、“10”、“00”與“01”(方法1) 或“11”、“01”、“00”與“10”(方法2)。其他的可能情況是 當碼組合“10”係設定爲一記憶胞的最低臨限電壓時，則碼 組合的排列次序是“10”、“11”、“01”與“00”(方法3)或 “10”、“00”、“01”與“11”(方法4)。同樣的方法，碼組合 的可能排列次序有“01”、“11”、“10”與“00”(方法5)或 “01”、“00”、“10” 與“11”(方法 0);以及“00”、“0Γ’、“1Γ， 與“10”(方法 7)或“00”、“10”、“11” 與“01”(方法 8)。 換句話說，當碼組合中之一所指派的是最高的臨限電 壓時，碼組合的排列方法仍可比照前述方式辦理。 應了解的是實施例可稍作變化，當只有三種臨限電壓 狀態應用在一多位元記憶體時，則存取碼組合的排列會至 第二順位的碼組合止，例如，以“ 11”爲首的排列即是“ 11”、 “10”與“〇〇”(“〇〇”是次序排列的結尾）。 第3圖繪示的是一種當組成碼組合的位元數大於前述 8 本紙張尺度適用中國國家標準（CNS) A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁} •裝· 、可 505857 3378pif.doc/002 五、發明説明（6) 的兩個時之碼組合的擴充排列方式。五到八種臨限電壓狀 態需要三個位元組成碼組合，例如“111”或“110”，而四種 狀態則只需兩個位元。 假設碼組合“111”係設定爲八個狀態中的最低臨限電 壓時，則碼組合的排列次序是“111”、“110”、“100”、“000”、 “010”、“011”、“001”與“10Γ’，或“111”、“011”、“001”、“000”、 “010”、“110”、“100”與“101”。另一以“100”爲首的排列次 序是“100”、“110”、“111”、“011”、“010”、“000”、“001” 與“101”，或“100”、“101”、“111”、“110”、“010”、“011”、 “001”與“000”。同樣地，其他的碼組合排列方式可依此類 推。 . 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 第4圖繪示執行本發明所提出之前述功能的記憶體結 構，其以相對應於四種臨限電壓狀態之四個碼組合“11”到 “〇〇”爲例。請參照圖4，基本上組成一多階記憶體的典型 零件包括有記憶胞陣列100、列選擇電路110、行選擇電 路120、讀/寫控制電路130、感測放大器電路140與Y閘 電路150，而數據轉換電路160的功能是安排碼組合，例 如自“11”排列到“10”、自“00”排列到“01”、自“11”排列到 “01”等等。轉換器160中的碼轉換機制是此藝者所熟知的， 且其能將前述之碼組合以相鄰兩碼組合間只有一個位元是 不同的規則排列之。 在讀取操作時，記憶胞係由列與行選擇電路110與 120、讀/寫控制電路130與感測放大器電路140選擇之， 其中，列與行選擇電路110與120會分解供給自外部的記 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 505857 3378pif.doc/002 A7 五、發明説明（1 ) 憶胞位址選擇訊號，而讀/寫控制電路130與感測放大器 電路140係將轉換自轉換器160的數據存入被選到的記憶 胞。在寫入操作中，當外部數據位元碼是“1〇”，且程式化 和確認週期能被設計成程式化週期的兩倍時，欲儲存在被 選到的記憶胞中之數據碼組合會以“〇〇”的形式自轉換器 160中產出，以達成本發明所揭露的排列方式。然後，讀 取在寫入操作中存入的數據時，碼組合“〇〇”的數據會經由 讀/寫控制電路130、感測放大器電路140與Y閘電路150 傳輸至轉換器160，而後被復原爲原始碼“10”。 如上所述，因爲本發明之記憶體能將一多位元記憶胞 之臨限電壓狀態對應的相鄰碼組合之位元失誤，控制在一 個位元的變異之下，故ECC功能的效率得以提昇且數據 的可靠度得以強化。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁)、 1T line paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 1 505857 3378pif.doc / 002 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (?) 160: Converter The second figure of the embodiment shows the arrangement of the multi-bit data code combination of the present invention. It is assumed that the code combination is composed of two binary bits (or two bit states), and the combination of four codes The states correspond to four possible threshold voltage states in the same memory cell: states A, B, C, and D. Please refer to Figure 2. The rule for the arrangement of code combinations is that only one bit of the adjacent combination is different. When the lowest threshold voltage (for example, -3V) is assigned to the code combination "11", the order of the code combination is "11", "10", "00", and "01" (Method 1) or "11" "," 01 "," 00 ", and" 10 "(Method 2). Other possible situations are when the code combination "10" is set to the minimum threshold voltage of a memory cell, then the order of the code combination is "10", "11", "01" and "00" (Method 3) Or "10", "00", "01", and "11" (Method 4). In the same way, the possible permutations of code combinations are "01", "11", "10" and "00" (Method 5) or "01", "00", "10" and "11" (Method 0) ; And "00", "0Γ '," 1Γ, and "10" (Method 7) or "00", "10", "11", and "01" (Method 8). In other words, when one of the code combinations is assigned the highest threshold voltage, the method of arranging the code combinations can still be handled in the same manner as described above. It should be understood that the embodiment may be slightly changed. When only three threshold voltage states are applied in a multi-bit memory, the arrangement of the access code combination will be the second code combination. For example, the “11 "" Is the "11", "10", and "〇〇" ("〇〇" is the end of the sequence). Figure 3 shows a type when the number of bits that make up the code combination is greater than the aforementioned 8. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page. } • Installation · 505857 3378pif.doc / 002 V. Expanded arrangement of two-time code combinations in the description of the invention (6). Five to eight threshold voltage states require three bits to form a code combination, such as " 111 "or" 110 ", and only two bits are required for the four states. Assuming that the code combination" 111 "is set to the lowest threshold voltage among the eight states, the order of the code combinations is" 111 ", "110", "100", "000", "010", "011", "001" and "10Γ '", or "111", "011", "001", "000", "010", "010" 110 "," 100 ", and" 101 ". The other sorting order starting with" 100 "is" 100 "," 110 "," 111 "," 011 "," 010 "," 000 "," 001 " Same as "101", or "100", "101", "111", "110", "010", "011", "001" and "000". The same Other code combinations and arrangements can be deduced by analogy.. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Figure 4 shows the implementation of the aforementioned functions proposed by the present invention. The memory structure is based on four code combinations "11" to "〇〇" corresponding to the four threshold voltage states as an example. Please refer to FIG. 4. The typical parts that basically constitute a multi-level memory include: The memory cell array 100, the column selection circuit 110, the row selection circuit 120, the read / write control circuit 130, the sense amplifier circuit 140 and the Y gate circuit 150, and the function of the data conversion circuit 160 is to arrange a code combination, for example, from "11" Arrange to "10", "00" to "01", "11" to "01", etc. The code conversion mechanism in the converter 160 is well known to the artist, and it can convert the aforementioned The code combination is arranged with only one bit that is different between two adjacent code combinations. During a read operation, the memory cell system consists of column and row selection circuits 110 and 120, read / write control circuit 130, and sense amplifier circuit. 140 of them, of which The column and row selection circuits 110 and 120 will be decomposed and supplied from the outside. 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 505857 3378pif.doc / 002 A7 5. Description of the invention (1) The memory cell address selection signal, and the read / write control circuit 130 and the sense amplifier circuit 140 store the data converted from the converter 160 into the selected memory cell. In the write operation, when the external data bit code is "10" and the programming and confirmation cycle can be designed to be twice the programming cycle, the data code combination to be stored in the selected memory cell It will be output from the converter 160 in the form of "〇〇" to achieve the arrangement disclosed by the invention. Then, when the data stored in the write operation is read, the data of the code combination “〇〇” is transmitted to the converter 160 via the read / write control circuit 130, the sense amplifier circuit 140, and the Y gate circuit 150, and is then Revert to the original code "10". As mentioned above, because the memory of the present invention can control the bit errors of adjacent code combinations corresponding to the threshold voltage state of a multi-bit memory cell under the variation of one bit, the efficiency of the ECC function is improved. And the reliability of the data has been enhanced. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 (210X 297 mm) (Please read the precautions on the back before filling this page)